CN205657052U - Face down chip - Google Patents
Face down chip Download PDFInfo
- Publication number
- CN205657052U CN205657052U CN201620384883.5U CN201620384883U CN205657052U CN 205657052 U CN205657052 U CN 205657052U CN 201620384883 U CN201620384883 U CN 201620384883U CN 205657052 U CN205657052 U CN 205657052U
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- semiconductor chip
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- board unit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
The utility model discloses a face down chip, including semiconductor chip and base plate unit, semiconductor chip's surface includes first surface and second surface, be formed with a connecting terminal on the first surface, the base plate unit includes third surface and fourth surface, the third is formed with the 2nd connecting terminal on the surface, semiconductor chip's first surface with the relative setting just in third surface of base plate unit a connecting terminal with the welding of the 2nd connecting terminal together, semiconductor chip's surface is formed with the encapsulated layer, and at least part the second surface exposes. In this way, the utility model discloses can improve semiconductor chip's heat -sinking capability.
Description
Technical field
This utility model relates to technical field of semiconductors, particularly relates to a kind of flip-chip.
Background technology
Interconnection technique is one of key technology in microelectronics Packaging, and microelectronics Packaging product quality, efficiency and cost are had significant impact, mainly includes wire bonding and two kinds of encapsulation technologies of flip-chip (Flip chip).Flip-Chip Using has high density, high-performance and compact feature, it is possible to such that packaging cost is lower, easily realize stacked chips and three-dimension packaging technique, it has also become the main development of encapsulation technology finds.
As shown in Figure 1, flip-chip packaging techniques is mainly deposition tin-lead ball 13 in the action face of chip 11, then the action face of chip 11 is overturn down and heat to utilize melted tin-lead ball 13 to combine with the circuit on base board unit 12 or other carrier, circuit board etc. or pin, thus realize the combination of chip 13 and base board unit 12 element such as grade.After chip 11 and base board unit 12 are combined, it usually needs chip 11 is carried out plastic packaging, thus forms encapsulated layer 14 on the surface of chip 11, to protect chip 11 and base board unit 12, improve the stability of chip 11.
But, in existing flip-clip, the whole the most packed layer of chip 11 14 wraps up, and causes the heat of chip 11 to be only capable of by tin-lead ball 13 and via base board unit 12 and outwards dispels the heat, and it greatly have impact on the electric heating property of chip 11, is unfavorable for the heat radiation of chip 11.
Utility model content
This utility model is mainly solving the technical problems that provide a kind of flip-chip, it is possible to increase the heat-sinking capability of flip-chip so that flip-chip better heat-radiation effect.
For solving above-mentioned technical problem, the technical scheme that this utility model uses is: provide a kind of flip-chip, including semiconductor chip and base board unit；The surface of described semiconductor chip includes first surface and second surface, the first connection terminal it is formed with on described first surface, described base board unit includes the 3rd surface and the 4th surface, being formed with the second connection terminal on described 3rd surface, the first surface of described semiconductor chip and the 3rd surface of described base board unit are oppositely arranged and described first connection terminal and described second connects terminal soldering and is connected together；Wherein, the surface of described semiconductor chip is formed with encapsulated layer, and at least part of described second surface exposes.
Wherein, the described second surface of exposure is formed with heat dissipating layer.
Wherein, it is formed with Underfill layer between first surface and the 3rd surface of described base board unit of described semiconductor chip.
Wherein, described first connects terminal includes that metal salient point and solder layer, described metal salient point are connected with the first surface of described semiconductor chip, and described solder layer is formed on described metal salient point.
Wherein, described first connection terminal is spherical stannum ball or the pedestal of column.
The beneficial effects of the utility model are: be different from the situation of prior art, in flip-chip of the present utility model, the first surface of semiconductor chip and the 3rd surface of base board unit is oppositely arranged and on semiconductor chip first connection terminal and base board unit the 3rd surface on second connection terminal soldering be connected together, thus realize the combination of semiconductor chip and base board unit, by making at least part of second surface of semiconductor chip expose, so that semiconductor chip is dispelled the heat by the second surface exposed, it is thus possible to improve the heat-sinking capability of semiconductor chip, make the better heat-radiation effect of semiconductor chip.
Further, this utility model, by being formed with heat dissipating layer on the second surface exposed, can improve the radiating effect of chip further.
Accompanying drawing explanation
Fig. 1 is the encapsulating structure schematic diagram of a kind of semiconductor chip of prior art；
Fig. 2 is the flow chart of method for packing one embodiment of this utility model flip-chip；
Fig. 3 is the flow chart of method for packing one embodiment of this utility model flip-chip, shows the corresponding structural representation of each step in figure；
Fig. 4 is in method for packing one embodiment of this utility model flip-chip, the structural representation of semiconductor chip；
Fig. 5 is in method for packing one embodiment of this utility model flip-chip, carries out the schematic diagram of underfill between semiconductor chip and base board unit；
Fig. 6 is in method for packing one embodiment of this utility model flip-chip, forms the flow chart of plastic packaging layer, show the structural representation that each step is interdependent in figure on the surface of semiconductor chip；
Fig. 7 is in method for packing one embodiment of this utility model flip-chip, forms the schematic diagram of heat dissipating layer on the second surface of the exposure of semiconductor chip；
Fig. 8 is the flow chart of the another embodiment of method for packing of this utility model flip-chip, shows the corresponding structural representation of each step in figure；
Fig. 9 is the structural representation of this utility model flip-chip one embodiment；
Figure 10 is the structural representation of this utility model another embodiment of flip-chip.
Detailed description of the invention
Elaborate concrete details in the following description to fully understand this utility model.But this utility model can be different from other modes described here implement with multiple, those skilled in the art can do similar popularization in the case of this utility model intension.Therefore this utility model is not limited by following public detailed description of the invention.
For the defect mentioned in background technology, this utility model provides the method for packing of a kind of flip-chip.Below in conjunction with drawings and embodiments, this utility model is described in further detail.
Refering to Fig. 2, in method for packing one embodiment of this utility model flip-chip, described method specifically includes following steps:
Step S201: semiconductor chip and base board unit are provided, the surface of semiconductor chip includes first surface and second surface, being formed with the first connection terminal on first surface, base board unit includes the 3rd surface and the 4th surface, the 3rd surface being formed with the second connection terminal.
Wherein, in conjunction with step S301 of Fig. 3, it is provided that semiconductor chip 31 and base board unit 32.Semiconductor chip 31 is chip to be packaged, and the surface of semiconductor chip 31 includes first surface 311 and second surface 312, as it is shown on figure 3, one of them surface that first surface 311 is semiconductor chip 31, it has circuit structure.Being formed with the first connection terminal 411, wherein four first connection terminals 411 shown in figure on first surface 311, first connects terminal 411 is electrically connected with the circuit structure (not shown) in semiconductor chip 31.
Base board unit 32 is the carrier of semiconductor chip 31, such as, can be circuit board.Base board unit 32 includes the 3rd surface 321 and fourth surface 322 relative with the 3rd surface 321.It is formed with the second connection terminal 412 as signal input on 3rd surface 321, the 4th surface 322 is formed the 3rd connection terminal 413 as signal output.Second connection terminal 412 and the 3rd connection terminal 413 are electrically connected to each other, and second connects the annexation between terminal 412, between the 3rd connection terminal 413 and between the second connection terminal 412 and the 3rd connection terminal 413 can need be determined according to side circuit, illustrates only as a kind of example in figure.
Step S202: the first surface of semiconductor chip and the 3rd surface of base board unit are oppositely arranged and are made the first connection terminal and second connect terminal soldering and be connected together.
In conjunction with step S302 shown in Fig. 3, semiconductor chip 31 is inverted on base board unit 32, make the on semiconductor chip 31 first connection terminal 411 be connected terminal 412 with second on base board unit 32 to weld, to realize the first connection terminal 411 and electric connection of the second connection terminal 412.
Wherein, first connect terminal 411 can after picking scaling powder second being connected terminal 412 and interconnect with base board unit 32；Can also be first by non-conductive adhesive (Non-Conductive Paste, NCP) on the surface of base board unit 32, make the first connection terminal 411 of semiconductor chip 31 be connected terminal 412 with the second of base board unit 32 by the mode of thermocompression bonding (Thermal Compress Bonding, TCB) and realize interconnection.
Step S203: form plastic packaging layer on the surface of semiconductor chip, and expose the second surface of semiconductor chip.
In conjunction with step S303 shown in Fig. 3, after semiconductor chip 31 and base board unit 32 are combined, semiconductor chip 31 is carried out plastic packaging and forms plastic packaging layer 33, and expose the second surface 312 of semiconductor chip 31.Wherein, first surface 311 having circuit structure, for the front of semiconductor chip 31, second surface 312 is the back side of the vis-a-vis with semiconductor chip 31.
In present embodiment, plastic packaging layer 33 is as the encapsulated layer of semiconductor chip 31, and it uses epoxide resin material to be formed, i.e. capsulation material is epoxide resin material.Certainly, in other embodiments, encapsulated layer can also use the materials such as pottery to be formed.
Wherein, the back side (i.e. second surface 312) of semiconductor chip 31 is exposed, and the side of semiconductor chip 31 and first surface 311 are plastic packaging layer 33 and are wrapped up.Further, the space between first surface 311 and the 3rd surface 321 of base board unit 32 of semiconductor chip 31 is also filled by plastic packaging layer 33.
Present embodiment, by exposing as the second surface 312 at semiconductor chip 31 back side, distribute so that the heat of semiconductor chip 31 connects terminal 412 not only by the second of base board unit 32 via base board unit 32, and can be dispelled the heat by the second surface 312 exposed, thus substantially increase the heat-sinking capability of semiconductor chip 31, make the radiating effect of semiconductor chip 31 more, be conducive to improving the stability of circuit.
Wherein, in a kind of possible embodiment, refering to Fig. 4, the first connection terminal 411 is pedestal, can be the structure of metal salient point (stud the bond)+solder that bonding technology is formed.Wherein it is possible to form bond wire salient point 4111 in advance on pad, and make to be formed on metal salient point 4111 solder layer 4112, thus form the first connection terminal 411.When the first surface 311 of semiconductor chip 31 and the 3rd surface 321 of base board unit 32 are oppositely arranged, first connects the solder layer 4112 of terminal 411 contacts with the second connection terminal 412 on the 3rd surface 321, thus by reflow soldering process, the solder layer 4112 on metal salient point 4111 is melted, and then metal salient point 4111 and the second connection terminal 412 are welded together, thus realize semiconductor chip 31 and the interconnection of base board unit 32.In another embodiment, it is also possible to connect second and on terminal 412, form metal salient point, then realize being connected terminal 411 phase with the first of semiconductor chip 31 by the metal salient point on the second connection terminal 412 and interconnect.By making the first or second connection terminal form metal salient point to realize base board unit 32 and the interconnection of semiconductor chip 31, by increasing capacitance it is possible to increase the space height between semiconductor chip 31 and base board unit 32, thus it is prone to the filling of plastic packaging material in plastic package process.
Certainly, in other embodiments, the first connection terminal 411 can also be the spherical stannum ball (solder ball) formed by solder, it is also possible to be the solder bump (pillar bump) etc. of column.
Wherein, in this utility model one embodiment, flip-chip link uses TCB/NCP technique, and the gap between base board unit 32 and semiconductor chip 31 is filled for NCP before carrying out plastic packaging.Specifically, as it is shown in figure 5, and combine Fig. 3, after step S302, and before step S303, including step: the space between first surface 311 and the 3rd surface 321 of base board unit 32 of semiconductor chip 31 is carried out NCP underfill, to form Underfill layer 34.
In other embodiments, it would however also be possible to employ some glue mode carries out underfill.Certainly, when spacing between semiconductor chip 31 and base board unit 32 is bigger, beneficially capsulation material flows into the space between semiconductor chip 31 and base board unit 32, therefore can not carry out underfill, but directly chip be carried out plastic packaging.
When spacing between semiconductor chip 31 and base board unit 32 is less, can can reduce and cause the probability of interior void by the space between semiconductor chip 31 and base board unit 32 first being carried out underfill because the material of plastic packaging layer 33 is difficult to fill up the space between first surface 311 and the 3rd surface 321 of base board unit 32 of semiconductor chip 31.
After completing underfill, perform step S303 so that semiconductor chip 31 is carried out plastic packaging.
In this utility model one embodiment, refering to Fig. 6, in figure, the element effect of identical label is identical, in encapsulation process, the second surface 312 of semiconductor chip 32 can be made to expose by arranging glued membrane 50a.Specifically, the surface of semiconductor chip 31 is formed the step of plastic packaging layer 33, farther includes:
Step S601: under the upper mold 50b matched moulds of plastic package die before pressure, arrange one layer of barrier layer in upper mold 50b, described barrier layer is for having resilient glued membrane 50a.Certainly, in other embodiments, barrier layer can also be the baffle plate of other materials.
Pressing is carried out by glued membrane 50a between upper mold 50b of step S602: be pressed together on the second surface 312 of semiconductor chip 31 by the upper film 50b being provided with glued membrane 50a, i.e. plastic package die and semiconductor chip 31.Thus glued membrane 50a is arranged on the second surface of semiconductor chip 31.
Step S603: capsulation material is filled in the space between glued membrane 50a and the 3rd surface 321 of base board unit 32, and solidifies capsulation material to form plastic packaging layer 33.
Step S604: remove upper mold 50b and glued membrane 50a, to expose the second surface 312 of semiconductor chip 31.
In present embodiment, by arranging one layer of glued membrane 50a on the second surface 312 of semiconductor chip 31, thus can stop that during plastic packaging capsulation material is spilled on this second surface 312, therefore can avoid being formed on second surface 312 plastic packaging layer 33.In addition, the glued membrane 50a of present embodiment has elasticity, therefore the upper film 50b of plastic package die can be pressed on glued membrane 50a, glued membrane 50a can be fitted tightly with the second surface 312 of semiconductor chip 31, capsulation material is avoided to overflow to this second surface 312 further, the most on the one hand the elasticity of glued membrane 50a itself can be utilized to absorb the height tolerance after solving different flip-chip, on the other hand absorb the stress of upper film 50b to prevent upper film 50b from being damaged by pressure by semiconductor chip 31.
In the above-described embodiment, by arranging glued membrane 50a to stop capsulation material to cover the second surface 312 relative with first surface 311, so that the second surface 312 relative with first surface 311 exposes, in other embodiments of this utility model, it is also possible to expose second surface 312 by other means.Such as, in the case of being not provided with glued membrane 50a, the plastic packaging layer on second surface 312 can be removed by techniques such as grinding or chemical attacks, thus expose second surface 312.
In addition, as shown in Figure 6, the second surface 312 exposed is the whole back side relative with first surface 311, in other embodiments, can also be only to expose a part of second surface 312, and the shape exposing second surface 312 can be trapezoidal, circular or irregularly shaped etc..
In the another embodiment of this utility model, in order to improve the heat-sinking capability of semiconductor chip 31 further, refering to Fig. 7, after step S303 shown in Fig. 3, it also can farther include following steps: forms heat dissipating layer 35 on the second surface 312 exposed.Wherein, heat dissipating layer 35 can use the aluminium material with preferable heat dispersion.
With continued reference to Fig. 7, after the surface of semiconductor chip 31 forms the step of plastic packaging layer 33, also comprise the steps: to form pedestal 414 on the 3rd connection terminal 413 of base board unit 32, and then form similar ball array encapsulation (Ball Grid Array, BGA) encapsulation of profile, then be interconnected with next layer of assembling.Wherein pedestal 414 can be spherical soldered ball, or column soldered ball etc., it is also possible to it is the coalition of metal salient point+solder.In other embodiments, if the 3rd connection terminal 413 of base board unit 32 is directly interconnected with next layer of assembling as signal terminal, form similar grid array encapsulation (Land Grid Array, LGA) encapsulation of profile, then form pedestal 414 without connecting the 3rd on terminal 413.
In the above-described embodiment, as a kind of example, each figure illustrate only the process encapsulating its required semiconductor chip on a base board unit.In order to improve production efficiency, in actual production, it is common that multiple base board units to be encapsulated its required semiconductor chip simultaneously.
When multiple base board units to be encapsulated its required semiconductor chip simultaneously, this utility model method for packing is achieved in that refering to Fig. 8, Fig. 8 is the flow chart of the another embodiment of method for packing of this utility model flip-chip, and wherein in figure, the element effect of identical label is identical.In the present embodiment, method for packing comprises the steps:
In step S801, it is provided that several semiconductor chips 31 and substrate 70, wherein substrate 70 is mother substrate, and it includes several base board units 32.There is between base board unit 32 cutting zone 71.
For example, one piece circuit board of one of them base board unit 32, for packaged semiconductor, and other circuit components can also be packaged with on base board unit 32, such as passive device etc., on the most each base board unit 32, the semiconductor chip 31 of encapsulation can be single can also be many, specifically can be determined by actual circuit structure.As a kind of example, figure showing, semiconductor chip 31 correspondence is encapsulated on a base board unit 32, and for convenience of description, figure only illustrates two semiconductor chips 31 and includes the substrate 70 of two base board units 32.
In step S802, semiconductor chip 31 and corresponding base board unit 32 are welded together.
In step S803, under the upper mold 50b matched moulds of plastic package die before pressure, upper mold 50b arranges one layer of glued membrane 50a, and the upper film 50b being provided with glued membrane 50a is pressed together on the second surface 312 of semiconductor chip 31.
In step S804, capsulation material is filled in the space between glued membrane 50a and the 3rd surface 321 of base board unit 32, and solidification capsulation material is to form plastic packaging layer 33 afterwards.
In step S805, remove film 50b and glued membrane 50a, to expose the second surface 312 of semiconductor chip 31.
Step is in 806, cuts the cutting zone 71 of substrate 70 with separating base plate unit 32, thus obtains the encapsulating structure of several independent semiconductor chips 31.Afterwards, the second surface 312 exposed forms heat dissipating layer 35, to improve the heat-sinking capability of semiconductor chip 31 further.
Wherein, in another embodiment, it is also possible to be to be initially formed heat dissipating layer 35, then carry out the cutting of cutting zone 71, with Simplified flowsheet.
In present embodiment, by carrying out the encapsulation of multiple semiconductor chip 31 on large substrates 70, then separate multiple encapsulating structures by follow-up cutting flow process, production efficiency can be improved.Further, by glued membrane 50a, the welding and assembling height tolerance that semiconductor chip 31 causes in reflow process can be regulated.Specifically, semiconductor chip 31 after being oppositely arranged and base board unit 32 are by Reflow Soldering after carrying out welding therebetween, and the multiple semiconductor chips 31 on substrate 70 there may be difference in height, cause the second surface 312 that exposes the most at grade.And during follow-up plastic packaging, by arranging the resilient glued membrane 50a of tool, when upper film 50b is pressed on glued membrane 50a, the elasticity utilizing glued membrane 50a can fit tightly with by multiple semiconductor chips 31 inconsistent for height with glued membrane 50a simultaneously, avoid existing between glued membrane 50a and relatively low semiconductor chip 31 bigger space, such that it is able to avoid capsulation material to overflow to the second surface 312 exposed.
Refering to Fig. 9, in an embodiment of this utility model flip-chip, flip-chip is the chip utilizing the method for packing encapsulation described in any of the above-described embodiment to be formed.Wherein, in present embodiment, flip-chip 90 includes semiconductor chip 31 and base board unit 32.
Semiconductor chip 31 is chip to be packaged, and the surface of semiconductor chip 31 includes first surface 311 and second surface 312, and first surface 311 is relative with second surface 312.First surface 311 is the action face of semiconductor chip 31, namely has the surface of circuit structure, and for the front of semiconductor chip 32, second surface 312 is then the back side of semiconductor chip 31.Being formed with the first connection terminal 411, wherein four first connection terminals 411 shown in figure on first surface 311, first connects terminal 411 is electrically connected with the circuit structure (not shown) in semiconductor chip 31.
Base board unit 32 is the carrier of semiconductor chip 31, such as, can be circuit board.Base board unit 32 includes the 3rd surface 321 and the 4th surface 322.It is formed with the second connection terminal 412 on 3rd surface 321, the 4th surface 322 is formed the 3rd connection terminal 413.Second connection terminal 412 and the 3rd connection terminal 413 are electrically connected to each other, and second connects the annexation between terminal 412, between the 3rd connection terminal 413 and between the second connection terminal 412 and the 3rd connection terminal 413 can need be determined according to side circuit, illustrates only as a kind of example in figure.
Wherein, the first surface 311 of semiconductor chip 31 and the 3rd surface 321 of base board unit 32 are oppositely arranged, and the first connection terminal 411 and the second connection terminal 412 weld together.
Wherein, the surface of semiconductor chip 31 is formed plastic packaging layer 33, and at least partly second surface 312 exposes.Wherein, plastic packaging layer 33 uses epoxide resin material to be formed.
As it is shown in figure 9, the back side that second surface 312 is the semiconductor chip 31 relative with first surface 311 exposed, the side of semiconductor chip 31 and first surface 311 are plastic packaging layer 33 and are wrapped up.Further, for the 3rd surface 321 and the electric property of pad of protective substrate unit 32, the region between the 3rd surface 321 and first surface 311 and the 3rd surface 321 of base board unit 32 of base board unit 32 is also wrapped up by plastic packaging layer 33.
Present embodiment, by the second surface 312 at the back side as semiconductor chip 31 is exposed, thus the heat of semiconductor chip 31 not only by base board unit 32 second connection terminal 412 distribute via base board unit 32, and can be dispelled the heat by the second surface 312 exposed, thus substantially increase the heat-sinking capability of semiconductor chip 31, make the radiating effect of semiconductor chip 31 more, be conducive to improving the stability of circuit.
In the embodiment of this utility model flip-chip, for the ease of the welding between semiconductor chip 31 and substrate 32, as shown in Figure 4, the first connection terminal 411 being the coalition of metal salient point+solder, it includes metal salient point 4111 and solder layer 4112.Solder layer 4112 is formed on metal salient point 4111, and the first connection terminal 411 of semiconductor chip 31 and the second connection terminal 412 of base board unit 32 are welded together by solder layer 4112.
Refering to Figure 10, in another embodiment of this utility model flip-chip, flip-chip 90 farther includes heat dissipating layer 35.Heat dissipating layer 35 is positioned on the second surface 312 of exposure.By the effect of heat dissipating layer 35, the radiating effect of chip can be improved further.
In addition, interior void is caused in order to avoid capsulation material is difficult to fill up the space between first surface 311 and the 3rd surface 321 of base board unit 32 of semiconductor chip 31, in present embodiment, the space between first surface 311 and the 3rd surface 321 of base board unit 32 of semiconductor chip 31 is formed with Underfill layer 34 by underfill process.Underfill layer 34 was formed before forming plastic packaging layer 33.
Wherein, the 3rd connection terminal 413 on the 4th surface 322 of substrate 32 being formed with pedestal 414, pedestal 414 can be such as soldered ball.
Flip-chip in this utility model embodiment, by exposing the back side of flip-chip, so that chip can be dispelled the heat by the back side exposed, can improve the heat-sinking capability of chip.Further, further, by forming heat dissipating layer on the back side exposed, it is possible to improve the radiating effect of chip further.
The foregoing is only embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every equivalent structure utilizing this utility model description and accompanying drawing content to be made or equivalence flow process conversion; or directly or indirectly it is used in other relevant technical fields, the most in like manner it is included in scope of patent protection of the present utility model.
Claims (5)
1. a flip-chip, it is characterised in that include semiconductor chip and base board unit；
The surface of described semiconductor chip includes first surface and second surface, on described first surface
Being formed with the first connection terminal, described base board unit includes the 3rd surface and the 4th surface, described
The second connection terminal it is formed with, the first surface of described semiconductor chip and described substrate on three surfaces
3rd surface of unit is oppositely arranged and described first connection terminal and described second connects terminal soldering
It is connected together；
Wherein, the surface of described semiconductor chip is formed with encapsulated layer, and the most described
Two surfaces expose.
Flip-chip the most according to claim 1, it is characterised in that described the second of exposure
Heat dissipating layer it is formed with on surface.
Flip-chip the most according to claim 1, it is characterised in that described semiconductor chip
First surface and the 3rd surface of described base board unit between be formed with Underfill layer.
Flip-chip the most according to claim 1, it is characterised in that described first connects end
Attached bag includes the first surface of metal salient point and solder layer, described metal salient point and described semiconductor chip
Connecting, described solder layer is formed on described metal salient point.
Flip-chip the most according to claim 1, it is characterised in that described first connects end
Son is spherical stannum ball or the pedestal of column.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620384883.5U CN205657052U (en) | 2016-04-29 | 2016-04-29 | Face down chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620384883.5U CN205657052U (en) | 2016-04-29 | 2016-04-29 | Face down chip |
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| CN205657052U true CN205657052U (en) | 2016-10-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112331568A (en) * | 2020-11-04 | 2021-02-05 | 青岛歌尔微电子研究院有限公司 | Chip glue overflow prevention packaging method |
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- 2016-04-29 CN CN201620384883.5U patent/CN205657052U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112331568A (en) * | 2020-11-04 | 2021-02-05 | 青岛歌尔微电子研究院有限公司 | Chip glue overflow prevention packaging method |
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Address after: 226001 Jiangsu Province, Nantong City Chongchuan District, No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226001 Jiangsu Province, Nantong City Chongchuan District, No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |