KR101847162B1 - Semiconductor package and method for manufacturing the same - Google Patents

Semiconductor package and method for manufacturing the same Download PDF

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Publication number
KR101847162B1
KR101847162B1 KR1020110097727A KR20110097727A KR101847162B1 KR 101847162 B1 KR101847162 B1 KR 101847162B1 KR 1020110097727 A KR1020110097727 A KR 1020110097727A KR 20110097727 A KR20110097727 A KR 20110097727A KR 101847162 B1 KR101847162 B1 KR 101847162B1
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South Korea
Prior art keywords
package
connection
connection pad
semiconductor chip
pad
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KR1020110097727A
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Korean (ko)
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KR20130033808A (en
Inventor
이상민
김병찬
윤경로
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삼성전기주식회사
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Priority to KR1020110097727A priority Critical patent/KR101847162B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package according to an embodiment of the present invention includes a first package having a plurality of first connection pads on one surface thereof, a second connection pad formed on one surface of the first package to correspond to the first connection pad, A second package having a connection pin, and a solder layer formed to surround the connection pin and bonded to the first connection pad and the second connection pad.

Description

[0001] Semiconductor package and method for manufacturing same [0002]

The present invention relates to a semiconductor package and a manufacturing method thereof.

Semiconductor packaging means that the circuit is electrically connected to the designed semiconductor chip and sealed and packaged so that it can withstand the external impact so that the physical function and shape can be used in real life.

The semiconductor package is the result of a semiconductor packaging process that finalizes the semiconductor chip. In a single wafer, a chip on which the same electric circuit is printed can be increased to several tens to several hundreds. However, the semiconductor chip alone can not supply or receive electric signals by receiving electricity from the outside.

Further, since the semiconductor chip contains a minute circuit, it can be easily damaged by an external impact. As a result, the semiconductor chip itself can not be a complete product and must be mounted on a printed circuit board to serve as a complete product.

Packaging technology is dependent on size reduction, heat dissipation and electrical performance improvement, reliability improvement, and price reduction of semiconductor chips. Accordingly, it is required to improve the packaging ability to support the high integration and high performance of semiconductor devices. The semiconductor package must meet the requirements of the semiconductor device, as well as have the package performance suitable for the conditions that occur in the next area of mounting the component on the printed circuit board.

Recently, as portable electronic devices have become smaller, space for mounting semiconductors has been further reduced, products have become more versatile and have higher performance, and the number of semiconductors to support them is increasing. With the development of multimedia and the rapid development of the computer communication industry, miniaturization, large capacity, and high speed of semiconductor chips have been achieved, and semiconductor packages have been developed with a trend toward high integration with thinning and multi-pinning.

Therefore, in order to increase the mounting efficiency per unit volume, the package should follow the trend of light and short cut. As a result, a chip scale package (CSP), which is almost the same size as the chip size, has appeared. In recent years, package development trends have shifted from stacking to chip size, stacking packages on top of stacked chips (SCSP: Stacked CSP), or stacking MCMs (Multi Chip Moudle) packages were also developed.

Among the stack packages, Package On Package (POP), which stacks packages on the package, has emerged as an alternative for high-density packages.

A package-on-package (POP) structure according to the prior art is disclosed in Korean Patent Publication No. 2001-0056937.

However, such a conventional package-on-package (POP) structure is problematic in that it shortens to a fine pitch of a ball pad, that is, a gap between ball pads, Which makes it difficult to assemble the package.

In addition, since the gap between the upper package and the lower package must be at least 250 탆 or more, there is a limit in reducing the solder ball size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional technology, and one aspect of the present invention is to provide a semiconductor package and a method of manufacturing the same, in which a short circuit problem due to solder spread does not occur.

According to another aspect of the present invention, there is provided a semiconductor package that maintains a height between a top package and a bottom package at a predetermined level or more, and a method of manufacturing the same.

Still another aspect of the present invention is to provide a semiconductor package with improved bonding alignment between the upper package and the lower package and a method of manufacturing the same.

Still another aspect of the present invention is to provide a semiconductor package satisfying fine pad pitch characteristics and a method of manufacturing the same.

A semiconductor package according to an embodiment of the present invention includes a first package having a plurality of first connection pads on one surface thereof, a second connection pad formed on one surface of the first package to correspond to the first connection pad, A second package having a connection pin, and a solder layer formed to surround the connection pin and bonded to the first connection pad and the second connection pad.

Here, the connection pin may include a head portion, and a shaft portion having one end connected to the head portion and the other end protruding outwardly.

At this time, the head portion may be formed in a disc shape, and the diameter of one end and the other end of the shaft portion may be larger than the diameter of the center end.

The semiconductor package may further include a first semiconductor chip mounted on the other surface of the first package, and a second semiconductor chip mounted on one surface of the second package.

The semiconductor package may further include a third connection pad formed on the other surface of the first package so as to be electrically connected to the first semiconductor chip. The first semiconductor chip and the third connection pad may be connected by wire bonding .

The second package may further include a fourth connection pad formed on the other surface of the second package so as to be electrically connected to an external device, and may further include an external connection terminal formed on the fourth connection pad.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, comprising: preparing a first package having a plurality of first connection pads and a connection ball formed on the first connection pad on a first surface thereof; Preparing a second package having a second connection pad corresponding to one connection pad and a connection pin formed on the second connection pad, and bonding the first package and the second package.

Here, the connection pin may include a head portion, a shaft portion having one end connected to the head portion and the other end protruding to the outside, and the exposed portion of the connection ball formed on the first connection pad may include, A groove having a shape corresponding to the other end of the groove may be formed.

At this time, the head portion may be formed in a disc shape.

The diameter of one end and the other end of the shaft portion may be larger than the diameter of the center end.

The connection ball is made of solder, and the groove of the connection ball can be formed by a coining process using a coining head having a corresponding shape.

The step of preparing the first package may include preparing a base substrate having a first connection pad formed on one surface thereof and a third connection pad formed on the other surface thereof, Mounting the first semiconductor chip on the first connection pad, and forming the connection ball on the first connection pad.

The step of mounting the first semiconductor chip may be performed by a wire bonding process, and the step of mounting the first semiconductor chip may further include the step of molding the first semiconductor chip and the wire.

The step of preparing the second package may include forming a second connection pad and a semiconductor chip mounting pad corresponding to the first connection pad on one side and a fourth connection pad connected to the external device on the other side, Mounting a second semiconductor chip so as to be electrically connected to the semiconductor chip mounting pad, and bonding the connection pin to the second connection pad.

At this time, the step of mounting the second semiconductor chip is performed by a flip-chip bonding process, and after the step of mounting the second semiconductor chip, an underfill is formed between the base substrate and the second semiconductor chip. and forming an under-fill resin layer.

The step of bonding the first package and the second package may include disposing the first package and the second package such that the connection ball and the connection pin are in contact with each other and performing a reflow process, 2 < / RTI > package.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

The present invention has an effect of preventing a short due to spreading of solder during a reflow process by bonding a package and a package using a connection pin having a fine diameter.

Further, according to the present invention, the package and the package are joined by using the connecting pin having a predetermined length, so that the interval between the bonded package and the package can be secured to a certain level or more.

Further, according to the present invention, the connection ball is formed with a groove having a shape corresponding to the protruding portion of the connection pin, so that the package can be easily aligned when the package is bonded.

Further, according to the present invention, it is possible to achieve a fine pad pitch by reducing the interval between pads by suppressing an increase in solder volume at the time of package bonding by using a connecting pin having a fine diameter.

1 is a cross-sectional view illustrating a structure of a semiconductor package according to an embodiment of the present invention.
FIGS. 2 to 5 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a connection pin according to an embodiment of the present invention.
7 is a cross-sectional view illustrating a connection ball formed in accordance with an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, particular advantages and novel features of the invention will become more apparent from the following detailed description and examples taken in conjunction with the accompanying drawings. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another, and the element is not limited by the terms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Semiconductor package

1 is a cross-sectional view illustrating a structure of a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor package 100 according to the present embodiment includes a first package 110, a second package 150, and a solder layer 195 coupling the two.

1, the first package 110 may include a base substrate 120 and a first semiconductor chip 130 mounted on the base substrate 120. As shown in FIG.

1, a plurality of first connection pads 122 are formed on the lower surface of the base substrate 120, and a plurality of third connection pads 124 (not shown) electrically connected to the semiconductor chip 130 are formed on the upper surface, May be formed.

The base substrate 120 may be a single layer or a multilayer printed circuit board formed by stacking a plurality of insulating layers and a plurality of circuit layers

At this time, a resin insulating layer may be used as the insulating layer. As the resin insulating layer, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as a glass fiber or an inorganic filler, for example, a prepreg can be used, And / or a photo-curable resin may be used, but the present invention is not limited thereto.

Further, the circuit layer including the first connection pad 122 and the third connection pad 124 can be applied without limitation as long as it is used as a conductive metal for a circuit in the field of circuit boards, and copper is used for a printed circuit board It is typical.

The semiconductor device 100 may further include a solder resist layer 115 formed on the base substrate 120 to expose the first connection pad 122 and the third connection pad 124.

In FIG. 1, one first semiconductor chip 130 is mounted on the base substrate 120. However, the present invention is not limited thereto, and a plurality of semiconductor chips may be mounted.

At this time, the first semiconductor chip 130 may be bonded to the base substrate 120 using a bonding material (not shown) such as epoxy, but the present invention is not limited thereto.

In this embodiment, the first semiconductor chip 130 of the first package 110 is electrically connected to the base substrate 120 through wire bonding.

1, a connection terminal (not shown) formed on the upper surface of the first semiconductor chip 130 and a third connection pad 124 on the upper surface of the base substrate 120 are connected to a wire 135 ). However, the present invention is not limited to this, and it is also possible to connect through a flip-chip bonding process.

The first package 110 is formed with a molding material 140 on the base substrate 120 to protect the first semiconductor chip 130 and the wires 135 formed on the base substrate 110 from the outside , An epoxy molding compound (EMC), a silicon epoxy, or the like may be used, but the present invention is not limited thereto.

The second package 150 may include a base substrate 160 and a second semiconductor chip 170 mounted on the base substrate 160 in the same manner as the first package 110 described above.

The base substrate 160 of the second package 150 may also be a single layer or a multilayer printed circuit board in which a plurality of insulating layers and a plurality of circuit layers are laminated.

1, a plurality of second connection pads 162 and a semiconductor chip mounting pad 164 are formed on the upper surface of the base substrate 160. A fourth connection pad 166 are formed.

Here, the second connection pad 162 may be formed at a position corresponding to the first connection pad 122 of the first package 110 described above, but is not limited thereto.

The second package 150 The circuit layer including the second connection pad 162, the semiconductor chip mounting pad 164 and the fourth connection pad 166 of the base board 160 is also formed in the circuit board area The conductive metal for the circuit in Fig.

As shown in FIG. 1, the fourth connection pad 166 may be formed on the fourth connection pad 166, and an external connection terminal 157 may be formed on the fourth connection pad 166. Here, The external connection terminal 157 may be a solder ball, but is not limited thereto.

The semiconductor device may further include a solder resist layer 155 formed on the base substrate 160 to expose the second connection pad 162, the semiconductor chip mounting pad 164, and the fourth connection pad 166 .

In this embodiment, the second semiconductor chip 170 of the second package 150 is electrically connected to the base substrate 160 through a flip-chip bonding process.

1, the connection bumps 172 formed on the lower surface of the second semiconductor chip 170 and the semiconductor chip mounting pads 164 on the upper surface of the base substrate 160 are flip-chip bonded (slip- chip bonding process. However, the present invention is not limited to this, and it is also possible to connect through a wire bonding process using a wire.

The second package 150 may further include an underfill material 180 formed by filling an under-fill liquid into a joint portion between the base substrate 160 and the second semiconductor chip 170 and curing the underfill material 180 can do.

The underfill material 180 is formed at the joining portion between the lower surface of the second semiconductor chip 170 and the base substrate 160. The underfill material 180 is not particularly limited to this example, It is also possible to form the molding material.

The connection pins 190 may be formed on the second connection pads 162 of the second package 150. The connection pins 190 may be formed on the first connection pads 122 of the first package 110, And the connection pin is formed in the second region.

6, the connection pin 190 according to the present embodiment may include a head portion 191 and a shaft portion 193 connected to the head portion 191 at one end and protruding outward at the other end .

At this time, the head portion 191 is formed in a disk shape, and one end of the shaft portion 193 may be formed to be connected to the center portion of the disk-shaped head portion 191, but is not limited thereto.

Further, the connection pin 190 can be integrally formed with the head portion 191 and the shaft portion 193 by injection molding using a metal mold.

In this embodiment, the shaft portion 193 of the connection pin 190 may be formed such that the diameter of one end a and the other end c are larger than the diameter of the center end b, as shown in Fig.

This is because the one end (a) and the other end (c), which are weak junctions at the time of reflow bonding with the first package 110, have a large area to cope with stress, , And the central end (b) portion which is convex due to the volume of the melted solder is formed to have a thin thickness in order to minimize the convex phenomenon.

In this embodiment, the connection pin 190 is formed in a curved shape as shown in FIG. 1. However, the present invention is not limited to this, and any shape may be used.

6, the length P of the connecting pin 190 should be at least 180 mu m. If the length of the connecting pin 190 is less than 180 mu m, A minimum gap between the first package 110 and the second package 150 may not be ensured when the second package 150 is bonded.

That is, in order to secure a minimum gap between the first package 110 and the second package 150 to be bonded, the connection pin 190 should also be at least a minimum length.

In this embodiment, the connection pin 190 may be any material having electric conductivity.

1, the semiconductor package according to the present embodiment is formed so as to surround the outer circumference of the connection pin 190, so that the first connection pad 122 of the first package 110, And a solder layer 195 that is bonded to the second connection pad 162 of the connection pad 150.

Accordingly, the semiconductor package according to the present embodiment can be manufactured by joining two packages, that is, the first package 110 and the second package 150 using the connecting pin 190, It is possible to prevent a short phenomenon that may occur due to an increase in the voltage.

Further, by using the connection pin 190 having a predetermined length or more, the gap between the first package 110 and the second package 150 to be bonded can be kept constant.

Method of manufacturing a semiconductor package

FIGS. 2 to 5 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 2, a first package 110 having a plurality of first connection pads 122 and a connection ball 125 formed on a first connection pad 122 is prepared on one surface.

2, a third connection pad 124 is formed on an upper surface of the first package 110, and a base substrate 120 on which a first connection pad 122 is formed. Mounting the first semiconductor chip 130 on the first connection pad 122 of the base substrate 120 so as to be electrically connected to the third connection pad 124 of the prepared base substrate 120, Thereby forming a connection ball 125 in the connection hole.

Here, the base substrate 120 may be a single layer or a multilayer printed circuit board.

For example, in FIG. 2, the base substrate 120 is illustrated as having a first connection pad 122 and a third connection pad 124 formed on one insulation layer 121, but is particularly limited thereto But a plurality of insulating layers and a plurality of circuit layers may be further formed.

At this time, forming a circuit layer including the first connection pad 122 and the third connection pad 124 on the base substrate 120 can be performed using a general circuit forming process known in the art, And the detailed description thereof will be omitted.

A solder resist layer 115 may be further formed on the base substrate 120 to expose the first connection pad 122 and the third connection pad 124.

In this embodiment, mounting of the first semiconductor chip 130 can be performed by a wire bonding process or a flip-chip bonding process.

2, a third connection pad 124 of the base substrate 120 and a connection terminal (not shown) formed on the first semiconductor chip 130 are connected by wire bonding using a wire 135 a flip chip mounting pad (not shown) is formed on the base substrate 120, and connection pads (not shown) are formed on the bottom surface of the first semiconductor chip 130 (Not shown) may be formed and connected through a flip-chip process.

The molding material 140 may be formed to surround the entire upper surface of the base substrate 120 to protect the mounted first semiconductor chip 130 and the wires 135 from the outside. In this case, when the first semiconductor chip 130 is flip-chip bonded on the base substrate 110, the first semiconductor chip 130 and the base substrate 120 are connected to each other, It is also possible to form a filler (not shown).

2, a connection ball 125 is formed on the first connection pad 122 of the base substrate 120. At this time, the connection ball 125 is not limited to a solder, ≪ / RTI >

7, an exposed portion of the connection ball 125 formed on the first connection pad 122, that is, a portion opposite to the portion in contact with the first connection pad 122, A groove A having a shape corresponding to the protruding portion B (see Fig. 6) of the protrusion 190 may be formed.

At this time, the groove A of the connection ball 125 may be formed through a coining process using a coining head having a corresponding shape.

That is, generally, in the related art, a soldering ball is formed on a pad, and then a coining process is performed to press the upper surface of the solder ball to make the height of the solder ball flat. In this case, The upper surface of the solder ball may be pressed by using a coining head having a corresponding protruding portion so that a groove A as shown in FIG. 2 is formed on the solder ball.

However, this is only an example, and the process of forming the groove in the connection ball 125 is not limited thereto.

3, a second package having a second connection pad 162 corresponding to the first connection pad 122 and a connection pin 190 formed on the second connection pad 162 on one side 150 are prepared.

3, the second connection pad 162 and the semiconductor chip mounting pad 164 are formed on the upper surface of the second package 150 in correspondence with the first connection pad 122 And a fourth connection pad 166 connected to an external device is formed on the lower surface of the base substrate 160. The second semiconductor chip 170 is mounted to be electrically connected to the semiconductor chip mounting pad 164, And joining the connection pins 190 to the second connection pads 162. [0035]

Here, the base substrate 160 may be a single layer or a multilayer printed circuit board.

3, the base substrate 160 includes a plurality of insulating layers 161 and second connection pads 162, a semiconductor chip mounting pad 164, a fourth connection pad 166, But the present invention is not limited thereto.

The formation of the circuit layer including the second connection pad 162, the semiconductor chip mounting pad 164 and the fourth connection pad 166 on the base substrate 160 may be performed by a general circuit forming process , Which are well known in the art, and a detailed description thereof will be omitted.

A solder resist layer 155 may be further formed on the base substrate 160 to expose the second connection pad 162, the semiconductor chip mounting pad 164 and the fourth connection pad 164.

Here, the mounting of the second semiconductor chip 170 can be performed by a flip-chip bonding process or a wire bonding process.

3, the semiconductor chip mounting pad 164 of the base substrate 160 and the connection bumps 172 formed on the bottom surface of the second semiconductor chip 170 are flip chip bonded (flip chip bonding) -chip bonding process. However, the present invention is not limited to this, and it is also possible to connect through a wire bonding process.

Thereafter, the underfill material 180 may be formed by filling and curing an under-fill liquid in a connected portion between the lower surface of the second semiconductor chip 170 and the base substrate 160. At this time, it is also possible to mold the second semiconductor chip 170 so as to surround the entire upper portion of the second semiconductor chip 170.

Next, referring to FIG. 3, the connection pin 190 is bonded to the second connection pad 162 of the second package 150 base substrate 160.

6, the connection pin 190 may include a head portion 191 and a shaft portion 193 connected to the head portion 191 at one end and protruding outward at the other end.

6) of the shaft portion 193 may be connected to the center portion of the disk-shaped head portion 191, but the present invention is not limited thereto. no.

Further, the connection pin 190 can be integrally formed with the head portion 191 and the shaft portion 193 by injection molding using a metal mold.

In this embodiment, the shaft portion 193 of the connection pin 190 may be formed such that the diameter of one end a and the other end c are larger than the diameter of the center end b, as shown in Fig.

This is because one end (a) and the other end (b), which are weak junctions at the time of reflow bonding with the first package 110, have a large area to cope with stress, And to have a thin thickness in order to minimize the convexity of the convex center part (b) due to the solder volume at the time of melting.

In this embodiment, as shown in FIG. 6, the connection pin 190 may be formed in a curved shape, but is not limited thereto, and any shape may be used.

In the present embodiment, the length P of the connection pin 190 may be at least 180 탆. If the length of the connection pin 190 is less than 180 탆, the first package 110 and the second package 150 The minimum gap between the first package 110 and the second package 150 is not ensured.

That is, in order to secure a minimum gap between the first package 110 and the second package 150 to be bonded, the connection pin 190 should also be at least a minimum length.

In this embodiment, the connecting pin 190 may be any material having electric conductivity.

Next, referring to FIGS. 4 and 5, the first package 110 and the second package 150 are bonded.

In the present embodiment, the step of bonding the first package 110 and the second package 150 includes disposing the second package 150 under the first package 110, as shown in FIG.

At this time, the connection pin 190 formed on the second connection pad 162 of the second package 150 is inserted into the groove A of the connection ball 125 formed on the first connection pad 122 of the first package 110, (B) of the protruded portion of the protruding portion of the protruding portion is inserted.

As described above, by using the connection ball 125 having the groove A having the shape corresponding to the end B of the protruded portion of the connection pin 190, the first package 110 and the second package 150 Alignment at the time of bonding can be facilitated.

The connection ball 125 is melted to reflow the first connection pad 122 of the first package 110 and the second connection pad 162 and the connection pin 190 of the second package 150, Lt; / RTI >

That is, the connection ball 125 formed on the first connection pad 122 is melted and flows downward to surround the outer circumference of the connection pin 190 and to be fused to the second connection pad 162, The second connection pad 162 and the connection pin 190 are combined into one.

As described above, by joining the first package and the second package using the connection pin having a predetermined length, it is possible to secure a gap h of a certain level or more between the coupled first package and the second package.

Further, by using the connecting pin having a fine diameter, it is possible to prevent a short which may occur due to an increase in solder volume at the time of package bonding.

Further, by bonding the package using the connecting pins, it is possible to suppress the increase of the solder volume and to reduce the inter-pad spacing w to achieve a fine pad pitch.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. It is apparent that the present invention can be modified or improved by those skilled in the art.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: semiconductor package 110: first package
115: solder resist layer 120: base substrate
121: insulating layer 122: first connection pad
124: third connection pad 125: connection ball
130: first semiconductor chip 135: wire
140: molding material 150: second package
155: solder resist layer 157: external connection terminal
160: base substrate 162: second connection pad
164: semiconductor chip mounting pad 166: fourth connection pad
170: second semiconductor chip 172: connection bump
180: underfill material 190: connecting pin
195: Solder layer

Claims (20)

A first package having a plurality of first connection pads on one surface thereof;
A second package having a second connection pad formed on one surface thereof to correspond to the first connection pad and a connection pin formed on the second connection pad; And
And a solder layer formed to surround the connection pin and bonded to the first connection pad and the second connection pad,
Wherein the connection pin includes a shaft portion protruding outside the second connection pad and surrounded by the solder layer,
Between the first package and the second package,
Wherein the shaft portion includes a portion whose diameter becomes smaller and larger,
Wherein the diameter of the solder layer is small. The method according to claim 1,
The connection pin further includes a head portion formed between the shaft portion and the second connection pad,
At a point where the shaft portion and the head portion come into contact with each other,
Wherein a diameter of the head portion is larger than a diameter of the shaft portion. The method of claim 2,
Wherein the head portion is formed in a disc shape. delete The method according to claim 1,
And a first semiconductor chip mounted on the other surface of the first package. The method according to claim 1,
And a second semiconductor chip mounted on one surface of the second package. The method of claim 5,
And a third connection pad formed on the other surface of the first package to be electrically connected to the first semiconductor chip. The method of claim 7,
And the first semiconductor chip and the third connection pad are connected by wire bonding. The method according to claim 1,
And a fourth connection pad formed on the other surface of the second package and electrically connected to the external device. The method of claim 9,
And an external connection terminal formed on the fourth connection pad. Preparing a first package having a plurality of first connection pads on one surface and connection balls formed on the first connection pads;
Preparing a second package having a second connection pad corresponding to the first connection pad and a connection pin formed on the second connection pad on one surface thereof; And
And bonding the first package and the second package,
Wherein the connection pin includes a shaft portion protruding outside the second connection pad and surrounded by a solder layer,
In the step of bonding the first package and the second package,
The connection ball is a solder layer that surrounds the shaft portion,
Between the first package and the second package,
Wherein the shaft portion includes a portion whose diameter becomes smaller and larger,
Wherein a diameter of the solder layer is increased or decreased. The method of claim 11,
The exposed portion of the connection ball formed on the first connection pad,
And a groove corresponding to an end of the shaft portion opposite to the first package is formed. The method of claim 11,
The connection pin further includes a head portion formed between the shaft portion and the second connection pad,
At a point where the shaft portion and the head portion come into contact with each other,
Wherein a diameter of the head portion is larger than a diameter of the shaft portion. 14. The method of claim 13,
Wherein the head portion is formed in a disc shape. The method of claim 12,
Wherein the connection ball is made of solder and the groove of the connection ball is formed by a coining process using a coining head having a corresponding shape. The method of claim 11,
Wherein preparing the first package comprises:
Preparing a base substrate on which a first connection pad is formed on one side and a third connection pad is formed on the other side;
Mounting a first semiconductor chip on the other surface of the base substrate so as to be electrically connected to the third connection pad; And
Forming the connection ball on the first connection pad
Wherein the semiconductor package is a semiconductor package. 18. The method of claim 16,
The step of mounting the first semiconductor chip is performed by a wire bonding process,
After the step of mounting the first semiconductor chip,
And molding the first semiconductor chip and the wire. The method of claim 11,
Wherein preparing the second package comprises:
Preparing a base substrate on one surface of which a second connection pad and a semiconductor chip mounting pad corresponding to the first connection pad are formed and a fourth connection pad connected to the external device is formed on the other surface;
Mounting a second semiconductor chip so as to be electrically connected to the semiconductor chip mounting pad; And
And joining the connection pin to the second connection pad
Wherein the semiconductor package is a semiconductor package. 19. The method of claim 18,
The step of mounting the second semiconductor chip is performed by a flip-chip bonding process,
After the step of mounting the second semiconductor chip,
And forming an under-fill resin layer between the base substrate and the second semiconductor chip. The method of claim 11,
Wherein the step of bonding the first package and the second package comprises:
Disposing the first package and the second package such that the connection ball and the connection pin are in contact with each other; And
A step of joining the first package and the second package by performing a reflow process
Wherein the semiconductor package is a semiconductor package.
KR1020110097727A 2011-09-27 2011-09-27 Semiconductor package and method for manufacturing the same KR101847162B1 (en)

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US9418953B2 (en) 2014-01-13 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging through pre-formed metal pins
KR102004795B1 (en) * 2014-07-18 2019-07-29 삼성전기주식회사 Semiconductor Package and Method of Manufacturing the same
CN113939911A (en) * 2019-05-31 2022-01-14 华为技术有限公司 Chip and integrated chip
CN113078147B (en) * 2021-02-22 2023-08-15 上海易卜半导体有限公司 Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
KR20220140290A (en) * 2021-04-09 2022-10-18 삼성전자주식회사 Package device comprising a capacitor disposed on the opposite side of the die relative to the substrate

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JP2009054741A (en) * 2007-08-27 2009-03-12 Powertech Technology Inc Semiconductor package
JP2011077093A (en) * 2009-09-29 2011-04-14 Texas Instr Japan Ltd Ultrasonic flip chip mounting method and ultrasonic mounting device

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