CN109411375B - Packaging auxiliary device and packaging method - Google Patents

Packaging auxiliary device and packaging method Download PDF

Info

Publication number
CN109411375B
CN109411375B CN201811253866.8A CN201811253866A CN109411375B CN 109411375 B CN109411375 B CN 109411375B CN 201811253866 A CN201811253866 A CN 201811253866A CN 109411375 B CN109411375 B CN 109411375B
Authority
CN
China
Prior art keywords
packaging
substrate
chips
back surface
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811253866.8A
Other languages
Chinese (zh)
Other versions
CN109411375A (en
Inventor
周云燕
王启东
宋刚
杨海博
曹立强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201811253866.8A priority Critical patent/CN109411375B/en
Publication of CN109411375A publication Critical patent/CN109411375A/en
Application granted granted Critical
Publication of CN109411375B publication Critical patent/CN109411375B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The invention discloses a packaging auxiliary device and a packaging method, wherein the packaging auxiliary device is matched with the bottom of a packaging structure and comprises the following steps: a base for supporting a substrate of the package structure; a plurality of accommodating grooves formed on the base for accommodating and supporting a plurality of back chips and a plurality of solder balls arranged on the back surface of the substrate; and after being matched by the packaging auxiliary device, the packaging structure is suitable for arranging a plurality of front chips on the front surface of the substrate.

Description

Packaging auxiliary device and packaging method
Technical Field
The embodiment of the invention relates to the technical field of semiconductor packaging, in particular to a packaging auxiliary device and a packaging method.
Background
With the trend of multi-functionalization and miniaturization of electronic products, high-density integration of semiconductor package structures is important. To achieve high interconnection density, shorten interconnection paths, and reduce package size, the semiconductor package technology field starts to increasingly adopt multi-chip three-dimensional integration technology to realize system-in-package.
Multi-chip three-dimensional integration techniques generally include placing multiple chips with different bonding schemes (e.g., front-side mounting, flip-chip mounting, wire bonding, etc.) on the front and back sides of a substrate with vertical interconnect structures to reduce package size and improve system performance.
However, since the front and back surfaces of the substrate need to be provided with the chip and the solder ball, and the number of the chips is large, the sizes are different, and the bonding modes are different, new difficulties are brought to the packaging process, and the packaging difficulty is increased. Therefore, in order to adapt to the multi-chip three-dimensional integration technology, the packaging process needs to be improved.
Disclosure of Invention
The embodiment of the invention aims to provide a packaging auxiliary device and a packaging method.
According to an aspect of the present invention, there is provided a package auxiliary device fitted to a bottom of a package structure, including: a base for supporting a substrate of the package structure; a plurality of accommodating grooves formed on the base for accommodating and supporting a plurality of back chips and a plurality of solder balls arranged on the back surface of the substrate; and after being matched by the packaging auxiliary device, the packaging structure is suitable for arranging a plurality of front chips on the front surface of the substrate.
According to some embodiments, the susceptor is connected to the exposed back surface of the substrate, and the susceptor is provided with a plurality of through hole structures in regions corresponding to the exposed back surface and the plurality of back surface chips for vacuum adsorption.
According to some embodiments, the packaging auxiliary device further includes a protection adhesive layer disposed on an area of the base corresponding to the exposed back surface and at a bottom of the receiving groove for receiving the plurality of back chips.
According to some embodiments, the packaging aid further comprises a plurality of spring structures disposed at the bottom of the receiving grooves for receiving the plurality of solder balls.
According to some embodiments, the packaging aid conducts heat from the workpiece table to the substrate.
According to some embodiments, the substrate comprises an active substrate or a passive substrate.
According to another aspect of the present invention, there is provided a packaging method using the packaging assistance device, including: providing a substrate; arranging a plurality of back chips and a plurality of solder balls on the back surface of the substrate to obtain a packaging structure; fitting the packaging auxiliary device to the bottom of the packaging structure, so that the base supports the substrate, and the plurality of accommodating grooves accommodate and support the plurality of back chips and the plurality of solder balls; arranging a plurality of front chips on the front surface of the substrate; removing the packaging aid.
According to some embodiments, the package structure is fixed to the package aid by vacuum suction.
According to some embodiments, the package structure is adhered to the package auxiliary device by a protective adhesive layer, wherein the substrate is adhered to the base, and the plurality of back chips are adhered to the bottoms of the plurality of accommodating grooves.
According to some embodiments, the plurality of solder balls are supported with a plurality of reed structures.
In the packaging auxiliary device according to the embodiment of the invention, the base is arranged to support the substrate of the packaging structure, and the plurality of accommodating grooves are arranged to accommodate and support the plurality of back chips and the plurality of solder balls arranged on the back of the substrate, so that the bottom of the packaging structure is matched with the packaging auxiliary device, the bottom of the packaging structure with a complex structure and uneven back has smooth and reliable support on the premise of better protection, the front side of the substrate is convenient to arrange the plurality of front chips, the preparation of a multi-chip three-dimensional integrated structure is facilitated, the packaging difficulty is reduced on one hand, and the packaging effect is improved on the other hand.
Drawings
Other objects and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings, and may assist in a comprehensive understanding of the invention.
FIG. 1 shows a schematic structural diagram of a packaging aid according to an exemplary embodiment of the invention;
fig. 2-7 show schematic diagrams of processes of a packaging method using the packaging aid of fig. 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. It should be noted that in the drawings or description, the same drawing reference numerals are used for similar or identical parts. Implementations not depicted or described in the drawings are of a form known to those of ordinary skill in the art. Additionally, while exemplifications of parameters including particular values may be provided herein, it is to be understood that the parameters need not be exactly equal to the respective values, but may be approximated to the respective values within acceptable error margins or design constraints. Directional phrases used in the embodiments, such as "upper", "lower", "front", "back", etc., refer only to the orientation of the drawings. Accordingly, the directional terminology used is intended to be in the nature of words of description rather than of limitation.
Fig. 1 shows a schematic structural view of a packaging aid 100 according to an exemplary embodiment of the present invention, the packaging aid 100 being fittable to the bottom of a packaging structure 20 (shown in fig. 5), as shown in fig. 1, the packaging aid 100 comprising: a base 11 for supporting a substrate 21 (shown in fig. 5) of the package structure 100; a plurality of receiving grooves 12 formed on the base 11 for receiving and supporting a plurality of rear chips 24 and a plurality of solder balls 23 (shown in fig. 5) provided on the rear surface of the substrate 21; the package structure 20 is adapted to dispose a plurality of front-side chips 25 (shown in fig. 6) on the front side of the substrate 21 after being engaged by the package auxiliary device 100. In the auxiliary packaging device 100 according to the embodiment of the invention, the base is arranged to support the substrate of the packaging structure, and the plurality of accommodating grooves are arranged to accommodate and support the plurality of back chips and the plurality of solder balls arranged on the back of the substrate, so that the bottom of the packaging structure is matched with the auxiliary packaging device, the bottom of the packaging structure with a complex structure and uneven back has smooth and reliable support on the premise of better protection, the front surface of the substrate is provided with the plurality of front chips, the preparation of a multi-chip three-dimensional integrated structure is facilitated, the packaging difficulty is reduced on one hand, and the packaging effect is improved on the other hand.
Referring to fig. 5, the package structure 20 of the present invention includes a substrate 21, a plurality of vertical interconnection structures 22 penetrating the substrate 21, a plurality of backside chips 24 disposed on the backside of the substrate 21, and a plurality of solder balls 23. The substrate 21 may include an active substrate or a passive substrate, the active substrate may be a chip with a function, such as a compound chip and a silicon-based chip, the compound chip may include GaAs, GaN, etc., and the silicon-based chip may include GeSi, etc.; the passive substrate may be a nonfunctional substrate such as a square, wafer, or irregular sheet made of silicon, silicon dioxide, ceramic, glass, metal, alloy, organic material, or the like. The plurality of vertical interconnection structures 22 are used to connect the front and back surfaces of the substrate 21, and may include a via, a wiring layer, a pad, and the like. The plurality of back chips 24 may be attached to the back surface of the substrate 21 by different bonding methods, such as front mounting, flip mounting, and the like. A plurality of solder balls 23 serve as I/O (input/output) terminals of the circuit and are available for interconnection to a Printed Circuit Board (PCB). The package structure 20 is an intermediate structure in the packaging process, and after the assembly of the back chip 24 and the solder balls 23 on the back surface of the substrate 21 is completed, the package structure 20 obtained by the assembly is matched with the auxiliary packaging device 100, and then a plurality of front chips 25 are assembled on the front surface of the package structure 20, so that the final package structure can be obtained. In the final package structure, a plurality of back chips 24 and a plurality of front chips 25 are provided on the back surface and the front surface of the substrate 21, respectively, which is a three-dimensional package structure.
Referring again to fig. 1, the base 11 has a flat bottom for providing a smooth support for the package structure 20. The base 11 may be made of a material with good heat transfer performance so as to conduct heat from the workpiece stage to the substrate 21 when the plurality of front chips 25 are disposed on the package structure 20 engaged with the package auxiliary device 100. The positions and sizes of the plurality of receiving grooves 12 may be determined according to the positions and sizes of the plurality of back chips 24 and the plurality of solder balls 23 to be received. The plurality of back chips 24 may include different types of chips, which have different sizes and different thicknesses from each other, and further, the plurality of back chips 24 may include a single-layer structure or a multi-layer stacked structure. The plurality of receiving grooves 12 may be dimensioned accordingly to have a groove depth and a groove width. Separate receiving grooves 12 may be provided for each of the single back chip 24 and the single solder ball 23, or a common receiving groove 12 may be provided for a plurality of back chips 24 having the same thickness and a plurality of solder balls 23 having the same thickness. For example, fig. 5 illustrates a case where two solder balls correspond to a common receiving groove.
Referring to fig. 5, the base 11 is connected to the exposed back surface of the substrate 21, which refers to the area of the back surface of the substrate where no backside chips, solder balls or other lead-out structures are disposed. The base 11 is provided with a plurality of through-hole structures 13 for vacuum suction in regions corresponding to the exposed back surface and the plurality of back surface chips 24. By evacuating air from the plurality of through-hole structures 13, a low-pressure environment is formed between the auxiliary packaging device 100 and the packaging structure 20, and the packaging structure 20 can be fixed to the auxiliary packaging device 100 under the action of the pressure difference.
Further, the auxiliary packaging device 100 further includes a protective adhesive layer 14, wherein the protective adhesive layer 14 is disposed on an area of the base 11 corresponding to the exposed back surface and is disposed at the bottom of the accommodating groove for accommodating the plurality of back chips 24. On one hand, the fixation between the package auxiliary device 100 and the package structure 20 can be strengthened by utilizing the adhesion effect of the protective adhesive layer 14, and the protective adhesive layer 14 can avoid the insufficient vacuum adsorption effect caused by the fluctuation of the line pattern structure because the exposed back surface of the substrate 21 and the plurality of back chips 24 are provided with the line pattern structures; on the other hand, the protective adhesive layer 14 can also protect the circuit pattern structure, and provide a good buffer effect at the contact surface.
The packaging aid 100 may further comprise a plurality of reed structures 15, the plurality of reed structures 15 being disposed at the bottom of the receiving groove for receiving the plurality of solder balls 23. By utilizing the good elasticity of the reed structures 15, the base plate 21 and the solder balls 23 can be supported softly, and the abrasion and damage caused by excessive contact can be prevented.
According to the above description, the auxiliary packaging device 100 of the present invention can be used for supporting the packaging structure 20, preventing the packaging process from damaging the complex structure at the bottom of the packaging structure 20, and meanwhile, is beneficial to the heat conduction of the workpiece stage, and can realize multi-chip assembly with different bonding modes and different heights on the front and back surfaces of the substrate 21, thereby reducing the packaging difficulty and reducing the cost.
Fig. 2-7 show schematic diagrams of the process of the packaging method using the packaging aid 100 of fig. 1, and with reference to fig. 2-7, the packaging method of the invention comprises the following steps:
first, as shown in fig. 2, a substrate 21 is provided, and a plurality of vertical interconnection structures 22 are formed on the substrate 21;
then, as shown in fig. 3-4, a plurality of solder balls 23 and a plurality of back chips 24 are disposed on the back surface of the substrate 21, so as to obtain a package structure 20; fig. 4 is a view showing the substrate 21 with the back side facing upward, the back chip 24 being mounted, and the substrate 21 being turned upside down after mounting;
thereafter, as shown in fig. 5, the package auxiliary device 100 is fitted to the bottom of the package structure 20, such that the base 11 supports the substrate 21, and the plurality of receiving grooves 12 receive and support the plurality of back chips 24 and the plurality of solder balls 23;
thereafter, as shown in fig. 6, a plurality of front-side chips 25 are disposed on the front side of the substrate 21, and the front-side chips 25 may adopt a plurality of bonding methods, including forward mounting, flip chip, wire bonding, etc., and the types and sizes of the chips are not limited;
finally, as shown in fig. 7, the packaging aid 100 is removed. Thus, the whole packaging process is completed.
Specifically, the package structure 20 is fixed to the package auxiliary device 100 by vacuum suction, wherein the substrate 21 is fixed to the base 11 by vacuum suction, and the plurality of back chips 24 are fixed to the bottom of the plurality of receiving grooves.
Further, the package structure 200 is adhered to the package auxiliary device 100 by the protective adhesive layer 14, wherein the substrate 21 is adhered to the base 11 by the protective adhesive layer 14, and the plurality of back chips 24 are adhered to the bottoms of the plurality of receiving grooves, so as to further reinforce and protect the circuit pattern structure on the back surface of the substrate 21 and the plurality of back chips 24.
Specifically, the plurality of spring structures 15 are used to support the plurality of solder balls 23, so that a soft supporting force is formed between the substrate 21 and the plurality of solder balls 23 and the auxiliary packaging device 100, thereby further protecting the packaging structure 20.
Finally, removing the packaging aid 10 may comprise: and closing the vacuum adsorption, separating the packaging structure assembled with the plurality of front chips 25 from the packaging auxiliary device 100, and removing the protective adhesive layer 14 to obtain the final packaging structure.
Although the present invention has been described in connection with the accompanying drawings, the embodiments disclosed in the drawings are intended to be illustrative of embodiments of the invention and should not be construed as limiting the invention.
It would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims (10)

1. A package aid mated to a bottom of a package structure, comprising:
a base for supporting a substrate of the package structure;
a plurality of accommodating grooves formed on the base for accommodating and supporting a plurality of back chips and a plurality of solder balls arranged on the back surface of the substrate;
and after being matched by the packaging auxiliary device, the packaging structure is suitable for arranging a plurality of front chips on the front surface of the substrate.
2. The packaging aid of claim 1, wherein the base is connected to an exposed back surface of the substrate, the base is provided with a plurality of through-hole structures in regions corresponding to the exposed back surface and the plurality of back surface chips for vacuum suction,
the exposed back surface is a substrate back surface area without the back surface chip, the solder balls or other lead-out structures.
3. The packaging aid of claim 2, further comprising a protective adhesive layer disposed on an area of the base corresponding to the exposed back surface and at a bottom of a receiving groove for receiving the plurality of back chips.
4. The packaging aid of claim 1, further comprising a plurality of spring structures disposed at the bottom of the receiving pockets for receiving the plurality of solder balls.
5. The packaging aid of claim 1, wherein the packaging aid conducts heat from a workpiece stage to the substrate.
6. The packaging aid of claim 1, wherein the substrate comprises an active substrate or a passive substrate.
7. A packaging method using the packaging aid of claim 1, comprising:
providing a substrate;
arranging a plurality of back chips and a plurality of solder balls on the back surface of the substrate to obtain a packaging structure;
fitting the packaging auxiliary device to the bottom of the packaging structure, so that the base supports the substrate, and the plurality of accommodating grooves accommodate and support the plurality of back chips and the plurality of solder balls;
arranging a plurality of front chips on the front surface of the substrate;
removing the packaging aid.
8. The packaging method according to claim 7, wherein the packaging structure is fixed to the packaging aid by vacuum suction.
9. The method of claim 8, wherein the package structure is bonded to the auxiliary device by a protective adhesive layer, wherein the substrate is bonded to the base and the plurality of backside chips are bonded to the bottom of the plurality of receiving cavities.
10. The method of claim 7, wherein the plurality of solder balls are supported by a plurality of spring structures.
CN201811253866.8A 2018-10-25 2018-10-25 Packaging auxiliary device and packaging method Active CN109411375B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811253866.8A CN109411375B (en) 2018-10-25 2018-10-25 Packaging auxiliary device and packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811253866.8A CN109411375B (en) 2018-10-25 2018-10-25 Packaging auxiliary device and packaging method

Publications (2)

Publication Number Publication Date
CN109411375A CN109411375A (en) 2019-03-01
CN109411375B true CN109411375B (en) 2020-09-15

Family

ID=65470034

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811253866.8A Active CN109411375B (en) 2018-10-25 2018-10-25 Packaging auxiliary device and packaging method

Country Status (1)

Country Link
CN (1) CN109411375B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811396A (en) * 2014-01-24 2014-05-21 南通富士通微电子股份有限公司 Jig for wafer packaging technology
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
CN105762084A (en) * 2016-04-29 2016-07-13 南通富士通微电子股份有限公司 Packaging method and packaging device for flip chip
CN105870109A (en) * 2016-05-19 2016-08-17 苏州捷研芯纳米科技有限公司 2.5D integrated packaged semiconductor device and manufacturing method thereof
CN106601628A (en) * 2016-12-30 2017-04-26 通富微电子股份有限公司 Chip packaging method and chip packaging structure
CN107331627A (en) * 2017-07-03 2017-11-07 京东方科技集团股份有限公司 A kind of chip packaging method and chip-packaging structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266191A (en) * 2006-03-28 2007-10-11 Nec Electronics Corp Wafer processing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811396A (en) * 2014-01-24 2014-05-21 南通富士通微电子股份有限公司 Jig for wafer packaging technology
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
CN105762084A (en) * 2016-04-29 2016-07-13 南通富士通微电子股份有限公司 Packaging method and packaging device for flip chip
CN105870109A (en) * 2016-05-19 2016-08-17 苏州捷研芯纳米科技有限公司 2.5D integrated packaged semiconductor device and manufacturing method thereof
CN106601628A (en) * 2016-12-30 2017-04-26 通富微电子股份有限公司 Chip packaging method and chip packaging structure
CN107331627A (en) * 2017-07-03 2017-11-07 京东方科技集团股份有限公司 A kind of chip packaging method and chip-packaging structure

Also Published As

Publication number Publication date
CN109411375A (en) 2019-03-01

Similar Documents

Publication Publication Date Title
US10832942B2 (en) Non-embedded silicon bridge chip for multi-chip module
US7019407B2 (en) Flip chip package structure
US20020074637A1 (en) Stacked flip chip assemblies
KR101746731B1 (en) Integrated circuit packaging stacking system with redistribution and method of manufacture thereof
US20060128061A1 (en) Fabrication of stacked die and structures formed thereby
US20090127686A1 (en) Stacking die package structure for semiconductor devices and method of the same
US20110294260A1 (en) Semiconductor package and method of forming the same
US9524883B2 (en) Holding of interposers and other microelectronic workpieces in position during assembly and other processing
US20070235865A1 (en) Semiconductor module havingdiscrete components and method for producing the same
KR20020055603A (en) Dual-die integrated circuit package
KR20030028391A (en) Separation mechanism for adhesive tape, separation apparatus for adhesive tape, separation method for adhesive tape, pickup apparatus for semiconductor chip, pickup method for semiconductor chip, manufacturing method for semiconductor apparatus, and manufacturing apparatus for semiconductor apparatus
WO2024045757A1 (en) 2.5d packaging structure and preparation method
US20220181297A1 (en) Chip Interconnecting Method, Interconnect Device and Method for Forming Chip Packages
KR102612582B1 (en) Method for fixing chips with corner or side contact without impact force
JP2012164951A (en) Device and method for peeling semiconductor chip
JP2008103390A (en) Manufacturing method of semiconductor device
CN109411375B (en) Packaging auxiliary device and packaging method
JP2006093679A (en) Semiconductor package
US8643192B2 (en) Integrated circuit package with discrete components surface mounted on exposed side
JP3651362B2 (en) Manufacturing method of semiconductor device
US20150318268A1 (en) Multi-chip package and method of manufacturing the same
US8144478B1 (en) Circuit module and method
CN112542391B (en) Chip interconnection method, interconnection device and method for forming packaging part
JPS63502071A (en) Chip Interface Eighth Mesa
US20090085202A1 (en) Methods and Apparatus for Assembling Integrated Circuit Device Utilizing a Thin Si Interposer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant