CN202495438U - Thermal-enhanced flip-chip quad flat non-lead package - Google Patents
Thermal-enhanced flip-chip quad flat non-lead package Download PDFInfo
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- CN202495438U CN202495438U CN 201120575398 CN201120575398U CN202495438U CN 202495438 U CN202495438 U CN 202495438U CN 201120575398 CN201120575398 CN 201120575398 CN 201120575398 U CN201120575398 U CN 201120575398U CN 202495438 U CN202495438 U CN 202495438U
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
The utility model discloses a thermal-enhanced flip-chip quad flat non-lead package. The package comprises a lead frame, a chip carrier and pluralities of pins. The lead frame is provided with a stepped structure along the thickness direction, and is provided with an upper surface, a lower surface and a step surface, wherein the lead frame comprises a chip carrier and pluralities of pins. The chip carrier is arranged on the central part of the lead frame, wherein the edge part of four sides of the chip carrier is provided with the stepped structure along the thickness direction, and is provided with the upper surface, the lower surface and the step surface. Pluralities of pins are arranged around the chip carrier, and are arranged around the chip carrier in multiple rings. Pluralities of pins are provided with the stepped structure along the thickness direction, and are provided with the upper surface, the lower surface and the step surface, wherein each pin comprises an inner pin arranged on the upper surface and an outer pin arranged on the lower surface. The package further comprises a first and a second metal material layer, an IC chip having a convex point, an insulation filler material and a plastic material. The QFN package provided by the utility model has the advantages of high reliability, low cost and high I/O density.
Description
Technical field
The utility model relates to semiconductor components and devices manufacturing technology field, refer more particularly to and have thermal-enhanced many circle pin arrangements four limit flat non-pin Flip-Chip Using (Flip Chip Quad Flat Non-lead Package, FCQFN).
Background technology
Along with electronic product such as mobile phone, notebook computer etc. towards miniaturization; Portable; Ultra-thinization, multimedization and satisfy popular needed low-cost direction and develop, high density, high-performance, high reliability and packing forms and packaging technology thereof have obtained development fast cheaply.Compare with packing forms such as expensive BGA; Fast-developing in recent years novel encapsulated technology; I.e. four limit flat non-pin QFN (Quad Flat Non-lead Package) encapsulation; Because have good hot property and electrical property, size is little, cost is low and numerous advantages such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Figure 1A and Figure 1B are respectively the schematic rear view of traditional Q FN encapsulating structure and along the generalized section of I-í section; This QFN encapsulating structure comprises lead frame 11, capsulation material 12, bonding die material 13; IC chip 14; Plain conductor 15, wherein lead frame 11 comprises chip carrier 111 and the pin of arranging around chip carrier 111 112 all around, IC chip 14 is fixed on the chip carrier 111 through bonding die material 13; IC chip 13 is realized being electrically connected through plain conductor 15 with the pin of arranging all around 112; 12 pairs of IC chips 14 of capsulation material, plain conductor 15 and lead frame 11 are sealed with the effect that reaches protection and support, and pin 112 exposes in the bottom surface of capsulation material 12, are welded on through scolder on the circuit board such as PCB to realize and extraneous being electrically connected.The exposed chip carrier in bottom surface 111 is welded on through scolder on the circuit board such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 14 produces.Compare with traditional T SOP and SOIC encapsulation, the QFN encapsulation does not have gull wing lead-in wire, and conductive path is short, and coefficient of self-inductance and impedance are low, thereby good electrical properties can be provided, and can satisfy at a high speed or the application of microwave.Exposed chip carrier provides remarkable heat dispersion.
The continuous enhancing of the raising of As IC integrated level and function, the I/O number of IC increases thereupon, the also corresponding increase of I/O number of pins of corresponding Electronic Packaging; But four traditional limit flat non-pin packaging parts; The pin of individual pen is periphery around chip carrier to be arranged, and has limited the raising of I/O quantity, has satisfied not high density, has had the needs of the IC of more I/O numbers; And owing to have the existence of the plain conductor of certain-length; Can cause the delay of transmission signals and crosstalk, the defective workmanships such as silk that also possibly cause breasting the tape, collapsing, the bank with certain altitude has limited reducing of packaging body thickness.Along with reducing of package body sizes; The power of chip is increasing simultaneously; Cause the density of heat flow rate in the packaging body to improve day by day; Therefore need select for use low thermal resistance material, heat-conducting glue or fin etc. effectively to derive the heat of package interior, remain potted temperature in allowed limits, thereby improve the reliability of packaging body.Traditional lead frame does not have the staircase structural model design; Can't effectively pin plastic material; Cause lead frame and capsulation material bond strength low; Be easy to cause the layering of lead frame and capsulation material even coming off of pin or chip carrier, and can't effectively stop moisture to be diffused into Electronic Packaging inside, thereby had a strong impact on the reliability of packaging body along lead frame and capsulation material combination interface.Traditional Q FN product needs in advance at the lead frame back side Continuous pressing device for stereo-pattern to treat also need remove cleanings such as adhesive tape, plastic packaging material overlap behind the plastic packaging to prevent the flash phenomenon when plastic package process, has increased packaging cost and has increased.Use four traditional limit flat non-pin packaging parts of cutter cutting and separating; Cutter also can cut to the lead frame metal in the cutting capsulation material; Not only can cause the reduction and the shortening in cutting blade life-span of cutting efficiency; And can produce metallic bur power, influenced the reliability of packaging body.Therefore, for the bottleneck of the low I/O quantity that breaks through traditional Q FN, the reliability that improves packaging body with reduce packaging cost, be badly in need of the QFN encapsulation and the manufacturing approach thereof of a kind of high reliability of research and development, low cost, high I/O density.
The utility model content
The utility model provides a kind of high density, thermal-enhanced many circle pin arrangements four limit flat non-pin Flip-Chip Using (Flip Chip Quad Flat Non-lead Package; FCQFN) and manufacturing approach, with the purpose of bottleneck that reaches the low I/O quantity that breaks through traditional Q FN and the reliability that improves packaging body.
To achieve these goals, the utility model adopts following technical proposals:
A kind of thermal-enhanced four limit flat non-pin Flip-Chip Using part structures is characterized in that comprising:
Lead frame has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface, and wherein lead frame comprises chip carrier, a plurality of pin:
Chip carrier is disposed at the lead frame central part, and edge, chip carrier four limit has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface, and
A plurality of pins; Be disposed at around the chip carrier, be many circles around chip carrier and arrange, have staircase structural model along thickness direction; Have upper surface, lower surface and ledge surface, wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface;
First metal material layer is disposed at the upper surface position of lead frame;
Second metal material layer is disposed at the lower surface position of lead frame;
IC chip with salient point is disposed on first metal material layer of lead frame upper surface position through the upside-down mounting welding;
Insulation filling material is disposed under the staircase structural model of lead frame;
Capsulation material coats IC chip, lead frame and first metal material layer with salient point, forms packaging part.
Further, fin is disposed at the IC chip through adhesive material and has no chance on the face.
Further, salient point is disposed at the IC chip and has chance with between face and the chip carrier, and perhaps the heat conduction partition is disposed at the IC chip through adhesive material and has chance with between face and the chip carrier.
Further, above-mentioned lead frame has a plurality of pins of arranging around chip carrier, and the pin shape of cross section is circle or rectangle, and the arrangement number of turns is individual pen, Shuan Quan, more than three circles or three enclose.
Further, many circles pin arrangements mode on the every limit of chip carrier is for being arranged in parallel or being staggered.
According to the embodiment of the utility model, nead frame has a plurality of pins that are three circle arrangements around chip carrier.
According to the embodiment of the utility model, comprise chip carrier and have staircase structural model around the lead frame that chip carrier is the pin that three circles arrange.
According to the embodiment of the utility model, be the rounded shape of shape of cross section of the pin of three circle arrangements around chip carrier.
According to the embodiment of the utility model, be the shape of cross section rectangular shaped of the pin of three circle arrangements around chip carrier.
According to the embodiment of the utility model, the pin arrangements mode on the every limit of chip carrier is for being arranged in parallel.
According to the embodiment of the utility model, the pin arrangements mode on the every limit of chip carrier is for being staggered.
According to the embodiment of the utility model, lead frame upper surface and lower surface dispose first metal material layer and second metal material layer respectively.
According to the embodiment of the utility model, first metal material layer that lead frame upper surface and lower surface dispose respectively and second metal material layer comprise nickel (Ni), palladium (Pd), gold (Au) metal material.
According to the embodiment of the utility model, the IC flip-chip that will have salient point through core equipment in the upside-down mounting is welded the first metal material layer position that is disposed at the lead frame upper surface, and the salient point on the IC chip is connected with lead frame through Reflow Soldering or thermocompression bonding.
According to the embodiment of the utility model, the adhesive material through heat conduction is disposed at the IC chip with the heat conduction partition and has chance with between face and the chip carrier.
According to the embodiment of the utility model, salient point is that three circles are arranged and the face battle array is arranged on the IC chip.
According to the embodiment of the utility model, salient point is lead-free solder salient point, solder containing pb salient point or metal salient point on the IC chip.
According to the embodiment of the utility model, heat conduction separator material kind is the metal material that copper, aluminium etc. have the good heat conductive performance.According to the embodiment of the utility model, the lead frame staircase structural model is the configuration insulation filling material down.
According to the embodiment of the utility model, lead frame staircase structural model configuration insulation filling material kind down is the thermosetting capsulation material, perhaps materials such as plug socket resin, printing ink and resistance weldering green oil.
According to the embodiment of the utility model, fin arrangement has no chance on the face in the IC chip.
According to the embodiment of the utility model, the fin material kind is the metal material that copper, aluminium etc. have the good heat conductive performance.
According to the embodiment of the utility model, expose the IC chip and have no chance face.
The utility model proposes a kind of thermal-enhanced many circle pin arrangements four limit flat non-pin Flip-Chip Using part (FCQFN) manufacturing approaches, may further comprise the steps:
Step 1: configuration mask material layer
The thin plate base material is cleaned and preliminary treatment, have the mask material layer pattern of window in the upper surface of thin plate base material and lower surface configuration.
Step 2: dispose first metal material layer and second metal material layer
In the window of the mask material layer that is disposed at thin plate base material upper surface and lower surface, dispose first metal material layer and second metal material layer respectively.
Step 3: the lower surface selectivity is partially-etched
Removing the mask material layer of thin plate base material lower surface, is resist layer with second metal material layer, and it is partially-etched that thin plate base material lower surface is carried out selectivity, forms groove.
Step 4: configuration insulation filling material
Etch partially fill insulant in the groove of formation in thin plate base material lower part through selectivity.
Step 5: the upper surface selectivity is partially-etched
Removing the mask material layer of thin plate base material upper surface, is corrosion preventing layer with first metal material layer, and it is partially-etched that thin plate base material upper surface is carried out selectivity, forms the lead frame with staircase structural model, comprises the chip carrier and many circle pins of separation.
Step 6A: configuration heat conduction partition (optional)
Adhesive material through heat conduction is disposed at the heat conduction partition on first metal material layer of chip carrier.
Step 6B: configuration has the IC chip of salient point
The IC flip-chip that will have salient point through core equipment in the upside-down mounting is welded the first metal material layer position that is disposed at the lead frame upper surface, and the salient point on the IC chip is connected with lead frame.
Step 7: configuration fin (optional)
Adhesive material through heat conduction with fin arrangement on the face for no reason at all of IC chip.
Step 8: plastic packaging
Coat formation packaging part product array through capsulation material.
Step 9: print
Product array behind the plastic packaging is carried out laser printing.
Step 10: cutting and separating product
The cutting and separating product forms independently single package.
According to the embodiment of the utility model, chemical plating method disposes first metal material layer and second metal material layer through electroplating perhaps.
According to the embodiment of the utility model, be resist layer with first metal material layer and second metal material layer, partially-etched to thin plate base material upper surface and lower surface selectivity.
According to the embodiment of the utility model, insulation filling material is configured in through methods such as silk screen printing or coatings and etches partially in the groove.
According to the embodiment of the utility model, the salient point on the IC chip is connected with interior pin, the chip carrier of many circle pins through Reflow Soldering or thermocompression bonding.
According to the embodiment of the utility model, select method cutting and separating products such as blade cuts, laser cutting or the cutting of water cutter for use, and only cut capsulation material and insulation filling material, not the cutting lead framework.
Based on above-mentioned, according to the utility model, the pin that many circles are arranged has higher I/O density; The staircase structural model of lead frame has increased the bonded area with capsulation material and insulation filling material, has the effect that locks each other with capsulation material and insulation filling material, can effectively prevent the lead frame and the layering of capsulation material and insulation filling material and coming off of pin or chip carrier; Effectively stop moisture from the package structure outside to diffusion inside, the generation of bridging phenomenon when the outer pin of small size size can effectively prevent surface mount, first metal material layer that lead frame upper surface and lower surface dispose respectively and second metal material layer can effectively improve upside-down mounting welding quality and surface mount quality; Salient point on the IC chip has shortened signal transmission path as electrically connected passage, has reduced signal delay and has crosstalked; Also and reduced the height of packaging body, salient point and heat conduction partition have promoted the hot property of packaging body as heat conducting passage; The fin and the IC chip back that dispose on the face for no reason at all of IC chip expose outside packaging body; Increased the packaging body heat dissipation capability, can the heat dispersion of packaging part have been promoted more than 30%, and improved the reliability of packaging body; Owing to only link to each other with insulation filling material between the single packaging body by capsulation material; Therefore when using cutter cutting and separating product, can not cut to the lead frame metal material, thereby improve cutting efficiency; Prolonged the life-span of cutter; Prevent the generation of metallic bur power, saved simultaneously and removed technologies such as glued membrane and plastic packaging material overlap after glued membrane, plastic packaging are pasted in the lead frame back side before the plastic packaging in the traditional Q FN encapsulation flow process, reduced packaging cost.
Hereinafter is special lifts embodiment, and conjunction with figs. elaborates to the above-mentioned feature and advantage of the utility model.
Description of drawings
Figure 1A is the schematic rear view of traditional Q FN encapsulating structure;
Figure 1B is the generalized section along the I-í section among Figure 1A;
Fig. 2 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear views of thermal-enhanced many circle pin arrangements FCQFN encapsulating structures of being arranged in parallel;
Fig. 2 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the thermal-enhanced schematic rear views that enclose pin arrangements FCQFN encapsulating structures that are arranged in parallel more;
Fig. 3 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear views of staggered thermal-enhanced many circle pin arrangements FCQFN encapsulating structures;
Fig. 3 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of staggered thermal-enhanced many circle pin arrangements FCQFN encapsulating structures;
Fig. 4 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 5 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 6 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 7 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 8 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 9 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Figure 10 A to Figure 10 L is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized sections of thermal-enhanced many circle pin arrangements FCQFN package structures of the embodiment drafting of the utility model.
Label among the figure: 100. traditional four limit flat non-leaded packages, 11. nead frames, 111. chip carriers, 112. pins, 12. capsulation materials; 13. the bonding die material, 14.IC chip, 15. plain conductors, 200, the thermal-enhanced many circle pin arrangements four limit flat non-pin Flip-Chip Using part structures of 200a, 200b, 200c, 200d, 200A, 200B, 200C, 200D, 200E, 200F.; 201. lead frame, 202. chip carriers, 203. pins, 20. thin plate base materials; 20a. thin plate base material upper surface, lead frame upper surface, 20b. thin plate base material lower surface, lead frame lower surface, 21a, 21b. mask material layer, 22. first metal material layers; 23. second metal material layer, the 22a. first metal material laminar surface, the 23a. second metal material laminar surface, 24. grooves; 24a. staircase structural model is surperficial, 24b. staircase structural model, 25. insulation filling materials, 25a. insulation filling material surface; The face 26.IC chip, 26a.IC chip are had chance with, the 26b.IC chip has no chance face, 27. salient points; 28. adhesive material, 29. fin, 30. capsulation materials, 31. heat conduction partitions.
Embodiment
Below in conjunction with accompanying drawing the utility model is elaborated:
Fig. 2 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear views of thermal-enhanced many circle pin arrangements FCQFN encapsulating structures of being arranged in parallel.Fig. 2 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the thermal-enhanced schematic rear views that enclose pin arrangements FCQFN encapsulating structures that are arranged in parallel more.
Can find out with reference to above-mentioned Fig. 2 A-B; In the present embodiment; The lead frame 201 of thermal-enhanced many circle pin arrangements FCQFN encapsulating structure 200a and 200b comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202; And the arrangement mode of the pin 203 on chip carrier 202 every limits disposes second metal material layer 23 for being arranged in parallel at lead frame 201 lower surfaces, in lead frame 201, disposes insulation filling material 25.Difference is that thermal-enhanced pin cross sections that enclose in the pin arrangements four limit flat non-pin Flip-Chip Using part structures of Fig. 2 A are circle more, and the pin cross section in thermal-enhanced many circle pin arrangements four limit flat non-pin Flip-Chip Using part structures of Fig. 2 B is a rectangle.
Fig. 3 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear views of staggered thermal-enhanced many circle pin arrangements FCQFN encapsulating structures.Fig. 3 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of staggered thermal-enhanced many circle pin arrangements FCQFN encapsulating structures.
Can find out with reference to above-mentioned Fig. 3 A-B; In the present embodiment; The lead frame 201 of thermal-enhanced many circle pin arrangements FCQFN encapsulating structure 200c and 200d comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202; And the arrangement mode of the pin 203 on chip carrier 202 every limits disposes second metal material layer 23 for being staggered at lead frame 201 lower surfaces, in lead frame 201, disposes insulation filling material 25.Difference is that thermal-enhanced pin cross sections that enclose in the pin arrangements four limit flat non-pin Flip-Chip Using part structures of Fig. 3 A are circle more, and the pin cross section in thermal-enhanced many circle pin arrangements four limit flat non-pin Flip-Chip Using part structures of Fig. 3 B is a rectangle.
Fig. 4 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B; With reference to Fig. 4; In the present embodiment, thermal-enhanced many circle pin arrangements FCQFN encapsulating structure 200A comprise lead frame 201, first metal material layer 22, second metal material layer 23, insulation filling material 25, IC chip 26, salient point 27, adhesive material 28, fin 29, capsulation material 30.
Fig. 5 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B; With reference to Fig. 5; In the present embodiment, thermal-enhanced many circle pin arrangements FCQFN encapsulating structure 200B comprise lead frame 201, first metal material layer 22, second metal material layer 23, insulation filling material 25, IC chip 26, salient point 27, adhesive material 28, fin 29, capsulation material 30.
Fig. 6 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B; With reference to Fig. 6; In the present embodiment, thermal-enhanced many circle pin arrangements FCQFN encapsulating structure 200C comprise lead frame 201, first metal material layer 22, second metal material layer 23, insulation filling material 25, IC chip 26, salient point 27, adhesive material 28, fin 29, capsulation material 30, heat conduction partition 31.
In the embodiment of Fig. 4, Fig. 5 and Fig. 6; Lead frame 201 is as the passage of conduction, heat radiation, connection external circuit; Have staircase structural model 24b along thickness direction, have upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 24a of staircase structural model 24b.Lead frame 201 comprises chip carrier 202 and is the pins 203 that many circles are arranged around chip carrier 202, chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and all have staircase structural model 24b.Chip carrier 202 is disposed at lead frame 201 central parts, and edge, chip carrier 202 4 limit has staircase structural model 24b along thickness direction.A plurality of pins 203 are disposed at around the chip carrier 202; Being many circles around chip carrier 202 arranges; And has ledge structure 24b along thickness direction; Its shape of cross section is rounded or rectangular-shaped, and wherein each pin 203 comprises interior pin that is disposed at this upper surface 20a and the outer pin that is disposed at this lower surface 20b.
First metal material layer 22 and second metal material layer 23 are disposed at the upper surface 20a position of lead frame 201 and the lower surface 20b position of lead frame 201 respectively; First metal material layer 22 has the same size size with the interior pin of pin 203, and second metal material layer 23 has the same size size with the outer pin of pin 203.First metal material layer 22 has metal material laminar surface 22a, and second metal material layer 23 has metal material laminar surface 23a.
Fig. 4, Fig. 5 and embodiment difference shown in Figure 6 are; In the embodiment of Fig. 4; The a plurality of salient points 27 upside-down mountings welding that is three circle arrangements of IC chip 26 is disposed at respectively on the interior pin of a plurality of pins 203 that are three circle arrangements; No salient point 27 upside-down mountings welding is disposed on the chip carrier 202; In the embodiment of Fig. 5, a plurality of salient points 27 upside-down mountings welding that is the arrangement of face battle array of IC chip 26 is disposed at respectively on the interior pin and chip carrier 202 of a plurality of pins 203 that are three circle arrangements, in the embodiment of Fig. 6; The a plurality of salient points 27 upside-down mountings welding that is three circle arrangements of IC chip 26 is disposed at respectively on the interior pin of a plurality of pins 203 that are three circle arrangements, and heat conduction partition 31 is disposed between IC chip 26 and the chip carrier 202 through adhesive material 28.
In the embodiment of Fig. 7, Fig. 8 and Fig. 9; Lead frame 201 is as the passage of conduction, heat radiation, connection external circuit; Have staircase structural model 24b along thickness direction, have upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 24a of staircase structural model 24b.Lead frame 201 comprises chip carrier 202 and is the pins 203 that many circles are arranged around chip carrier 202, chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and all have staircase structural model 24b.Chip carrier 202 is disposed at lead frame 201 central parts, the rectangular shape of its shape of cross section, and edge, chip carrier 202 4 limit has staircase structural model 24b along thickness direction.A plurality of pins 203 are disposed at around the chip carrier 202; Being many circles around chip carrier 202 arranges; And has ledge structure 24b along thickness direction; Its shape of cross section is rounded or rectangular-shaped, and wherein each pin 203 comprises interior pin that is disposed at this upper surface 20a and the outer pin that is disposed at this lower surface 20b.
First metal material layer 22 and second metal material layer 23 are disposed at the upper surface 20a position of lead frame 201 and the lower surface 20b position of lead frame 201 respectively; First metal material layer 22 has the same size size with the interior pin of pin 203, and second metal material layer 23 has the same size size with the outer pin of pin 203.First metal material layer 22 has metal material laminar surface 22a, and second metal material layer 23 has metal material laminar surface 23a.
Expose the face 26b for no reason at all of IC chip 26, the heat that the IC chip is produced is transferred in the external environment condition directly, fast, to promote the heat dispersion of packaging part.
Fig. 7, Fig. 8 and embodiment difference shown in Figure 9 are; In the embodiment of Fig. 7; The a plurality of salient points 27 upside-down mountings welding that is three circle arrangements of IC chip 26 is disposed at respectively on the interior pin of a plurality of pins 203 that are three circle arrangements; No salient point 27 upside-down mountings welding is disposed on the chip carrier 202, and in the embodiment of Fig. 8, a plurality of salient points 27 upside-down mountings welding that is the arrangement of face battle array of IC chip 26 is disposed at respectively on the interior pin and chip carrier 202 of a plurality of pins 203 that are three circle arrangements; In the embodiment of Fig. 9, heat conduction partition 31 is disposed between IC chip 26 and the chip carrier 202 through heat conduction adhesive material 28.
Figure 10 A to Figure 10 L is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized sections of thermal-enhanced many circle pin arrangements FCQFN package structures of the embodiment drafting of the utility model.
Please with reference to Figure 10 A; Provide to have upper surface 20a and with respect to the thin plate base material 20 of the lower surface 20b of upper surface 20a, the material of thin plate base material 20 can be that copper, copper alloy, iron, ferroalloy, nickel, nickel alloy and other are applicable to the metal material of making lead frame.The thickness range of thin plate base material 20 is 0.1mm-0.25mm, for example is 0.127mm, 0.152mm, 0.203mm.Upper surface 20a and lower surface 20b to thin plate base material 20 clean and preliminary treatment, for example use plasma water degreasing, dust etc., with the upper surface 20a of realization thin plate base material 20 and the purpose of lower surface 20b cleaning.
Please with reference to Figure 10 B; Configuration has the mask material layer 21a and the mask material layer 21b of window respectively on the upper surface 20a of thin plate base material 20 and lower surface 20b; Window described here is meant not by the thin plate base material 20 of mask material layer 21a and mask material layer 21b covering; Mask material layer 21a and mask material layer 21b protection will be to being carried out etching by the thin plate base material 20 of mask material layer 21a and mask material layer 21b covering in the processing step of back by the thin plate base material 20 of its covering.
Please with reference to Figure 10 C; Configuration first metal material layer 22 in the window of mask material layer 21a on being disposed at the upper surface 20a of thin plate base material 20; First metal material layer 22 has the first metal material laminar surface 22a; Configuration second metal material layer 23, the second metal material layers 23 have the second metal material laminar surface 23a in the window of mask material layer 21b on being disposed at the lower surface 20b of thin plate base material 20.The collocation method of first metal material layer 22 and second metal material layer 23 is methods such as plating, chemical plating, evaporation, sputter; And allow to form by the different metallic material; In the present embodiment, preferential selection plating or chemical plating are as the collocation method of first metal material layer 22 and second metal material layer 23.The material of first metal material layer 22 and second metal material layer 23 is nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin metal material and alloys thereof such as (Sn); In the present embodiment; First metal material layer 22 and second metal material layer 23 for example are nickel-palladium-gold plates; For first metal material layer 22; The gold plate of outside is to guarantee the upside-down mounting welding quality of salient point 27 on lead frame 201 with middle palladium coating; The nickel coating of the inside is as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction, and blocked up cocrystalization compound influence the regional reliability of bonding, for second metal material layer 23; But the gold plate of outside is to guarantee the wettability of scolder at lead frame 201 with middle palladium coating; Improve the quality that packaging body mounts at circuit board upper surfaces such as PCB, the nickel coating of the inside is that blocked up cocrystalization compound influences the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction.
Please with reference to Figure 10 D; Mask material layer 21b on the lower surface 20b of thin plate base material 20 removed; The method that removes in the present embodiment can be chemical reaction method and mechanical means, and chemical reaction method is an alkaline solution of selecting solubility for use, for example potassium hydroxide (KOH), NaOH (NaOH); Adopt the mask material layer 21b on the lower surface 20b of mode such as spray and thin plate base material 20 to carry out chemical reaction; Thereby its dissolving is reached the effect that removes, remove mask material layer 21b after, only remaining second metal material layer 23 on the lower surface 20b of thin plate base material 20.
Please with reference to Figure 10 E; With second metal material layer 23 on the lower surface 20b of thin plate base material 20 as etched resist layer; It is partially-etched to adopt the spray mode that thin plate base material 20 lower surface 20b are carried out selectivity; Form groove 24 and staircase structural model surface 24a, the etch depth scope can be the 40%-90% that accounts for the thickness of thin plate base material 20.In the present embodiment, the preferential employing of spray mode gone up the spray mode, and etching solution is preferentially selected alkaline etching liquid, like alkaline etching liquids such as alkaline copper chloride etching solution, ammonium chlorides, to reduce the destruction of etching solution to second metal material layer 23.
Please with reference to Figure 10 F; Lower surface 20b at thin plate base material 20 fills insulation filling material 25 in the groove 24 of the partially-etched formation of selectivity; Insulation filling material 25 has insulation filling material surface 25a, and this surface and the second metal material layer 23a are on the same horizontal plane.In the present embodiment; Insulation filling material 25 is insulating material such as thermosetting capsulation material, plug socket resin, printing ink and resistance weldering green oil; Insulation filling material 25 has enough acidproof, alkali resistance; To guarantee that follow-up technology can not damage forming insulation filling material 25, the fill method of insulation filling material 25 is to be filled in the groove 24 through methods such as injection moulding or silk screen printings, and too much insulation filling material 25 is removed with mechanical grinding method or chemical treatment method in the configuration back; To eliminate the flash of insulation filling material 25; The insulation filling material surface 25a and the second metal material laminar surface 23a of insulation filling material 25 are on the same horizontal plane,, remove flash through developing method for insulation filling materials 25 such as photosensitive type resistance weldering green oils.
Please with reference to Figure 10 G; Mask material layer 21a on the upper surface 20a of thin plate base material 20 removed; The method that removes in the present embodiment can be chemical reaction method and mechanical means, and chemical reaction method is an alkaline solution of selecting solubility for use, for example potassium hydroxide (KOH), NaOH (NaOH); Adopt the mask material layer 21a chemical reaction on the upper surface 20a of mode such as spray and thin plate base material 20; Thereby its dissolving is reached the effect that removes, remove mask material layer 21a after, only remaining first metal material layer 22 on the upper surface 20a of thin plate base material 20.
Please with reference to Figure 10 H; With first metal material layer 22 on the upper surface 20a of thin plate base material 20 as etched resist layer; It is partially-etched to adopt the spray mode that thin plate base material 20 upper surface 20a are carried out selectivity, is etched to staircase structural model surface 24a, exposes insulation filling material 25.Form lead frame 201; Lead frame 201 comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202; Dispose insulation filling material 25 in the lead frame 201, i.e. chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and be fixed together through insulation filling material 25.Pin and outer pin in the pin 203 of the separation that after selectivity is partially-etched, forms has, the salient point 27 of interior pin connection IC chip 26 in follow-up IC flip-chip welding technology, outer pin is as the passage of connection external circuit.Form staircase structural model 24b, staircase structural model 24b has staircase structural model surface 24a.In the present embodiment, the preferential employing of the spray mode of etching solution gone up the spray mode, and etching solution is preferentially selected alkaline etching liquid, like alkaline etching liquids such as alkaline copper chloride etching solution, ammonium chlorides, to reduce the destruction of etching solution to first metal material layer 22.
Please with reference to Figure 10 I, IC chip 26 have the face of having chance with 26a and with the corresponding face 26b for no reason at all of the face 26a that has chance with, and be a plurality of salient points 27 that three circles arrange and be disposed on the face of the having chance with 26a of IC chip 26.Through core equipment in the upside-down mounting with first metal material layer 22 positions of IC chip 26 flip-chip configuration in lead frame upper surface 20a; The a plurality of salient points 27 that are three circle arrangements on the IC chip 26 are disposed at respectively on the interior pin of a plurality of pins 203 that are three circle arrangements; In the present embodiment, salient point 27 is lead-free solder salient point, solder containing pb salient point or metal salient point on the IC chip 26.
Please with reference to Figure 10 J, a plurality of salient points 27 that three circles arrange of being on the IC chip 26 are connected on a plurality of interior pins that are a plurality of pins 203 that three circles arrange that dispose first metal material layer 22, to realize electrical interconnection through Reflow Soldering or thermocompression bonding.
Please, adopt the adhesive material 28 of heat conduction that fin 29 is disposed on the face 26b for no reason at all of IC chip 26 with reference to Figure 10 K.
Please with reference to Figure 10 L; Adopt injection moulding process; Coat above-mentioned IC chip 26, salient point 27, adhesive material 28, fin 29, lead frame 201 and first metal material layer 22 through environment-friendly type plastic closure material 30; Form product array, expose second metal material layer 23 that is disposed at lead frame lower surface 20b and the face 26b for no reason at all of IC chip 26.In the present embodiment; Capsulation material 30 can be materials such as thermosetting polymer; The insulation filling material 25 of being filled has the physical property similar with capsulation material 30, and thermal coefficient of expansion for example is to reduce the product failure that is caused by thermal mismatching; Improve reliability of products, insulation filling material 25 can be a commaterial with capsulation material 30.Toasting the back behind the plastic packaging solidifies; Capsulation material 30 has mutual lock function with insulation filling material 25 and the lead frame 201 with staircase structural model 24b; Can effectively prevent lead frame 201 and capsulation material 30 and the layering of insulation filling material 25 and coming off of pin 203 or chip carrier 202; And effectively stop moisture to be diffused into package interior along the combination interface of lead frame 201 and capsulation material 30 and insulation filling material 25, improved the reliability of packaging body.Behind the plastic packaging product array is carried out laser printing.
Please with reference to Figure 10 M; Cut thermal-enhanced many circle pin arrangements FCQFN products of separated arrays; Thoroughly cutting and separating capsulation material 30 forms single thermal-enhanced many circle pin arrangements FCQFN packaging parts 200 with insulation filling material 25; In the present embodiment, single product separation method is methods such as blade cuts, laser cutting or the cutting of water cutter, and only cuts capsulation material 30 and insulation filling material 25; Cutting lead framework metal material is not only drawn out 2 thermal-enhanced many circle pin arrangements FCQFN packaging parts 200 after the cutting and separating among Figure 10 M.
The description of the embodiment of the utility model is from effective explanation and describes the purpose of the utility model; Be not in order to limit the utility model; Those skilled in the art is to be understood that under any: under the condition of utility model design that does not break away from the utility model and scope, can change the foregoing description.So the utility model is not limited to the specific embodiment that disclosed, but cover the essence and the interior modification of scope of the defined the utility model of claim.
Claims (5)
1. thermal-enhanced four limit flat non-pin Flip-Chip Using part structures is characterized in that comprising:
Lead frame has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface, and wherein lead frame comprises chip carrier, a plurality of pin:
Chip carrier is disposed at the lead frame central part, and edge, chip carrier four limit has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface, and
A plurality of pins; Be disposed at around the chip carrier, be many circles around chip carrier and arrange, have staircase structural model along thickness direction; Have upper surface, lower surface and ledge surface, wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface;
First metal material layer is disposed at the upper surface position of lead frame;
Second metal material layer is disposed at the lower surface position of lead frame;
IC chip with salient point is disposed on first metal material layer of lead frame upper surface position through the upside-down mounting welding;
Insulation filling material is disposed under the staircase structural model of lead frame;
Capsulation material coats IC chip, lead frame and first metal material layer with salient point, forms packaging part.
2. a kind of thermal-enhanced four limit flat non-pin Flip-Chip Using part structures according to claim 1 is characterized in that fin is disposed at the IC chip through adhesive material and has no chance on the face.
3. a kind of thermal-enhanced four limit flat non-pin Flip-Chip Using part structures according to claim 2; It is characterized in that; Salient point is disposed at the IC chip and has chance with between face and the chip carrier, and perhaps the heat conduction partition is disposed at the IC chip through adhesive material and has chance with between face and the chip carrier.
4. a kind of thermal-enhanced four limit flat non-pin Flip-Chip Using part structures according to claim 1; It is characterized in that; Above-mentioned lead frame has a plurality of pins of arranging around chip carrier; The pin shape of cross section is circle or rectangle, and the arrangement number of turns is individual pen, Shuan Quan, more than three circles or three enclose.
5. a kind of thermal-enhanced four limit flat non-pin Flip-Chip Using part structures according to claim 1 is characterized in that many circles pin arrangements mode on the every limit of chip carrier is for being arranged in parallel or being staggered.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120575398 CN202495438U (en) | 2011-12-31 | 2011-12-31 | Thermal-enhanced flip-chip quad flat non-lead package |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201120575398 CN202495438U (en) | 2011-12-31 | 2011-12-31 | Thermal-enhanced flip-chip quad flat non-lead package |
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| CN202495438U true CN202495438U (en) | 2012-10-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015083043A1 (en) * | 2013-12-04 | 2015-06-11 | International Business Machines Corporation | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| CN105762084A (en) * | 2016-04-29 | 2016-07-13 | 南通富士通微电子股份有限公司 | Packaging method and packaging device for flip chip |
-
2011
- 2011-12-31 CN CN 201120575398 patent/CN202495438U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015083043A1 (en) * | 2013-12-04 | 2015-06-11 | International Business Machines Corporation | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| GB2536383A (en) * | 2013-12-04 | 2016-09-14 | Ibm | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| GB2536383B (en) * | 2013-12-04 | 2017-02-01 | Ibm | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| US10153250B2 (en) | 2013-12-04 | 2018-12-11 | International Business Machines Corporation | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| US10886254B2 (en) | 2013-12-04 | 2021-01-05 | International Business Machines Corporation | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| US11251160B2 (en) | 2013-12-04 | 2022-02-15 | International Business Machines Corporation | Manufacturing of flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| CN105762084A (en) * | 2016-04-29 | 2016-07-13 | 南通富士通微电子股份有限公司 | Packaging method and packaging device for flip chip |
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