CN103021876A - Method for manufacturing high-density QFN (quad flat no-lead) package device - Google Patents
Method for manufacturing high-density QFN (quad flat no-lead) package device Download PDFInfo
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- CN103021876A CN103021876A CN2012105495266A CN201210549526A CN103021876A CN 103021876 A CN103021876 A CN 103021876A CN 2012105495266 A CN2012105495266 A CN 2012105495266A CN 201210549526 A CN201210549526 A CN 201210549526A CN 103021876 A CN103021876 A CN 103021876A
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a method for manufacturing a high-density QFN (quad flat no-lead) package device. The chip load and pins of the manufactured high-density QFN package device do not need to be based on a lead frame manufactured in advance, chip carriers and pins with step structures are formed by organically combining etching, electroplating and chemical plating methods in a package technical process, insulated filling materials are arranged in grooves among outer chip carriers and outer pins and among the outer pins by an injection molding or silk-screen printing method, plastic package materials are used for coating and sealing, and the independent chip carriers and the independent pins are formed by an etching or mechanical grinding method. The manufactured QFN package device with the arranged multi-turn pins has high I/O (input/output) density and fine reliability.
Description
Technical field
The present invention relates to high density QFN components and parts manufacturing technology field, refer more particularly to the manufacture method of four limit flat leadless package parts with high I/O density.
Background technology
Along with electronic product such as mobile phone, notebook computer etc. towards miniaturization, portable, ultrathin, multimedization and satisfy popular needed low-cost future development, high density, high-performance, high reliability and packing forms and packaging technology thereof have obtained fast development cheaply.Compare with packing forms such as expensive BGA, fast-developing novel encapsulated technology in recent years, i.e. four limit flat non-pin QFN(Quad Flat Non-lead Package) encapsulation, because have good hot property and electrical property, size is little, cost is low and the many merits such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Figure 1A and Figure 1B are respectively tradition without the schematic rear view of the QFN encapsulating structure of staircase structural model design with along the generalized section of I-í section; this QFN encapsulating structure comprises lead frame 11; capsulation material 12; adhesive material 13; IC chip 14; plain conductor 15; wherein lead frame 11 comprises chip carrier 111 and the pin 112 of arranging around chip carrier 111 all around; IC chip 14 is fixed on the chip carrier 111 by adhesive material 13; IC chip 14 is realized electrical connection with the pin 112 of arranging by plain conductor 15 all around; 12 pairs of IC chips 14 of capsulation material; plain conductor 15 and lead frame 11 seal to reach the effect of protection and support; pin 112 exposes in the bottom surface of capsulation material 12, is welded on by scolder on the circuit board such as PCB to realize and extraneous electrical connection.The exposed chip carrier in bottom surface 111 is welded on by scolder on the circuit board such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 14 produces.With traditional TSOP with SOIC encapsulation compare, the QFN encapsulation does not have gull wing lead-in wire, conductive path is short, coefficient of self-inductance and impedance are low, thereby good electrical property can be provided, and can satisfy at a high speed or the application of microwave.Exposed chip carrier provides remarkable heat dispersion.
Along with the raising of IC integrated level and the continuous enhancing of function, the I/O number of IC increases thereupon, the also corresponding increase of I/O number of pins of corresponding Electronic Packaging, but four traditional limit flat leadless package parts, the pin of individual pen is periphery around chip carrier and arranges, limited the raising of I/O quantity, do not satisfied high density, have the needs of the IC of more I/O numbers.Even traditional QFN encapsulation without the ledge structure design has the pin that multi-turn is arranged, owing to can't effectively pin capsulation material, cause lead frame and capsulation material bond strength low, be easy to cause the layering of lead frame and capsulation material even coming off of pin or chip carrier, and can't effectively stop moisture to be diffused into Electronic Packaging inside along lead frame and capsulation material combination interface, had a strong impact on the reliability of packaging body.Even traditional QFN encapsulation has the ledge structure design, can only be based on that individual pen pin or staggered multi-circle pin realize, each outer end of all pins must extend to packaging body one side, be exposed in the external environment condition, it is inner to cause moisture very easily to diffuse to encapsulation, affect the reliability of product, and because the restriction in space can't realize more highdensity encapsulation at all.The chip load of traditional Q FN encapsulation and pin must be based on the lead frame structure of prior making moulding, otherwise chip load be connected shortage mechanical support and connection and and and can't finish all potting process with pin.Need when traditional Q FN is encapsulated in plastic package process in advance at lead frame back side Continuous pressing device for stereo-pattern behind plastic packaging, also need to remove the cleanings such as adhesive tape, plastic packaging material overlap to prevent the flash phenomenon, increased packaging cost and increased.Therefore, the bottleneck for the low I/O quantity that breaks through traditional Q FN encapsulation solves the above-mentioned reliability of traditional Q FN encapsulation and reduces packaging cost, is badly in need of QFN packaging and the manufacture method thereof of a kind of high reliability of research and development, low cost, high I/O density.
Summary of the invention
The invention provides a kind of manufacture method of high density QFN packaging, with the bottleneck that reaches the low I/O quantity that breaks through traditional Q FN encapsulation, high packaging cost and the purpose that improves the reliability of packaging body.
To achieve these goals, the present invention adopts following technical proposals, may further comprise the steps:
Step 1: adopt the exposure imaging method, form the mask material layer with window at the metal base upper surface.
Step 2: as resist layer, the metal base upper surface is carried out etching with mask material layer with window, form outer chip carrier, outer pin and groove.
Step 3: remove the mask material layer that is disposed at the metal base upper surface.
Step 4: adopt injection moulding or method for printing screen outside between chip carrier and the outer pin, dispose insulation filling material in the groove between outer pin and the outer pin.
Step 5: adopt the exposure imaging method, make the mask material layer with window at the surface location of insulation filling material.
Step 6: adopt successively chemical plating and electro-plating method in the window of mask material layer, make in chip carrier and interior pin, formation has the chip carrier pin of ledge structure, wherein chip carrier comprises interior chip carrier and outer chip carrier, and pin comprises interior pin and outer pin.
Step 7: adopt plating or chemical plating method at the surface of interior chip carrier and interior pin configuration the first metal material layer.
Step 8: the mask material layer that removes the surface that is disposed at insulation filling material.
Step 9: by adhesive material with the IC chip configuration on first metal material layer on interior chip carrier or interior pin surface.
A plurality of bonding welding pads on the step 10:IC chip are connected to respectively the first metal material layer of interior chip carrier and interior pin configuration by plain conductor.
Step 11: adopt injection moulding process to coat sealing IC chip, adhesive material, plain conductor, interior carrier, interior pin and the first metal material layer with capsulation material.
Step 12: the rear solidifying requirements according to selected capsulation material is carried out rear curing.
Step 13: adopt mechanical grinding method or engraving method that metal base is carried out attenuate, form independently chip carrier and pin.
Step 14: adopt chemical plating method to make the second metal material layer on the surface of chip carrier and outer pin outside.
Step 15: the cutting and separating product forms independently single package.
According to embodiments of the invention, the chip carrier of formation is comprised of interior chip carrier and outer chip carrier, makes the pin that forms and is comprised of interior pin and outer pin.
According to embodiments of the invention, before metal base was carried out attenuate, the chip carrier of formation linked to each other with metal base with pin.
According to embodiments of the invention, adopt mechanical grinding method or engraving method that metal base is carried out attenuate, realize independently chip carrier and pin.
According to embodiments of the invention, the size of interior chip carrier and interior pin is respectively greater than the size of outer chip carrier and outer pin.
According to embodiments of the invention, adopt insulation filling material and capsulation material to carry out secondary and coat sealing formation packaging.
According to embodiments of the invention, make the packaging that forms and have a plurality of pins that are the multi-turn arrangement around chip carrier.
According to embodiments of the invention, make the packaging that forms and have the pin that is the arrangement of face battle array.
According to embodiments of the invention, the arrangement mode of a plurality of pins that manufacturing forms is not limit, and can be to be arranged in parallel, and can be to be staggered yet.
According to embodiments of the invention, make the shape of cross section of a plurality of pins that form and do not limit, can be circle, also can be rectangle.
According to embodiments of the invention, chip carrier and the pin of making the packaging that forms have ledge structure.
Based on above-mentioned, according to the present invention, the chip load of the high density QFN packaging that manufacturing forms and pin need not the lead frame structure based on prior making moulding, namely need not to rely on traditional lead frame provide mechanical support be connected with connection but in potting process, at first adopt and have the precision of making height, the engraving method of the controlled characteristics such as strong is made outer pin and outer chip carrier, then in groove, dispose insulation filling material, then adopt successively and have the precision of making height, evenness is good, pin and interior chip carrier in the chemical plating of the controlled characteristics such as strong and electro-plating method are made, at last after plastic package process is finished, it is low that employing has a cost, the mechanical grinding method of the characteristics such as evenness is good, perhaps adopt and have the precision of making height, the thickness of the whole attenuate metal base of engraving method of the controlled characteristics such as strong forms the chip carrier and the pin that independently have ledge structure.The present invention adopts the secondary encapsulating method, namely adopt insulation filling material and capsulation material to carry out secondary and coat sealing, wherein insulation filling material is disposed in the groove of chip carrier and the ledge structure below, the above zone of staircase structural model adopts capsulation material to coat sealing, what this filling, clad structure feature can realize encapsulating seals without the cavity, eliminates because of defectives such as the bubble of sealing incomplete generation, cavities.The high density QFN packaging that the present invention makes formation has high I/O density, the staircase structural model of chip carrier and pin has increased the bonded area with capsulation material, has the effect that mutually locks with capsulation material, can effectively prevent chip carrier and the layering of pin and capsulation material and coming off of pin or chip carrier, effectively stop moisture to the encapsulation diffusion inside, the generation of bridging phenomenon when the outer pin of small size size can effectively prevent surface mount, chip carrier and pin upper, the metal material layer of lower surface configuration can Effective Raise metal lead wire bonding quality and surface mount quality, has good reliability, and the arrangement mode of pin is not limit, can be for being arranged in parallel, also can be for being staggered, all pins need not to extend to packaging body one side.
Embodiment cited below particularly, and cooperate accompanying drawing that above-mentioned feature and advantage of the present invention are elaborated.
Description of drawings
Figure 1A is the schematic rear view of traditional Q FN encapsulating structure;
Figure 1B is the generalized section along the I-í section among Figure 1A;
Fig. 2 A be the pin cross section drawn according to embodiments of the invention 1 for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of the high density QFN packaging that is arranged in parallel;
Fig. 2 B is along the I-among Fig. 2 A
IThe generalized section of section;
Fig. 3 A to Fig. 3 O is that all generalized sections all are along the generalized section shown in Fig. 2 B section according to the manufacturing process generalized section of the high density QFN packaging of embodiments of the invention 1 drafting.
The schematic rear view with high density QFN packaging of being face battle array pin arrangements of Fig. 4 for drawing according to embodiments of the invention 2;
Fig. 5 A is along the I-among Fig. 4
IThe first generalized section of section.
Fig. 5 B is along the I-among Fig. 4
IThe second generalized section of section.
Number in the figure: 100. traditional four limit flat non-pin encapsulation, 11. lead frames, 111. chip carriers, 112. pin, 12. capsulation materials, 13. adhesive materials, 14.IC chip, 15. plain conductors, 200. have the high density QFN encapsulation that multi-circle pin is arranged, 300. have the high density QFN encapsulation that is face battle array pin arrangements, 20. metal bases, 20a. metal base upper surface, 20b. the metal base lower surface, 21. mask material layers, 22. chip carriers, 22a. chip carrier in the outer chip carrier, 22b., 23. pins, 23a. outer pin, 23b. interior pin, 24. grooves, 25. insulation filling materials, 26. mask material layer, 27. ledge structure, 28. first metal material layers, 29. adhesive materials, 30.IC chip, 31. plain conductor, 32. capsulation materials, 33. second metal material layers.
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing:
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view with high density QFN packaging that multi-circle pin arranges that is arranged in parallel.
Can find out with reference to above-mentioned Fig. 2 A, in the present embodiment, high density QFN packaging 200 with multi-circle pin arrangement has chip carrier 22 and is the pin 23 that multi-turn is arranged around chip carrier 22, the arrangement mode of the pin 23 on chip carrier 22 every limits is for being arranged in parallel, the cross section of pin 23 is circular, surface configuration at chip carrier 22 and pin 23 has the second metal material layer 33, disposes insulation filling material 25 in high density QFN packaging 200.The arrangement mode of pin 23 is not defined as and is arranged in parallel in the present embodiment, can be other arrangement modes, and the shape of cross section of pin 23 is not defined as circle, can be rectangle.
Fig. 2 B is along the I-among Fig. 2 A
IThe generalized section of section.In conjunction with Fig. 2 A, with reference to Fig. 2 B, in the present embodiment, high density QFN packaging 200 with multi-circle pin arrangement comprises chip carrier 22, pin 23, insulation filling material 25, ledge structure 27, the first metal material layer 28, adhesive material 29, IC chip 30, plain conductor 31, capsulation material 32 and the second metal material layer 33, wherein chip carrier 22 comprises outer chip carrier 22a and interior chip carrier 22b, and pin 23 comprises outer pin 23a and interior pin 23b.
Chip carrier 22 is disposed at the central part of the high density QFN packaging 200 with multi-circle pin arrangement, the rectangular shape of its shape of cross section.Pin 23 is multi-turn around chip carrier 22 to be arranged, and its shape of cross section is rounded or rectangular-shaped.Chip carrier 22 is connected with pin as the passage of conduction, heat radiation, connection external circuit, has ledge structure 27.Insulation filling material 25 is disposed at ledge structure 27 belows of chip carrier 22 and pin 23.The first metal material layer 28 and the second metal material layer 33 are disposed at respectively upper surface and the lower surface of chip carrier 22 and pin 23.IC chip 30 is disposed at the first metal material layer 28 positions on the chip carrier 22 by adhesive material 29, a plurality of bonding welding pads on the IC chip 30 are connected to respectively the first metal material layer 28 of interior chip carrier 22b and interior pin 23b configuration by plain conductor 31, realize electrical interconnection and ground connection.Capsulation material 32 coats the above-mentioned IC chip 30 of sealing, adhesive material 29, plain conductor 31, interior chip carrier 22b, interior pin 23b and the first metal material layer 28; expose the second metal material layer 33 that is disposed on outer chip carrier 22a and the outer pin 23a, the high density QFN packaging 200 with multi-circle pin arrangement is played the effect of supporting with protection.
The below will describe with Fig. 3 A to Fig. 3 O the manufacturing process of the high density QFN packaging with multi-circle pin arrangement in detail.
Fig. 3 A to Fig. 3 O is that all generalized sections all are along the generalized section shown in Fig. 2 B section according to the manufacturing process generalized section of the high density QFN packaging with multi-circle pin arrangement of embodiments of the invention 1 drafting.
Please refer to Fig. 3 A, provide and have upper surface 20a and with respect to the metal base 20 of the lower surface 20b of upper surface 20a, the material of metal base 20 can be that copper, copper alloy, iron, ferroalloy, nickel, nickel alloy and other are applicable to make the metal material of chip carrier and pin, preferentially selects copper or Cu alloy material.The thickness range of metal base 20 is 0.1mm-0.3mm.Upper surface 20a and lower surface 20b to metal base 20 clean and preliminary treatment, such as using plasma water degreasing, dust etc., with the upper surface 20a of realization metal base 20 and the purpose of lower surface 20b cleaning.
Please refer to Fig. 3 B; on the upper surface 20a of metal base 20, make the mask material layer 21 with window by the exposure imaging method; window described here refers to that not by the subregion of the metal base 20 of mask material layer 21 covering, 21 protection of mask material layer are by the subregion of the metal base 20 of its covering.Mask material layer 21 requires with metal base 20 combinations firm, has thermal stability, as against corrosion, anti-coating, has etch-resistance and anti-plating.For the exposure imaging manufacture method, at first the upper surface 20a at metal base 20 is coated with photic wet film, coating process can be curtain coating, roller coating and spraying etc., perhaps the upper surface 20a at metal base 20 pastes photic dry film, and then it is exposed under certain light source, such as ultraviolet light, electron beam or X-ray, utilize the light sensitive characteristic of the chemical photosensitive materials such as photic wet film and photic dry film, photic wet film or photic dry film are optionally exposed, mask plate patterns is duplicated on photic wet film or the photic dry film, finally the upper surface 20a at metal base 20 forms mask material layer 21 after using developer solution to carry out developing process.
Please refer to Fig. 3 C, with mask material layer 21 with window as resist layer, select the only etching solution of etching metal base material 20, adopt the spray mode that metal base upper surface 20a is carried out etching, forming outer chip carrier 22a, outer pin 23a and groove 24, is 0.03mm-0.15mm through the outer chip carrier 22a of etching formation and the thickness range of outer pin 23a.In the present embodiment, the preferential upward spray mode that adopts of the spray mode of etching solution, and in etching solution, add a small amount of organic substance, reducing etching solution to the lateral erosion effect of metal base 20, because mask material layer 21 is to have the polymeric materials such as the wet film of light sensitive characteristic or dry film, acid resistance is alkali resistance not, as etched resist layer, etching solution is preferentially selected acidic etching liquid, such as acid copper chloride etching liquid, iron chloride etching solution, to reduce etching solution to the destruction of mask material layer 21.
Please refer to Fig. 3 D, mask material layer 21 on the upper surface 20a of metal base 20 is removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the alkaline solution of selecting solubility, potassium hydroxide (KOH) for example, NaOH (NaOH), adopt the mask material layer 21 on the upper surface 20a of the mode such as spray and metal base 20 to carry out chemical reaction, thereby its dissolving is reached the effect that removes, also can select organic striping liquid that mask material layer 21 is removed, after removing mask material layer 21, only there are outer chip carrier 22a and outer pin 23a on the metal base 20, outside between chip carrier 22a and the outer pin 23a, form groove 24 between outer pin 23a and the outer pin 23a.
Please refer to Fig. 3 E, adopt injection moulding or method for printing screen outside between chip carrier 22a and the outer pin 23a, dispose insulation filling material 25 in the groove 24 between outer pin 23a and the outer pin 23a.In the present embodiment, insulation filling material 25 is thermosetting capsulation materials, plug socket resin, the insulating material such as printing ink and welding resistance green oil, insulation filling material 25 has enough acidproof, alkali resistance, to guarantee that follow-up technique can not damage forming insulation filling material 25, solidify to form the insulation filling material 25 of suitable hardness after the filling, need to carry out ultraviolet exposure for photocuring insulation filling material 25, insulation filling material 25 after the sclerosis has some strength, has the effect of mutual locking with outer chip carrier 22a and outer pin 23a, remove too much insulation filling material 25 with mechanical grinding method or chemical treatment method, to eliminate the flash of insulation filling material 25, for insulation filling materials 25 such as photosensitive type welding resistance green oils, remove flash by developing method.
Please refer to Fig. 3 F; surface at insulation filling material 25 makes the mask material layer 26 with window by the exposure imaging method; window described here refers to that not by the subregion on table 20a and insulation filling material 25 surfaces on the metal base of mask material layer 26 covering, 26 protection of mask material layer are by the subregion of its covering.Mask material layer 26 requires with insulation filling material 25 combinations firm, has thermal stability, as against corrosion, anti-coating, has etch-resistance and anti-plating.For the exposure imaging manufacture method, at first at the photic wet film of the surface-coated of insulation filling material 25, coating process can be curtain coating, roller coating and spraying etc., perhaps paste photic dry film on the surface of insulation filling material 25, and then it is exposed under certain light source, such as ultraviolet light, electron beam or X-ray, utilize the light sensitive characteristic of the chemical photosensitive materials such as photic wet film and photic dry film, photic wet film or photic dry film are optionally exposed, mask plate patterns is duplicated on photic wet film or the photic dry film, finally the surface at insulation filling material 25 forms mask material layer 26 after using developer solution to carry out developing process.
Please refer to Fig. 3 G, adopt successively chemical plating and electro-plating method in the window of mask material layer 26, make in chip carrier 22b and interior pin 23b, formation has chip carrier 22 and a plurality of pin 23 of ledge structure 27, wherein chip carrier comprises interior chip carrier 22b and outer chip carrier 22a, and pin 23 comprises interior pin 23b and outer pin 23a.At first in the window of mask material layer 26, adopt chemical plating method to form one deck metal level as thin as a wafer, then adopt electro-plating method to form and have certain thickness interior chip carrier 22b and interior pin 23b.The material of interior chip carrier 22b and interior pin 23b is metal material and the alloys thereof such as copper (Cu), nickel (Ni), iron (Fe), aluminium (Al), and allow to be formed by different metal materials, preferential copper or the copper alloy selected be as the material of interior chip carrier 22b and interior pin 23b, and can be identical material with outer chip carrier 22a and outer pin 23a.Chemical plating and electro-plating method have the characteristics such as high accuracy, high-flatness, controllability be strong, can be used for making ultra-thin interior chip carrier 22b and interior pin 23b, the interior chip carrier 22b that forms through chemical plating and electro-plating method and the thickness range of interior pin 23b are 0.03mm-0.15mm.
Please refer to Fig. 3 H, adopt plating or chemical plating method to make the first metal material layer 28 on the surface of interior chip carrier 22b and interior pin 23b.The material of the first metal material layer 28 is metal material and the alloys thereof such as nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin (Sn).The thickness range of the first metal material layer 28 is 0.002mm-0.03mm.In the present embodiment, the first metal material layer 28 for example is nickel-palladium-gold plate, the gold plate of outside and middle palladium coating are to guarantee bond ability and the bonding quality of plain conductor 31 on interior chip carrier 22b and interior pin 23b in lead key closing process, the nickel coating of the inside is that blocked up cocrystalization compound affects the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents from being caused by Elements Diffusion-chemical reaction.
Please refer to Fig. 3 I, mask material layer 26 is removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the alkaline solution of selecting solubility, for example potassium hydroxide (KOH), NaOH (NaOH), adopt the mode such as spray and mask material layer 26 to carry out chemical reaction, thereby its dissolving is reached the effect that removes, also can select organic striping liquid that mask material layer 26 is removed.
Please refer to Fig. 3 J, IC chip 30 is disposed at the first metal material layer 28 positions of interior chip carrier 22b by adhesive material 29.In the present embodiment, adhesive material 29 can be the materials such as epoxy resin of bonding die adhesive tape, argentiferous particle, behind the configuration IC chip 30, needs that adhesive material 29 is carried out high-temperature baking and solidifies, with the bond strength of enhancing with IC chip 30, the first metal material layer 28.
Please refer to Fig. 3 K, a plurality of bonding welding pads on the IC chip 30 are connected to the first metal material layer 28 of interior chip carrier 22b and interior pin 23b configuration by plain conductor 31, realize electrical interconnection and ground connection.In the present embodiment, plain conductor 31 is gold thread, aluminum steel, copper cash and plating palladium copper cash etc.
Please refer to Fig. 3 L, adopt injection moulding process, by high-temperature heating, with environment-friendly type plastic closure material 32 coating sealing IC chips 30, adhesive material 29, plain conductor 31, interior chip carrier 22b, interior pin 23b and first metal material layer 28 of low water absorption, low stress.In the present embodiment, capsulation material 32 can be the materials such as thermosetting polymer, the insulation filling material 25 of filling has the physical property similar to capsulation material 32, thermal coefficient of expansion for example, to reduce the product failure that is caused by thermal mismatching, improve the reliability of product, insulation filling material 25 can be commaterial with capsulation material 32.Toast rear curing behind the plastic packaging, capsulation material 32 and insulation filling material 25 have mutual lock function with chip carrier 22 and pin 23 with ledge structure 27, can effectively prevent chip carrier 22 and pin 23 and capsulation material 32 and the layering of insulation filling material 25 and coming off of pin 23 or chip carrier 22, and effectively stop moisture to be diffused into package interior along the combination interface of chip carrier 22 and pin 23 and capsulation material 32 and insulation filling material 25, improved the reliability of packaging body.After rear curing, product array is carried out laser printing.
Please refer to Fig. 3 M, adopt mechanical grinding method or engraving method that metal base 20 is carried out attenuate from lower surface 20b, until expose insulation filling material 25, form independently chip carrier 22 and pin 23.In the mechanical grinding method, successively to the lower surface 20b of metal base 20 roughly grind, fine grinding and correct grinding, in the process of grinding, can suitably add chemical medicinal liquid, in conjunction with the quality of method for chemially etching with the elevating mechanism grinding.In engraving method, select the only etching solution of etching metal base material 20, adopt the spray mode that metal base 20 lower surface 20b are carried out whole etching.
Please refer to Fig. 3 N, adopt chemical plating method to make the second metal material layer 33 in the surface of chip carrier 22a and outer pin 23a outside.The material of the second metal material layer 33 is metal material and the alloys thereof such as nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin (Sn).The thickness range of the second metal material layer 33 is 0.002mm-0.03mm.In the present embodiment, the second metal material layer 33 for example is nickel-palladium-gold plate, but the gold plate of outside and middle palladium coating are to guarantee the outside wettability of chip carrier 22a and outer pin 23a of scolder, improve the quality that packaging body mounts at circuit board upper surfaces such as PCB, the nickel coating of the inside is that blocked up cocrystalization compound affects the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents from being caused by Elements Diffusion-chemical reaction.
Please refer to Fig. 3 O, cutting has the product array of the high density QFN packaging 200 of multi-circle pin arrangement, thoroughly cutting and separating insulation filling material 25 and capsulation material 32 form the single high density QFN packaging 200 that multi-circle pin is arranged that has, in the present embodiment, the single product separation method is the methods such as blade cuts, laser cutting or the cutting of water cutter, and only cut insulation filling material 25 and capsulation material 31, cutting metal material not, 2 that only draw out among Fig. 3 O after the cutting and separating have the high density QFN packagings 200 that multi-circle pin is arranged.
The schematic rear view with high density QFN packaging 300 of being face battle array pin arrangements of Fig. 4 for drawing according to embodiments of the invention 2, its middle-high density QFN packaging 300 has the pin 23 that the face battle array is arranged, surface configuration at pin 23 has the second metal material layer 33, in high density QFN packaging 300, dispose insulation filling material 25, the arrangement mode of pin 23 is not limit, can be for being arranged in parallel, also can be for being staggered, the shape of cross section of pin 23 can be circle or rectangle, and is identical with arrangement mode and the shape of cross section of multi-circle pin 23 among the embodiment 1.In the present embodiment, the arrangement mode of the face battle array pin 23 of high density QFN packaging 300 is for being arranged in parallel, and the shape of cross section of pin 23 is circular.
Fig. 5 A is along the I-among Fig. 4
IThe first generalized section of section.In conjunction with Fig. 4, with reference to Fig. 5 A, in the present embodiment, the high density QFN packaging 300 that is face battle array pin arrangements comprises pin 23, the first metal material layer 28, the second metal material layer 33, insulation filling material 25, ledge structure 27, adhesive material 29, IC chip 30, plain conductor 31 and capsulation material 32, wherein pin 23 comprises outer pin 23a and interior pin 23b.Be and have the in full accord of high density QFN packaging 200 that multi-circle pin arranges among the manufacture method of high density QFN packaging 300 of face battle array pin arrangements and flow process and the embodiment 1.
Fig. 5 B is along the I-among Fig. 4
ISection the second generalized section.In conjunction with Fig. 4, with reference to Fig. 5 B, in the present embodiment, the high density QFN packaging 300 that is face battle array pin arrangements comprises interior chip carrier 22b, pin 23, insulation filling material 25, the first metal material layer 28, the second metal material layer 33, ledge structure 27, adhesive material 29, IC chip 30, plain conductor 31 and capsulation material 32, wherein pin 23 comprises outer pin 23a and interior pin 23b.Be and have the in full accord of high density QFN packaging 200 that multi-circle pin arranges among the manufacture method of high density QFN packaging 300 of face battle array pin arrangements and flow process and the embodiment 1.
Description to embodiments of the invention is for effectively illustrating and describe purpose of the present invention, be not to limit the present invention, those skilled in the art is to be understood that under any: under the condition that does not break away from inventive concept of the present invention and scope, can change above-described embodiment.So the present invention is not limited to disclosed specific embodiment, but cover the interior modification of the defined the spirit and scope of the invention of claim.
Claims (5)
1. the manufacture method of a high density QFN packaging may further comprise the steps:
(a) adopt the exposure imaging method, form the mask material layer with window at the metal base upper surface;
(b) with mask material layer with window as resist layer, the metal base upper surface is carried out etching, form outer chip carrier, outer pin and groove;
(c) remove the mask material layer that is disposed at the metal base upper surface;
(d) adopt injection moulding or method for printing screen outside between chip carrier and the outer pin, dispose insulation filling material in the groove between outer pin and the outer pin;
(e) adopt the exposure imaging method, make the mask material layer with window at the surface location of insulation filling material;
(f) adopt successively chemical plating and electro-plating method in the window of mask material layer, make in chip carrier and interior pin, formation has chip carrier and the pin of ledge structure, wherein chip carrier comprises interior chip carrier and outer chip carrier, and pin comprises interior pin and outer pin;
(g) adopt plating or chemical plating method at surface configuration first metal material layer of interior chip carrier and interior pin;
(h) remove the mask material layer that is disposed at the insulation filling material surface;
(i) by adhesive material with the IC chip configuration on the first metal material layer of interior chip carrier or interior pin configuration;
(j) a plurality of bonding welding pads on the IC chip are connected to respectively the first metal material layer of interior chip carrier and interior pin configuration by plain conductor;
(k) adopt injection moulding process to coat sealing IC chip, adhesive material, plain conductor, interior chip carrier, interior pin and the first metal material layer with capsulation material, toast rear curing behind the plastic packaging;
(l) adopt mechanical grinding method or engraving method that metal base is carried out attenuate, form independently chip carrier and pin;
(m) adopt chemical plating method to make the second metal material layer in the surface of chip carrier and outer pin outside;
(n) separation forms independently single package.
2. the manufacture method of high density QFN packaging according to claim 1 is characterized in that, is 0.03mm-0.15mm through the outer chip carrier of engraving method formation and the thickness range of outer pin.
3. the manufacture method of high density QFN packaging according to claim 1 is characterized in that, adopting successively the interior chip carrier of chemical plating and electro-plating method making and the thickness range of interior pin is 0.03mm-0.15mm.
4. the manufacture method of high density QFN packaging according to claim 1 is characterized in that, adopts insulation filling material and capsulation material to carry out secondary and coats sealing.
5. the manufacture method of high density QFN packaging according to claim 1 is characterized in that, adopts blade cuts, laser cutting or water cutter cutting method cutting and separating to form single package, and only cuts capsulation material and insulation filling material.
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