CN202996820U - Rewiring QFN package device - Google Patents
Rewiring QFN package device Download PDFInfo
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- CN202996820U CN202996820U CN 201220700196 CN201220700196U CN202996820U CN 202996820 U CN202996820 U CN 202996820U CN 201220700196 CN201220700196 CN 201220700196 CN 201220700196 U CN201220700196 U CN 201220700196U CN 202996820 U CN202996820 U CN 202996820U
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- pin
- chip carrier
- chip
- material layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a rewiring QFN package device. The device is characterized in that a chip carrier is configured in the central position of the package device; a plurality of pins are arranged around the chip carrier into multiple circles; insulation filling material is configured between the chip carrier and the pins as well as between the pins; an IC chip is configured on the chip carrier through pasting material; a first metal material layer is arranged around the IC chip; the pins are connected with the first metal material layer through a rewiring layer; the IC chip is connected to the first metal material layer by metal wires; a second metal material layer is configured on the lower surface of the chip carrier and the pins; and plastic package material coats and seals the IC chip, the pasting material, the metal wires, the first metal material layer, the rewiring layer and the chip carrier and only exposes the second metal material layer configured on the lower surface of the chip carrier and the pins. The rewiring QFN package device has the advantages of high I/O density, low manufacturing cost and good reliability.
Description
Technical field
The utility model relates to QFN components and parts manufacturing technology field, refers more particularly to four limit flat leadless package part and manufacture methods thereof with high I/O density.
Background technology
Along with electronic product such as mobile phone, notebook computer etc. towards miniaturization, portable, ultrathin, multimedization and satisfy popular needed low-cost future development, high density, high-performance, high reliability and packing forms and packaging technology thereof have obtained development fast cheaply.Compare with packing forms such as expensive BGA, fast-developing novel encapsulated technology in recent years, i.e. four limit flat non-pin QFN(Quad Flat Non-lead Package) encapsulation, due to have good hot property and electrical property, size is little, cost is low and the many merits such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Due to the raising of IC integrated level and the continuous enhancing of function, the I/O number of IC increases thereupon, the also corresponding increase of I/O number of pins of corresponding packaging, but the pin of traditional QFN packaging part device is individual pen around the chip carrier periphery to be arranged, limited the raising of I/O quantity, can not meet high density, have the needs of the IC of more I/O numbers, therefore the QFN packaging that multi-circle pin is arranged has appearred being, wherein pin is the multi-turn arrangement around chip carrier, has significantly improved the I/O number of pins of packaging.
Figure 1A and Figure 1B are respectively schematic rear view with QFN packaging that multi-circle pin arranges and along the generalized section of I-í section.The QFN encapsulating structure that this multi-circle pin is arranged comprises chip carrier 11, is the pin 12 that three circles are arranged, capsulation material 13, adhesive material 14, IC chip 15, plain conductor 16 around chip carrier 11.IC chip 15 is fixed on chip carrier 12 by adhesive material 14; IC chip 15 is realized electrical connection with the pin 12 that surrounding is arranged by plain conductor 16; 13 pairs of IC chips 15 of capsulation material, plain conductor 16, chip carrier 11 and pin 12 seal to reach the effect of protection and support; pin 12 is exposed in the bottom surface of capsulation material 13, is welded on by scolder on the circuit board such as PCB to realize and extraneous electrical connection.The exposed chip carrier 11 in bottom surface is welded on by scolder on the circuit board such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 15 produces.
Compare with the QFN packaging of traditional individual pen pin arrangements, the QFN packaging that multi-circle pin is arranged has higher pin number, has satisfied the more and more higher requirement of IC integrated level.Yet, in order to improve the I/O quantity of QFN packaging, need more zone to place a plurality of pins, therefore need to increase the size of QFN packaging, the requirement of this and packaging miniaturization is runed counter to, and along with package dimension increases, distance between chip and pin can increase, cause plain conductor, use amount as gold (Au) line increases, increased manufacturing cost, long plain conductor very easily causes the problems such as subsiding, breasting the tape of plain conductor and intersection in the Shooting Technique process, affected the yield of packaging and the lifting of reliability.Therefore, arrange oversize bottleneck, the above-mentioned yield of solution and integrity problem and the reduction manufacturing cost of QFN packaging in order to break through existing multi-circle pin, be badly in need of QFN packaging and the manufacture method thereof of a kind of small size of research and development, high reliability, low cost, high I/O density.
The utility model content
The utility model provides a kind of QFN packaging and manufacture method thereof of connecting up again, with the bottleneck that reaches the low I/O quantity that breaks through traditional Q FN encapsulation, high packaging cost and the purpose that improves the reliability of packaging body.
To achieve these goals, the utility model adopts following technical proposals:
The utility model proposes a kind of QFN packaging that connects up again, it is characterized in that, comprising:
Chip carrier is disposed at the central part of packaging;
A plurality of pin configuration are multi-turn around chip carrier and arrange in the chip carrier surrounding;
Insulation filling material is disposed between chip carrier and pin, and between pin and pin;
The IC chip is disposed on chip carrier by adhesive material;
The first metal material layer is around the IC arrangements of chips;
Pin is realized and being connected of the first metal material layer by wiring layer again;
The IC chip is connected to the first metal material layer by plain conductor;
The second metal material layer is disposed at the lower surface of chip carrier and pin;
Capsulation material coats the above-mentioned IC chip of sealing, adhesive material, plain conductor, the first metal material layer, wiring layer and chip carrier again, only exposes the second metal material layer that is disposed at chip carrier and pin lower surface.
According to embodiment of the present utility model, before metal base was carried out attenuate, the chip carrier of formation was connected with metal base with pin.
According to embodiment of the present utility model, adopt mechanical grinding method or engraving method to carry out attenuate to metal base, realize independently chip carrier and pin.
According to embodiment of the present utility model, adopt insulation filling material and capsulation material to carry out secondary and coat sealing formation packaging.
According to embodiment of the present utility model, to make a plurality of pins that form and pass through again the bonding position that wiring layer changes plain conductor, realization is interconnected with the IC chip.
based on above-mentioned, according to the utility model, the chip load of the QFN packaging that connects up again that manufacturing forms and pin need not the lead frame structure based on prior making moulding, namely need not to rely on traditional lead frame provide mechanical support be connected with connection but in potting process, at first adopt that to have the precision of making high, the engraving method of the controlled characteristics such as strong is made pin and chip carrier, then configure insulation filling material in groove, then adopt successively that to have the precision of making high, evenness is good, chemical plating and the electro-plating method of the controlled characteristics such as strong are made wiring layer again, at last after plastic package process is completed, it is low that employing has a cost, the mechanical grinding method of the characteristics such as evenness is good, adopt perhaps that to have the precision of making high, the thickness of the whole attenuate metal base of engraving method of the controlled characteristics such as strong, form independently chip carrier and pin.The wiring layer again that the utility model adopts can make the size of packaging significantly reduce, shortened the distance between IC chip and pin, reduced plain conductor, use amount as gold (Au) line, reduced manufacturing cost, solve subsiding, breast the tape and the problem such as intersection of plain conductor in the Shooting Technique process, promoted yield and the reliability of packaging.The utility model adopts the secondary encapsulating method, namely adopt insulation filling material and capsulation material to carry out secondary and coat sealing, wherein insulation filling material is disposed under wiring layer again, the above zone of wiring layer adopts capsulation material to coat sealing again, what this filling, clad structure feature can realize encapsulating seals without the cavity, eliminates because of defectives such as the bubble of sealing incomplete generation, cavities.The generation of bridging phenomenon when the pin of the small size size that the utility model manufacturing forms can effectively prevent surface mount, the lower surface of chip carrier, pin and the metal material layer that configures on wiring layer again can effectively improve metal lead wire bonding quality and surface mount quality respectively, and the arrangement mode of pin is not limit, can be for being arranged in parallel, also can be for being staggered, all pins need not to extend to packaging body one side.
Embodiment cited below particularly, and coordinate accompanying drawing that above-mentioned feature and advantage of the present utility model are elaborated.
Description of drawings
Figure 1A is the schematic rear view of the QFN packaging of multi-circle pin arrangement;
Figure 1B is the generalized section along the I-í section in Figure 1A;
Fig. 2 A is the schematic rear view according to the QFN packaging that connects up again of embodiment drafting of the present utility model;
Fig. 2 B is the front schematic view according to the QFN packaging that connects up again of embodiment drafting of the present utility model;
Fig. 2 C is along the I-in Fig. 2 B
IThe generalized section of section;
Fig. 3 A to Fig. 3 M is that all generalized sections are all along the generalized section shown in Fig. 2 C section according to the manufacturing process generalized section of the QFN packaging that connects up again of embodiment drafting of the present utility model.
number in the figure: the QFN packaging that 100. multi-circle pins are arranged, 11. chip carrier, 12. pin, 13. capsulation material, 14. adhesive material, 15.IC chip, 16. plain conductor, the QFN packaging 200. connect up again, 20. metal base, 20a. metal base upper surface, 20b. metal base lower surface, 21. mask material layer, 22. chip carrier, 23. pin, 24. groove, 25. insulation filling material, 26. wiring layer again, 27. the first metal material layer, 28. adhesive material, 29.IC chip, 30. plain conductor, 31. capsulation material, 32. the second metal material layer.
Embodiment
Preparation method of the present utility model comprises the following steps:
(a) adopt the exposure imaging method, form the mask material layer with window at the metal base upper surface;
(b) with mask material layer with window as resist layer, the metal base upper surface is carried out etching, form chip carrier, pin and groove;
(c) remove the mask material layer that is disposed at the metal base upper surface;
(d) adopt in injection moulding or the method for printing screen groove between chip carrier and pin, between pin and pin and configure insulation filling material;
(e) adopt the exposure imaging method, make the mask material layer with window at the surface location of insulation filling material and pin;
(f) adopt successively chemical plating and electro-plating method to make wiring layer again in the window of mask material layer;
(g) remove the mask material layer on the surface that is disposed at insulation filling material;
(h) adopt to electroplate or chemical plating method at surface portion configuration first metal material layer of wiring layer again;
(i) by adhesive material with the IC chip configuration on chip carrier;
(j) the IC chip is connected to the first metal material layer by plain conductor;
(k) adopt injection moulding process to coat sealing IC chip, adhesive material, plain conductor, wiring layer, the first metal material layer and chip carrier again with capsulation material, toast rear curing after plastic packaging;
(l) adopt mechanical grinding method or engraving method to carry out attenuate to metal base, form independently chip carrier and pin;
(m) adopt chemical plating method to make the second metal material layer at the lower surface of chip carrier and pin;
(n) separation forms independently single package.
Further, be 0.03mm-0.15mm through the chip carrier of etching formation and the thickness range of pin.
Further, adopting successively the thickness range of the wiring layer again of chemical plating and electro-plating method making is 0.02mm-0.15mm.
Further, adopt blade cuts, laser cutting or water cutter cutting method cutting and separating to form single package, and only cut capsulation material and insulation filling material.Below in conjunction with accompanying drawing, the utility model is elaborated:
Fig. 2 A is rectangle for the pin cross section of drawing according to embodiment of the present utility model, and the pin arrangements mode on chip carrier every limit is the schematic rear view of the QFN packaging that connects up again that is arranged in parallel.
Can find out with reference to above-mentioned Fig. 2 A, in the present embodiment, the QFN packaging 200 that connects up again has chip carrier 22 and is around chip carrier 22 pin 23 that two circles are arranged, the arrangement mode of the pin 23 on chip carrier 22 every limits is for being arranged in parallel, the cross section of pin 23 is rectangle, lower surface at chip carrier 22 and pin 23 disposes the second metal material layer 32, disposes insulation filling material 25 in the QFN packaging 200 that connects up again.In the present embodiment, the arrangement number of turns of pin 23 is not limit, can for Liang Quan, three the circle and three the circle more than, the arrangement mode of pin 23 is not defined as and is arranged in parallel, and can be other arrangement modes, the shape of cross section of pin 23 is not defined as rectangle, can be circle.
Fig. 2 B is rectangle for the pin cross section of drawing according to embodiment of the present utility model, and the pin arrangements mode on chip carrier every limit is the front schematic view of the QFN packaging that connects up again that is arranged in parallel.
Can find out with reference to above-mentioned Fig. 2 B, in order clearly to show the internal structure of the QFN packaging 200 that connects up again, the spy saves capsulation material 31.In the present embodiment, insulation filling material 25 is disposed between chip carrier 22 and pin 23, between pin 23 and pin 23, and be disposed at again the below of wiring layer 26, IC chip 29 is disposed on chip carrier 22, IC chip 29 is connected to respectively the first metal material layer 27 of wiring layer 26 configurations again by plain conductor 30, pin 22 extends to package interior by wiring layer 26 again, realizes interconnected with IC chip 29.
Fig. 2 C is along the I-in Fig. 2 B
IThe generalized section of section.In conjunction with Fig. 2 A and 2B, with reference to Fig. 2 C, in the present embodiment, then the QFN packaging 200 that connects up comprise chip carrier 22, be the pin 23, insulation filling material 25 of two circle pin arrangements, wiring layer 26, the first metal material layer 27, adhesive material 28, IC chip 29, plain conductor 30, capsulation material 31 and the second metal material layer 32 again around chip carrier 22.
The below will describe with Fig. 3 A to Fig. 3 M the manufacturing process of the QFN packaging that connects up again in detail.
The have two manufacturing process generalized sections of enclosing again the connect up QFN packaging of pin arrangements of Fig. 3 A to Fig. 3 M for drawing according to embodiment of the present utility model, all generalized sections are all along the generalized section shown in Fig. 2 C section.
Please refer to Fig. 3 A, provide and have upper surface 20a and with respect to the metal base 20 of the lower surface 20b of upper surface 20a, the material of metal base 20 can be that copper, copper alloy, iron, ferroalloy, nickel, nickel alloy and other are applicable to make the metal material of chip carrier and pin, preferentially selects copper or Cu alloy material.The thickness range of metal base 20 is 0.1mm-0.3mm.Upper surface 20a and lower surface 20b to metal base 20 clean and preliminary treatment, such as with plasma water degreasing, dust etc., with the upper surface 20a that realizes metal base 20 and the purpose of lower surface 20b cleaning.
Please refer to Fig. 3 B; make the mask material layer 21 with window by the exposure imaging method on the upper surface 20a of metal base 20; window described here refers to that not by the subregion of the metal base 20 of mask material layer 21 covering, 21 protection of mask material layer are by the subregion of the metal base 20 of its covering.Mask material layer 21 requires with metal base 20 combinations firm, has thermal stability, as against corrosion, anti-coating, has etch-resistance and anti-plating.for the exposure imaging manufacture method, at first at the photic wet film of the upper surface 20a of metal base 20 coating, coating process can be curtain coating, roller coating and spraying etc., perhaps the upper surface 20a at metal base 20 pastes photic dry film, and then it is exposed under certain light source, as ultraviolet light, electron beam or X-ray, utilize the light sensitive characteristic of the chemical photosensitive materials such as photic wet film and photic dry film, photic wet film or photic dry film are optionally exposed, mask plate patterns is duplicated on photic wet film or photic dry film, form mask material layer 21 on final upper surface 20a at metal base 20 after using developer solution to carry out developing process.
Please refer to Fig. 3 C, with mask material layer 21 with window as resist layer, select the only etching solution of etching metal base material 20, adopt the spray mode to carry out etching to metal base upper surface 20a, forming chip carrier 22, pin 23 and groove 24, is 0.03mm-0.15mm through the chip carrier 22 of etching formation and the thickness range of pin 23.In the present embodiment, the preferential upward spray mode that adopts of the spray mode of etching solution, and add a small amount of organic substance in etching solution, reducing etching solution to the lateral erosion effect of metal base 20, because mask material layer 21 is to have the polymeric materials such as the wet film of light sensitive characteristic or dry film, acid resistance is alkali resistance not, as etched resist layer, etching solution is preferentially selected acidic etching liquid, as acid copper chloride etching liquid, iron chloride etching solution, to reduce etching solution to the destruction of mask material layer 21.
please refer to Fig. 3 D, mask material layer 21 on the upper surface 20a of metal base 20 is removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the alkaline solution of selecting solubility, potassium hydroxide (KOH) for example, NaOH (NaOH), adopt the mask material layer 21 on the upper surface 20a of the mode such as spray and metal base 20 to carry out chemical reaction, thereby its dissolving is reached the effect that removes, also can select organic striping liquid that mask material layer 21 is removed, after removing mask material layer 21, only there are chip carrier 22 and pin 23 on metal base 20, between chip carrier 22 and pin 23, form groove 24 between pin 23 and pin 23, the chip carrier 22 that forms is connected with metal base 20 with pin 23.
Please refer to Fig. 3 E, adopt in injection moulding or the method for printing screen groove 24 between chip carrier 22 and pin 23, between pin 23 and pin 23 and configure insulation filling material 25.in the present embodiment, insulation filling material 25 is thermosetting capsulation materials, plug socket resin, the insulating material such as printing ink and welding resistance green oil, insulation filling material 25 has enough acidproof, alkali resistance, to guarantee that follow-up technique can not damage forming insulation filling material 25, solidify to form the insulation filling material 25 of suitable hardness after filling, need to carry out ultraviolet exposure for photocuring insulation filling material 25, insulation filling material 25 after sclerosis has some strength, has the effect of mutual locking with chip carrier 22 and pin 23, remove too much insulation filling material 25 with mechanical grinding method or chemical treatment method, to eliminate the flash of insulation filling material 25, for insulation filling materials 25 such as photosensitive type welding resistance green oils, remove flash by developing method.
Please refer to Fig. 3 F, adopt successively chemical plating and electro-plating method to make again wiring layer 26 at the surface location of insulation filling material 25 and pin 23.At first, surface location at insulation filling material 25 and pin 23 is made the mask material layer with window by the exposure imaging method, window described here refers to the subregion that do not covered by the mask material layer in follow-up technique, will make wiring layer 26 in this window again.then, adopt successively chemical plating method and electro-plating method to form in the window of mask material layer and have certain thickness wiring layer again 26, the material of wiring layer 26 is copper (Cu) again, nickel (Ni), iron (Fe), metal material and the alloys thereof such as aluminium (Al), and allow to be formed by different metal materials, preferential copper or the copper alloy conduct material of wiring layer 26 again of selecting, and can be identical material with chip carrier 22 and pin 23, chemical plating and electro-plating method have high accuracy, high-flatness, the characteristics such as controllability is strong, can be used for making ultra-thin wiring layer again 26, the thickness range of the wiring layer again 26 that forms through chemical plating and electro-plating method is 0.02mm-0.15mm.At last, the mask material layer is removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the alkaline solution of selecting solubility, for example potassium hydroxide (KOH), NaOH (NaOH), adopt the mode such as spray and mask material layer to carry out chemical reaction, thereby its dissolving is reached the effect that removes, also can select organic striping liquid that the mask material layer is removed.Make the wiring layer again 26 that forms and pin 23 is extended to the inside of packaging 200, the size of packaging 200 is significantly reduced, shortened the bonding distance of plain conductor 30, reduced the use amount of plain conductor 30, reduced manufacturing cost, solve subsiding, breast the tape and the problem such as intersection of plain conductor 30 in the Shooting Technique process, promoted yield and the reliability of packaging.
Please refer to Fig. 3 G, adopt to electroplate or chemical plating method is made the first metal material layer 27 on the surface of wiring layer 26 again.The material of the first metal material layer 27 is metal material and the alloys thereof such as nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin (Sn).The thickness range of the first metal material layer 27 is 0.002mm-0.03mm.In the present embodiment, the first metal material layer 27 is for example nickel-palladium-gold plate, the gold plate of outside and middle palladium coating are bond ability and the bonding qualities that guarantees plain conductor 30 in lead key closing process, the nickel coating of the inside is that blocked up cocrystalization compound affects the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents from being caused by Elements Diffusion-chemical reaction.
Please refer to Fig. 3 H, by adhesive material 28, IC chip 29 is disposed on chip carrier 22.In the present embodiment, adhesive material 28 can be the materials such as epoxy resin of bonding die adhesive tape, argentiferous particle, after configuration IC chip 29, needs that adhesive material 28 is carried out high-temperature baking and solidifies, with the bond strength of enhancing with IC chip 29, chip carrier 22.
Please refer to Fig. 3 I, a plurality of bonding welding pads on IC chip 29 are connected to the first metal material layer 27 of wiring layer 26 configurations again by plain conductor 30, realize electrical interconnection.In the present embodiment, plain conductor 30 is gold thread, aluminum steel, copper cash and plating palladium copper cash etc.
Please refer to Fig. 3 J, adopt injection moulding process, by high-temperature heating, coat sealing IC chips 29, adhesive material 28, wiring layer 26, plain conductor 30, the first metal material layer 27 and chip carrier 22 again with the environment-friendly type plastic closure material 31 of low water absorption, low stress.In the present embodiment, capsulation material 31 can be the materials such as thermosetting polymer, the insulation filling material 25 of filling has the physical property similar to capsulation material 31, thermal coefficient of expansion for example, to reduce the product failure that is caused by thermal mismatching, improve the reliability of product, insulation filling material 25 can be commaterial with capsulation material 31.Toast rear curing after plastic packaging, after rear curing, the packaging product array is carried out laser printing.
Please refer to Fig. 3 K, adopt mechanical grinding method or engraving method to carry out attenuate to metal base 20 from lower surface 20b, until expose insulation filling material 25, form independently chip carrier 22 and pin 23.In the mechanical grinding method, successively to the lower surface 20b of metal base 20 roughly grind, fine grinding and correct grinding, in the process of grinding, can suitably add chemical medicinal liquid, in conjunction with the quality of method for chemially etching with the elevating mechanism grinding.In engraving method, select the only etching solution of etching metal base material 20, adopt the spray mode to carry out whole etching to metal base 20 lower surface 20b.
Please refer to Fig. 3 L, adopt chemical plating method to make the second metal material layer 32 on the surface of chip carrier 22 and pin 23.The material of the second metal material layer 32 is metal material and the alloys thereof such as nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin (Sn).The thickness range of the second metal material layer 32 is 0.002mm-0.03mm.In the present embodiment, the second metal material layer 32 is for example nickel-palladium-gold plate, the gold plate of outside and middle palladium coating are to guarantee that but scolder is in the wettability of chip carrier 22 and pin 23, improve the quality that packaging body mounts at circuit board upper surfaces such as PCB, the nickel coating of the inside is that blocked up cocrystalization compound affects the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents from being caused by Elements Diffusion-chemical reaction.
Please refer to Fig. 3 M, cut the product array of the QFN packaging 200 that connects up again, thoroughly cutting and separating insulation filling material 25 and capsulation material 31 form the single QFN packaging 200 that connects up again, in the present embodiment, the single product separation method is the methods such as blade cuts, laser cutting or the cutting of water cutter, and only cut insulation filling material 25 and capsulation material 31, cutting metal material is not only drawn out 2 QFN packagings 200 that connect up again after cutting and separating in Fig. 3 M.
Description to embodiment of the present utility model is for effectively illustrating and describe the purpose of this utility model, be not to limit the utility model, under any, those skilled in the art is to be understood that: under the condition that does not break away from utility model design of the present utility model and scope, can change above-described embodiment.Therefore the utility model is not limited to disclosed specific embodiment, but cover the defined essence of the present utility model of claim and the interior modification of scope.
Claims (1)
1. the QFN packaging that connects up again, is characterized in that, comprising:
Chip carrier is disposed at the central part of packaging;
A plurality of pin configuration are multi-turn around chip carrier and arrange in the chip carrier surrounding;
Insulation filling material is disposed between chip carrier and pin, and between pin and pin;
The IC chip is disposed on chip carrier by adhesive material;
The first metal material layer is around the IC arrangements of chips;
Pin is realized and being connected of the first metal material layer by wiring layer again;
The IC chip is connected to the first metal material layer by plain conductor;
The second metal material layer is disposed at the lower surface of chip carrier and pin;
Capsulation material coats the above-mentioned IC chip of sealing, adhesive material, plain conductor, the first metal material layer, wiring layer and chip carrier again, only exposes the second metal material layer that is disposed at chip carrier and pin lower surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220700196 CN202996820U (en) | 2012-12-17 | 2012-12-17 | Rewiring QFN package device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220700196 CN202996820U (en) | 2012-12-17 | 2012-12-17 | Rewiring QFN package device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202996820U true CN202996820U (en) | 2013-06-12 |
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ID=48567960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220700196 Expired - Fee Related CN202996820U (en) | 2012-12-17 | 2012-12-17 | Rewiring QFN package device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202996820U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109585442A (en) * | 2018-11-28 | 2019-04-05 | 武汉瑞纳捷电子技术有限公司 | A kind of high-power chip domain and its layout and packaging and routing optimization method |
-
2012
- 2012-12-17 CN CN 201220700196 patent/CN202996820U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109585442A (en) * | 2018-11-28 | 2019-04-05 | 武汉瑞纳捷电子技术有限公司 | A kind of high-power chip domain and its layout and packaging and routing optimization method |
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