CN109585442A - A kind of high-power chip domain and its layout and packaging and routing optimization method - Google Patents
A kind of high-power chip domain and its layout and packaging and routing optimization method Download PDFInfo
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- CN109585442A CN109585442A CN201811432087.4A CN201811432087A CN109585442A CN 109585442 A CN109585442 A CN 109585442A CN 201811432087 A CN201811432087 A CN 201811432087A CN 109585442 A CN109585442 A CN 109585442A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000005457 optimization Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 abstract description 18
- 229910052751 metal Inorganic materials 0.000 abstract description 18
- 238000010586 diagram Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention relates to IC Layouts and chip package field, more particularly to a kind of high-power chip domain and its layout and packaging and routing optimization method, the main branch for being subjected to high current is deleted in chip layout, leave each current branch, several opennings are added in chip layout and are connected respectively to each current branch, and the openning whole routing that current branch each in chip layout is connected is connected on the same packaging pin.The high-power chip domain and its layout and packaging and routing optimization method, will need the metal layer for transmitting high current to remove, replace with multiple opennings, then be interconnected by more package leads inside chip layout, and then reduce chip area, save the cost.
Description
Technical field
The present invention relates to IC Layouts and chip package field, in particular to a kind of high-power chip
Domain and its layout and packaging and routing optimization method.
Background technique
With the development of science and technology, electronic product while guaranteeing performance, just constantly pursues small in size, light weight spy
Point, the hardware circuit of plate grade are gradually substituted by several even single chips.And IC industry is also being grown rapidly, work
Skill size is gradually reduced, and chip cost is limited to the size of chip, and the metal layer that high current is transmitted in high-power chip is walked
Line passage occupied area tends not to small.
Existing high-power chip, domain is on processing high current cabling, and general there are two types of methods: first, by top layer
Metal layer and multilayer bottom metal layer stack, and to transmit high current, and then reduce the gold of transmitting high current inside domain
Belong to area shared by layer cable tray；Second, the metal layer cable tray of transmitting high current is not reserved individually, directly by excessive electricity
The metal layer of stream is layered on above device, and the openning of chip is also disposed in thereon.
But all there is its drawback for above two method.First method can not be effective reduction it is excessive
Area shared by metal routing channel when electric current, because for high current, the current carrying capability right and wrong of underlying metal
Often poor, in general, 1um underlying metal can at most bear 1mA electric current, if total current value is more than 1A, chip the inside
It is necessarily required to very wide metal to exist, to guarantee current capacity.Openning is directly placed above device by second method,
Other two problem can be brought in this way: firstly, this needs has specific customization, meeting on the manufacturing process of bare die and packaging technology
Greatly increase cost；In addition, stress when openning routing may be damaged device below, in order to adapt to such case,
The technique of its specific customization necessarily also may require that the relevant design size increased under openning, will necessarily make the face of this part domain
Product increases.
Summary of the invention
The embodiment of the invention provides a kind of high-power chip domain and its layout and packaging and routing optimization methods, at least solve
The excessive technical problem of the metal layer cable tray occupied area of certainly existing high-power chip domain transmitting high current.
According to an embodiment of the invention, the layout and packaging and routing optimization method of a kind of high-power chip domain are provided,
The following steps are included:
The main branch for being subjected to high current is deleted in chip layout, leaves each current branch；
Several opennings are added in chip layout is connected respectively to each current branch；
The openning whole routing that current branch each in chip layout is connected is connected on the same packaging pin.
Further, the sum of electric current that each current branch can bear is not less than the maximum electricity that chip layout can bear
Stream.
Further, the openning whole routing that current branch each in chip layout is connected is connected to chip layout
On first packaging pin.
Further, the packaging pin quantity of chip layout is 2N, 2N packaging pin along chip layout clockwise according to
Secondary arrangement, N are the integer more than or equal to 1.
According to another embodiment of the present invention, a kind of high-power chip domain, including chip layout ontology, chip are provided
Several branches and several opennings are provided on domain, several opennings are connected respectively in several current branch, several electric currents
The openning whole routing that branch is connected is connected on the same packaging pin.
Further, the sum of electric current that several current branch can bear is not less than the maximum electricity that chip layout can bear
Stream.
Further, the openning whole routing that several current branch are connected is connected to first of chip layout ontology
On packaging pin.
Further, the packaging pin quantity of chip layout ontology is 2N, and 2N packaging pin is along chip layout ontology
It is sequentially arranged clockwise, N is the integer more than or equal to 1.
High-power chip domain and its layout and packaging and routing optimization method in the embodiment of the present invention, will be in chip layout
The metal layer that portion needs to be used to transmit high current removes, and replaces with multiple opennings, then be interconnected in one by more package leads
It rises, and then reduces chip area, save the cost.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the lead frame figure generally encapsulated；
Fig. 2 is the bare die schematic diagram for being subjected to high current with openning；
Fig. 3 is bare die packaging and routing schematic diagram；
Fig. 4 is a kind of layout of high-power chip domain of the present invention and the flow chart of packaging and routing optimization method；
Fig. 5 is a kind of packaging and routing schematic diagram of high-power chip domain of the present invention.
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work
It encloses.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover
Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to
Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product
Or other step or units that equipment is intrinsic.
Embodiment 1
Fig. 1-3 is the packaging and routing schematic diagram of the prior art, specifically:
Fig. 1 is the lead frame figure generally encapsulated, and third side's block portion is divided into cavity, and surrounding square is that each of encapsulation draws
Foot has 2N pin here.
Fig. 2 is the bare die schematic diagram for being subjected to high current with openning.Wherein square block is the openning of bare die.Up and down
The square in direction indicates that the main branch for being subjected to high current, main branch can bear electric current, and cannot be less than this chips can bear
Maximum current.The square of left and right directions indicates that each current branch, the sum of each current branch cannot be less than this chips institute
The maximum current that can be born.
Fig. 3 is bare die packaging and routing schematic diagram.
An embodiment according to the present invention provides the layout and packaging and routing optimization method of a kind of high-power chip domain,
Referring to fig. 4, comprising the following steps:
S101: the main branch for being subjected to high current is deleted in chip layout, leaves each current branch；
S102: several opennings are added in chip layout and are connected respectively to each current branch；
S103: the openning whole routing that current branch each in chip layout is connected is connected to the same packaging pin
On, it completes interconnection and electric current summarizes.
The layout and packaging and routing optimization method of high-power chip domain in the embodiment of the present invention, inside chip layout
It needs the metal layer for transmitting high current to remove, replaces with multiple opennings, then be interconnected by more package leads,
And then reduce chip area, save the cost.The metal layer cable tray for transmitting high current in chip is saved, chip face is reduced
Product, and then reduced cost, while after removing big metal layer, domain cabling can also be flexibly many.
In as a preferred technical scheme, the sum of electric current that each current branch can bear can be held not less than chip layout
The maximum current received.
In as a preferred technical scheme, the openning whole routing that current branch each in chip layout is connected is connected
Onto first packaging pin of chip layout.
In as a preferred technical scheme, the packaging pin quantity of chip layout is 2N, and 2N packaging pin is along chip
Domain is sequentially arranged clockwise, and N is the integer more than or equal to 1.
Embodiment 2
According to another embodiment of the present invention, a kind of high-power chip domain is provided, referring to Fig. 5, including chip layout
Ontology is provided with several branches and several opennings on chip layout, and several opennings are connected respectively in several current branch,
The openning whole routing that several current branch are connected is connected on the same packaging pin.
In as a preferred technical scheme, the sum of electric current that several current branch can bear is not less than chip layout institute energy
The maximum current of receiving.
In as a preferred technical scheme, the openning whole routing that several current branch are connected is connected to chip layout
On first packaging pin of ontology.
In as a preferred technical scheme, the packaging pin quantity of chip layout ontology is 2N, 2N packaging pin edge
Chip layout ontology is sequentially arranged clockwise, and N is the integer more than or equal to 1.
High-power chip domain in the embodiment of the present invention will need the metal for transmitting high current inside chip layout
Layer remove, replace with multiple opennings, then be interconnected by more package leads, so reduce chip area, saving at
This.The metal layer cable tray for transmitting high current in chip is saved, reduces chip area, and then reduced cost, while
After removing big metal layer, domain cabling can also be flexibly many.
The serial number of the above embodiments of the invention is only for description, does not represent the advantages or disadvantages of the embodiments.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (8)
1. the layout and packaging and routing optimization method of a kind of high-power chip domain, which comprises the following steps:
The main branch for being subjected to high current is deleted in chip layout, leaves each current branch；
Several opennings are added in chip layout is connected respectively to each current branch；
The openning whole routing that current branch each in chip layout is connected is connected on the same packaging pin.
2. the method according to claim 1, wherein the sum of electric current that each current branch can bear is not less than institute
State the maximum current that chip layout can bear.
3. the method according to claim 1, wherein the openning that current branch each in chip layout is connected
Whole routings are connected on first packaging pin of the chip layout.
4. according to the method described in claim 3, it is characterized in that, the packaging pin quantity of the chip layout is 2N a, 2N
A packaging pin is sequentially arranged clockwise along the chip layout, and N is the integer more than or equal to 1.
5. a kind of high-power chip domain, which is characterized in that including chip layout ontology, be provided on the chip layout several
Branch and several opennings, several opennings are connected respectively in several current branch, several current branch
The openning whole routing connected is connected on the same packaging pin.
6. chip layout according to claim 5, which is characterized in that the electric current that several current branch can bear it
With the maximum current that can bear not less than the chip layout.
7. chip layout according to claim 5, which is characterized in that the opening that several current branch are connected
Window whole routing is connected on first packaging pin of the chip layout ontology.
8. chip layout according to claim 7, which is characterized in that the packaging pin quantity of the chip layout ontology is
2N, the 2N packaging pins are sequentially arranged clockwise along the chip layout ontology, and N is the integer more than or equal to 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811432087.4A CN109585442B (en) | 2018-11-28 | 2018-11-28 | High-power chip layout and packaging routing optimization method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811432087.4A CN109585442B (en) | 2018-11-28 | 2018-11-28 | High-power chip layout and packaging routing optimization method thereof |
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| CN109585442A true CN109585442A (en) | 2019-04-05 |
| CN109585442B CN109585442B (en) | 2021-02-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113221500A (en) * | 2021-06-18 | 2021-08-06 | 苏州复鹄电子科技有限公司 | Chip routing layout automatic design method based on artificial intelligence algorithm |
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| CN101409281A (en) * | 2007-10-12 | 2009-04-15 | 美国芯源系统股份有限公司 | Method and apparatus for laying out pattern of high power switch mode voltage regulators |
| CN202996820U (en) * | 2012-12-17 | 2013-06-12 | 北京工业大学 | Rewiring QFN package device |
| CN103903996A (en) * | 2014-04-14 | 2014-07-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Chip bonding pad layout design method suitable for multiple different encapsulation requirements |
| CN104750886A (en) * | 2013-12-29 | 2015-07-01 | 北京华大九天软件有限公司 | Method for confirming pin access area in integrated circuit layout wiring |
| CN105575941A (en) * | 2016-02-03 | 2016-05-11 | 日银Imp微电子有限公司 | High-power resonant power supply control chip realized by double-chip package |
| CN108304614A (en) * | 2017-12-27 | 2018-07-20 | 苏州中晟宏芯信息科技有限公司 | The setting method and device of integrated circuit diagram pin |
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2018
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07307437A (en) * | 1994-05-10 | 1995-11-21 | Sony Corp | High density packaging method |
| CN101409281A (en) * | 2007-10-12 | 2009-04-15 | 美国芯源系统股份有限公司 | Method and apparatus for laying out pattern of high power switch mode voltage regulators |
| CN202996820U (en) * | 2012-12-17 | 2013-06-12 | 北京工业大学 | Rewiring QFN package device |
| CN104750886A (en) * | 2013-12-29 | 2015-07-01 | 北京华大九天软件有限公司 | Method for confirming pin access area in integrated circuit layout wiring |
| CN103903996A (en) * | 2014-04-14 | 2014-07-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Chip bonding pad layout design method suitable for multiple different encapsulation requirements |
| CN105575941A (en) * | 2016-02-03 | 2016-05-11 | 日银Imp微电子有限公司 | High-power resonant power supply control chip realized by double-chip package |
| CN108304614A (en) * | 2017-12-27 | 2018-07-20 | 苏州中晟宏芯信息科技有限公司 | The setting method and device of integrated circuit diagram pin |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113221500A (en) * | 2021-06-18 | 2021-08-06 | 苏州复鹄电子科技有限公司 | Chip routing layout automatic design method based on artificial intelligence algorithm |
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Address after: 430000 building 01, building 15, optical valley wisdom Park, No.7, financial port 1st Road, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan ruinajie Semiconductor Co.,Ltd. Address before: 430073, Hubei, East Lake province Wuhan New Technology Development Zone Finance port No. 7, No. 15, Optics Valley wisdom garden, No. 01 building Patentee before: WUHAN RUINAJIE ELECTRONIC TECHNOLOGY Co.,Ltd. |