CN113013144B - Digital isolator chip - Google Patents
Digital isolator chip Download PDFInfo
- Publication number
- CN113013144B CN113013144B CN201911319318.5A CN201911319318A CN113013144B CN 113013144 B CN113013144 B CN 113013144B CN 201911319318 A CN201911319318 A CN 201911319318A CN 113013144 B CN113013144 B CN 113013144B
- Authority
- CN
- China
- Prior art keywords
- capacitor
- fuse
- signals
- chip
- bare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 69
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 238000007493 shaping process Methods 0.000 claims abstract description 15
- 230000002708 enhancing effect Effects 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a novel digital isolator chip, comprising: the transmitting module is arranged on the primary side and is used for transmitting the digital signals after shaping and modulating the digital signals; the receiving module is arranged on the secondary side and is used for demodulating the received high-frequency differential signals, enhancing the driving capability and then outputting the signals; and an isolation module disposed between the primary side and the secondary side; the isolation module comprises a first bare core, a second bare core and a third bare core, wherein the third bare core is connected in series between the first bare core and the second bare core. The invention connects the fuse in series between the two voltage-resistant isolation capacitors of the original isolation module, when the digital isolator chip is broken down by high voltage, a high-resistance state is formed at the two ends of the fuse, thereby limiting the direct current between the input and the output and playing a good role in protecting personnel and equipment at the low voltage side.
Description
Technical Field
The present invention relates to an integrated circuit, and more particularly, to an isolation circuit for a semiconductor chip.
Background
The existing isolation method of the ON-CHIP capacitor isolator CHIP (ON-CHIP) is mainly realized by isolating silicon dioxide (SiO 2) between the metal of the lower polar plate of the capacitor and the metal of the upper polar plate of the capacitor. In a general scheme, a first layer of metal (M1) is adopted as a lower polar plate of the capacitor, a sixth layer of metal (M6) is adopted as an upper polar plate of the capacitor, dense SiO2 is filled between the M1 and the M6, and the thickness of the SiO2 layer is thicker as much as possible, so that higher voltage can be isolated.
Referring to fig. 1, the operation principle of the isolator chip is as follows: the digital signal is input from the VIN pin of the isolator chip, the frequency of the signal is generally DC-150 Mbps, and the signal quality is reduced due to the influence of the length and parasitism of a transmission path, for example, rising edge/falling edge time is increased, and a Schmitt trigger is required to perform signal shaping to change the signal into a square wave with good quality; then the modulator modulates the carrier wave generated by the internal high-frequency oscillator, and modulates the signal onto the carrier wave; the signal is connected with one end of an isolation module of the isolator chip, and is input into a demodulator through the isolation module to be amplified and demodulated, and the original input signal is recovered; and finally, the driving capacity is enhanced through the driving module, and the signals are output from the output end of the isolator chip, so that the isolated transmission of the signals is completed.
Referring to fig. 2, the isolation module includes a first die and a second die, and a pair of voltage-resistant isolation capacitors are respectively disposed on the first die and the second die: capacitor C 1P, capacitor C 1N, capacitor C 2P, capacitor C 2N; the total isolation of the isolation module is realized by connecting two capacitors in series, and the upper polar plates of the two capacitors are connected through a pressure welding wire, so that the total pressure resistance of the isolation module is the sum of the pressure resistance of the two isolation capacitors; the grounding between the two bare chips in the isolation module is respectively separated and independent, so that complete electrical isolation between the input and the output is realized.
Typically, the thickness of SiO2 between M1 and M6 of a 6-layer metal CMOS is about 7um, the withstand voltage capability of SiO2 is estimated by a conservative value of 400V/um, and the total withstand voltage capability is about 5600V. However, in some special applications, a voltage higher than 5600V still occurs to break down the isolation capacitor, and the impedance value between the input and the output of the digital isolator chip after breakdown is reduced to less than about 100kΩ to 500kΩ. If calculated from the extreme 100kΩ impedance, and assuming that the high voltage remains unabated, electrical leakage of tens to hundreds of mA can occur, causing personnel injury or equipment damage. This characteristic of the isolation module severely limits the digital isolator chip to certain high withstand voltage applications, particularly where safety is a concern.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a digital isolator chip for solving the problems that in the prior art, after high voltage breakdown, the isolator module is in a low-resistance state and the isolator chip no longer has any protection function. Problems may occur with personnel or equipment on the low pressure side.
To achieve the above and other related objects, the present invention provides a digital isolator chip comprising:
The transmitting module is arranged on the primary side and is used for transmitting the digital signals after shaping and modulating the digital signals;
The receiving module is arranged on the secondary side and is used for demodulating the received high-frequency differential signals, enhancing the driving capability and then outputting the signals;
and an isolation module disposed between the primary side and the secondary side;
The isolation module comprises a first bare core, a second bare core and a third bare core, wherein the third bare core is connected in series between the first bare core and the second bare core.
In an embodiment of the invention, the transmitting module includes a shaping unit and a modulating unit; the receiving module comprises a demodulator and a driving unit;
The input end of the shaping unit is the input end of the chip, and the input digital signals sequentially pass through the shaping unit and the modulation unit and then are output to the isolation module;
The isolated digital signals sequentially pass through the demodulator and the driving unit and then are output from the output end of the chip.
In an embodiment of the invention, the shaping unit comprises a schmitt trigger.
In an embodiment of the invention, the modulation unit includes a demodulator and a high frequency oscillator.
In an embodiment of the present invention, the first die is provided with a capacitor C 1P and a capacitor C 1N;
A capacitor C 2P and a capacitor C 2N are arranged on the second bare chip;
And a fuse F1 and a fuse F2 are arranged on the third bare chip.
In one embodiment of the present invention, the upper plate of the capacitor C 1P is connected to one side pad of the fuse F1, and the other side pad of the fuse F1 is connected to the upper plate of the capacitor C 2P.
In an embodiment of the present invention, the capacitor C 1P, the fuse F1 and the capacitor C 2P are connected by bonding wires.
In one embodiment of the present invention, the upper plate of the capacitor C 1N is connected to one side pad of the fuse F2, and the other side pad of the fuse F2 is connected to the upper plate of the capacitor C 2N.
In an embodiment of the present invention, the capacitor C 1N, the fuse F2 and the capacitor C 2N are connected by bonding wires.
In an embodiment of the present invention, the material of the fuse F1 and the material of the fuse F2 are polysilicon.
As described above, the digital isolator chip of the invention is characterized in that the fuse is connected in series between the two voltage-resistant isolation capacitors of the original isolation module, when the digital isolator chip is broken down by high voltage, a high-resistance state is formed at the two ends of the fuse, so that direct current between input and output is limited, and the digital isolator chip has a good protection effect on personnel and equipment at a low voltage side.
Drawings
Fig. 1 is a schematic diagram of a prior art isolator chip wiring scheme of the present invention.
Fig. 2 is a schematic diagram of an isolated module wiring according to the prior art of the present invention.
Fig. 3 shows a schematic diagram of the wiring of the isolator chip of the present invention.
Fig. 4 is a schematic diagram of the wiring of the isolation module according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Referring to fig. 3, the present invention provides a digital isolator chip, comprising:
The transmitting module is arranged on the primary side and is used for shaping and modulating the digital signals and transmitting the digital signals; the transmitting module comprises a shaping unit and a modulating unit. The shaping unit comprises a schmitt trigger, and the modulating unit comprises a demodulator and a high-frequency oscillator.
The receiving module is arranged on the secondary side and is used for demodulating the received high-frequency differential signals, enhancing the driving capability and then outputting the signals; the receiving module comprises a demodulator and a driving unit.
And an isolation module disposed between the primary side and the secondary side;
The isolation module comprises a first bare core, a second bare core and a third bare core, wherein the third bare core is connected in series between the first bare core and the second bare core.
Referring to fig. 4, the first die and the second die are the same two die, and a pair of isolation voltage-resistant capacitors are disposed on the first die: capacitor C 1P and capacitor C 1N; a pair of isolation voltage-resistant capacitors are arranged on the second bare chip: capacitor C 2P and capacitor C 2N;
And the third bare chip is provided with a fuse F1 and a fuse F2, and the fuse F1 and the fuse F2 are made of polysilicon.
The upper electrode plate of the capacitor C 1P is connected with the bonding pad on one side of the fuse F1 through a pressure welding wire, and the bonding pad on the other side of the fuse F1 is connected with the upper electrode plate of the capacitor C 2P through a pressure welding wire.
The upper electrode plate of the capacitor C 1N is connected with the bonding pad on one side of the fuse F2 through a pressure welding wire, and the bonding pad on the other side of the fuse F2 is connected with the upper electrode plate of the capacitor C 2P through a pressure welding wire.
Under normal conditions, high voltage is mainly borne by the isolation voltage-resistant capacitors on the first bare chip and the second bare chip, the fuse on the third bare chip is not fused, the two ends of the fuse are low-resistance, the isolator chip is not affected, meanwhile, the current flowing through the fuse under normal conditions is very small, and the fuse keeps good conduction and cannot be fused;
When the voltage between the input and the output is too high, the isolation voltage-resistant capacitors on the first bare chip and the second bare chip are broken down, and a large current flows from the high-voltage side to the low-voltage side instantaneously; when the current exceeds the bearing current of the fuse, the fuse is fused, so that the two ends of the fuse become high-resistance, and the isolator chip can protect personnel and equipment on the low-voltage side.
Referring to fig. 3, a single-ended signal is input from VIN pin of the isolator chip, shaped by the schmitt trigger, then the modulator and carrier generated by the internal high-frequency oscillator are subjected to OOK modulation to high frequency, converted into differential signals, transmitted to the isolation module, the first differential signal is output via capacitor C 1P, fuse F1 and capacitor C 2P, the second differential signal is output via capacitor C 1N, fuse F2 and capacitor C 2N, the demodulator receives signals from capacitor C 2P and capacitor C 2N, demodulates the signals, recovers the input signals, and outputs via VOUT pin after driving enhancement.
In summary, according to the digital isolator chip disclosed by the invention, the fuse is connected in series between the two voltage-resistant isolation capacitors of the original isolation module, when the digital isolator chip is broken down by high voltage, high resistance states are formed at the two ends of the fuse, direct current between input and output is limited, and a good protection effect is achieved on personnel and equipment at a low voltage side. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (4)
1. A digital isolator chip comprising:
The transmitting module is arranged on the primary side and is used for transmitting the digital signals after shaping and modulating the digital signals;
The receiving module is arranged on the secondary side and is used for demodulating the received high-frequency differential signals, enhancing the driving capability and then outputting the signals;
and an isolation module disposed between the primary side and the secondary side;
The isolation module comprises a first bare core, a second bare core and a third bare core, and the third bare core is connected in series between the first bare core and the second bare core;
The first bare chip is provided with a capacitor C 1P and a capacitor C 1N, wherein a lower polar plate of the capacitor C 1P and a lower polar plate of the capacitor C 1N on the first bare chip are made of a first layer of metal, an upper polar plate is made of a sixth layer of metal, and dense SiO2 is filled between the first layer of metal and the sixth layer of metal;
The second bare chip is provided with a capacitor C 2P and a capacitor C 2N, wherein a lower polar plate of the capacitor C 2P and a lower polar plate of the capacitor C 2N on the second bare chip are made of a first layer of metal, an upper polar plate is made of a sixth layer of metal, and dense SiO2 is filled between the first layer of metal and the sixth layer of metal;
the third bare chip is provided with a fuse F1 and a fuse F2;
The upper plate of the capacitor C 1P is connected with a bonding pad on one side of the fuse F1, and the bonding pad on the other side of the fuse F1 is connected with the upper plate of the capacitor C 2P;
The upper plate of the capacitor C 1N is connected with a bonding pad on one side of the fuse F2, and the bonding pad on the other side of the fuse F2 is connected with the upper plate of the capacitor C 2N;
the transmitting module comprises a shaping unit and a modulating unit; the receiving module comprises a demodulator and a driving unit;
The input end of the shaping unit is the input end of the chip, and the input digital signals sequentially pass through the shaping unit and the modulation unit and then are output to the isolation module;
the isolated digital signals sequentially pass through the demodulator and the driving unit and then are output from the output end of the chip;
the shaping unit comprises a schmitt trigger;
the modulation unit comprises a demodulator and a high-frequency oscillator;
The single-ended signal is shaped by a Schmitt trigger from an isolator chip, then the modulator and a carrier wave generated by an internal high-frequency oscillator are subjected to OOK modulation, modulated to high frequency, converted into differential signals and transmitted to an isolation module, the first differential signals pass through a capacitor C1P, a fuse F1 and a capacitor C2P, the second differential signals pass through a capacitor C1N, a fuse F2 and a capacitor C2N, and the demodulator receives signals from the capacitor C2P and the capacitor C2N, demodulates the signals, recovers input signals, drives and enhances the signals and outputs the signals.
2. A digital isolator chip as in claim 1, wherein: the capacitor C 1P, the fuse F1 and the capacitor C 2P are connected through a pressure welding wire.
3. A digital isolator chip as in claim 1, wherein: the capacitor C 1N, the fuse F2 and the capacitor C 2N are connected through pressure welding wires.
4. A digital isolator chip as in claim 1, wherein: the materials of the fuse F1 and the fuse F2 are polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911319318.5A CN113013144B (en) | 2019-12-19 | 2019-12-19 | Digital isolator chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911319318.5A CN113013144B (en) | 2019-12-19 | 2019-12-19 | Digital isolator chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113013144A CN113013144A (en) | 2021-06-22 |
| CN113013144B true CN113013144B (en) | 2024-05-14 |
Family
ID=76381286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911319318.5A Active CN113013144B (en) | 2019-12-19 | 2019-12-19 | Digital isolator chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113013144B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114464458A (en) * | 2022-02-14 | 2022-05-10 | 安徽启电自动化科技有限公司 | Signal isolation capacitor, PCB and signal isolation transmission device |
| CN116705710B (en) * | 2023-06-13 | 2024-02-20 | 北京中科格励微科技有限公司 | Airtight digital isolator based on wafer reconstruction and manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9473329B1 (en) * | 2015-01-21 | 2016-10-18 | Holt Integrated Circuits | Analog front-end with galvanically isolated differential bus |
| CN107919861A (en) * | 2016-10-08 | 2018-04-17 | 北京中科格励微科技有限公司 | A kind of digital signal isolator |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7821428B2 (en) * | 2004-06-03 | 2010-10-26 | Silicon Laboratories Inc. | MCU with integrated voltage isolator and integrated galvanically isolated asynchronous serial data link |
| US7923710B2 (en) * | 2007-03-08 | 2011-04-12 | Akros Silicon Inc. | Digital isolator with communication across an isolation barrier |
| US8451032B2 (en) * | 2010-12-22 | 2013-05-28 | Silicon Laboratories Inc. | Capacitive isolator with schmitt trigger |
| US8643138B2 (en) * | 2011-06-30 | 2014-02-04 | Silicon Laboratories Inc. | High breakdown voltage integrated circuit isolation structure |
| US8625242B2 (en) * | 2011-08-03 | 2014-01-07 | Maxim Integrated Products, Inc. | Failsafe galvanic isolation barrier |
-
2019
- 2019-12-19 CN CN201911319318.5A patent/CN113013144B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9473329B1 (en) * | 2015-01-21 | 2016-10-18 | Holt Integrated Circuits | Analog front-end with galvanically isolated differential bus |
| CN107919861A (en) * | 2016-10-08 | 2018-04-17 | 北京中科格励微科技有限公司 | A kind of digital signal isolator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113013144A (en) | 2021-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113013144B (en) | Digital isolator chip | |
| US10594162B2 (en) | Galvanic isolator | |
| KR101805246B1 (en) | Driver circuit and method of generating an output signal | |
| CN108666303A (en) | Method and device for electric over-stress and electrostatic discharge (ESD) protection | |
| JP2006502686A (en) | Protection device to prevent differential mode transient voltage flow | |
| CN104218542A (en) | Battery protection circuit | |
| JP2018521513A (en) | Conductive seal ring for power bus distribution | |
| JP2010233140A (en) | Semiconductor integrated circuit device | |
| CN203774781U (en) | Signal interface high-power electromagnetic pulse protection device | |
| US7965479B2 (en) | Over-current and over-voltage protection assembly apparatus | |
| CN203027597U (en) | Power adapter and electrostatic discharge protective circuit thereof | |
| CN208190897U (en) | A kind of electrostatic discharge protective circuit of microphone | |
| CN221282122U (en) | Isolation gate structure and isolator chip | |
| CN201061140Y (en) | Single phase AC power supply line and signal circuit double protected lightning protection device | |
| CN104157664B (en) | Image sensor noise restraint full-chip ESD protection structure | |
| CN102891186A (en) | Protection diode and semiconductor device having the same | |
| US20160308347A1 (en) | Protection module and decoupling component thereof for symmetrical twisted pairs | |
| JP6897628B2 (en) | Semiconductor device | |
| CN105790026B (en) | Mobile terminal, USB and its manufacture method | |
| CN220775393U (en) | Structure of protection chip based on open circuit failure mode and electronic equipment | |
| CN201234127Y (en) | Leakage protection circuit and apparatus for non-balance interface | |
| CN220527691U (en) | Electrostatic protection network port and circuit board | |
| CN108428697A (en) | A kind of low-capacitance bidirectional band negative resistance TVS device | |
| CN102646902A (en) | Anti-high-pressure surging connector and circuit board using same | |
| TW201811121A (en) | Electrostatic discharge protection apparatus and electrostatic discharge protection method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |