CN2676411Y - Golden finger structure - Google Patents

Golden finger structure Download PDF

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Publication number
CN2676411Y
CN2676411Y CNU2003201266461U CN200320126646U CN2676411Y CN 2676411 Y CN2676411 Y CN 2676411Y CN U2003201266461 U CNU2003201266461 U CN U2003201266461U CN 200320126646 U CN200320126646 U CN 200320126646U CN 2676411 Y CN2676411 Y CN 2676411Y
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CN
China
Prior art keywords
golden finger
chip
gold finger
unit
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNU2003201266461U
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Chinese (zh)
Inventor
吴凯强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced packaging and testing (Hongkong) Co.,Ltd.
Riyueguang Semiconductor Weihai Co ltd
Original Assignee
Weiyu Semiconductor Hongkong Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Weiyu Semiconductor Hongkong Co ltd filed Critical Weiyu Semiconductor Hongkong Co ltd
Priority to CNU2003201266461U priority Critical patent/CN2676411Y/en
Application granted granted Critical
Publication of CN2676411Y publication Critical patent/CN2676411Y/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

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  • Packages (AREA)

Abstract

The utility model relates to a gold finger structure. A single gold finger on known packaging base plates is redesigned into a gold finger group which has a plurality of gold finger units. The electric connection relation is arranged between every two gold finger units evenly. Therefore, in a stacked packaging structure, every leading wire which is connected with the same gold finger by wiring in original chips of every layer can be wired on different gold finger units of the same gold finger group respectively. By utilizing the gold finger structure of the utility model, that the chip is adhered to a colloid to contaminate the entire gold finger along the wiring path of the chip of one layer can be avoided, and then the deficiency that the chips of other layers can not be wired is avoided.

Description

The golden finger structure
Technical field
The utility model relates to a kind of golden finger structure, particularly relates to a kind of golden finger structure that is applied to stack package structure.
Background technology
Multicore sheet encapsulation (Multi-chip Package, MCP) technology now has been widely used on the memory package market of mobile phone, this be a kind of with the multiple chips storehouse to be encapsulated as the technology of an IC.As shown in Figure 1, it is a storehouse encapsulating structure schematic diagram, as seen from the figure, on a base plate for packaging 10, be provided with a lower floor's chip 12 and a upper strata chip 14, lower floor's chip 12 attaches on the base plate for packaging 10 by lower floor's adhesion colloid 16, and the upper strata chip also attaches on lower floor's chip 12 by a upper strata adhesion colloid 18, and this two chip 12 14 sees through topping wire 20 respectively and is electrically connected with a following layer conductor 22 and a golden finger 24.
With reference to Fig. 2, because can producing along base plate for packaging 10, adhesion colloid flows, so in lower floor's adhesion colloid 16 sides groove 26 can be set outwards overflows to stop lower floor's adhesion colloid 16, yet upper strata adhesion colloid 18 but still can overflow glue on golden finger 24 along following layer conductor 22, so, topping wire 20 promptly can't routing on golden finger 24.
And as shown in Figure 3, during the routing offset of layer conductor 22 on golden finger 24 instantly, topping wire 20 again can be for want of enough the routing space and be difficult to routing on golden finger 24, even and if lower floor's chip 12 and upper strata chip 14 is big or small identical littler, as shown in Figure 4, more be difficult to following layer conductor 22 heavy industrys to solve the problem of routing offset.
Summary of the invention
Main purpose of the present utility model provides a kind of golden finger structure, in stack package structure, can directly the lead-in wire that links to each other be connected to respectively on the different golden fingers unit of same golden finger group on each layer chip.
Another purpose of the present utility model provides a kind of golden finger structure, avoids in the stack package structure, and adhesion colloid is along the routing path of certain layer of chip and pollute whole golden finger, and then makes the disappearance that other layer chip can't routing.
Another purpose of the present utility model provides a kind of golden finger structure, avoids in the stack package structure, and certain layer of routing offset of chip on golden finger, and make the disappearance that other layer chip can't routing.Above-mentioned purpose of the present utility model is to realize like this, a kind of golden finger structure, be established in the package stack stack architecture, it is characterized in that package stack stack architecture has several layers of chip, and each this chip has several lead-in wires respectively, links to each other with several golden finger groups respectively, and each this golden finger group has several golden finger unit, it electrically connects to each other, and respectively this lead-in wire that directly links to each other on each this chip is connected to respectively on the golden finger unit of same this golden finger group.Routing produced on same golden finger the adhesion colloid of can avoiding by this respectively going between pollutes and problem such as routing offset.
By following in conjunction with the accompanying drawings to the detailed description of specific embodiment, the effect that will be easier to understand the purpose of this utility model, technology contents, characteristics and be reached.
Description of drawings
Fig. 1 is known stack package structure schematic diagram;
Fig. 2 is the excessive glue problem schematic diagram of known stack package structure;
Fig. 3 and Fig. 4 are known stack package structure routing offset schematic diagram;
Cutaway view and the vertical view of Fig. 5 and Fig. 6 the utility model embodiment;
Fig. 7 pollutes the schematic diagram of each golden finger unit for the utility model prevents viscose;
Fig. 8 and Fig. 9 are other embodiment schematic diagram of the utility model.
Description of reference numerals: 10 substrates; 12 lower floor's chips; 14 upper strata chips; 16 lower floor's viscoses; 18 upper strata viscoses; 20 topping wire; 22 times layer conductors; 24 golden fingers; 26 grooves; 30 substrates; 32 lower floor's chips; 34 upper strata chips; 36 lower floor's viscoses; 38 upper strata viscoses; 40 golden finger unit; 42 leads; 44 welding resisting layers; 46 times layer conductors; 48 topping wire; 50 chips; 52 lead-in wires.
Embodiment
Cutaway view and vertical view referring to Fig. 5 and the utility model embodiment shown in Figure 6, as seen from the figure, one storehouse encapsulating structure is established on the base plate for packaging 30, this stack package structure comprises a lower floor's chip 32 and a upper strata chip 34, lower floor's chip 32 is attached on the base plate for packaging 30 by lower floor's colloid 36,34 of upper strata chips utilize a upper strata colloid 38 to attach on lower floor's chip 32, other has several golden finger groups, each golden finger group has two golden finger unit 40 respectively, it utilizes a lead 42 to form to each other and electrically connects, and also be coated with a welding resisting layer 44 on the lead 42, it can provide lead 42 anti-welding effects and can prevent that two golden finger unit 40 are simultaneously by upper strata or lower floor's colloid 38 36 pollution problems, therefore, with reference to Fig. 7, when layer conductor 46 is connected in the golden finger unit 40 of close base plate for packaging 30 inboards instantly, topping wire 48 can be connected in the golden finger unit 40 in the outside, that is polluted inboard golden finger unit 40 along following layer conductor 46 when upper strata colloid 38, also can not pollute the golden finger unit 40 in the outside and cause the problem that topping wire 38 can't routing.In addition, projection or the groove outside in lower floor's colloid 36 can be set also, to prevent the problem of lower floor's colloid 36 outside overflows.
And for example shown in Figure 8, in the measure-alike stack package structure of one upper and lower layer of chip 34,32, by using the utility model, can be when the position of layer conductor 46 on inboard golden finger unit 40 outwards be offset down, topping wire 48 is connected on the golden finger unit, the outside 40 smoothly, removing by this to provide the routing processing procedure higher processing procedure tolerance, need not more to worry that upper and lower layer chip 34,32 is measure-alike and be difficult to the problem of layer conductor 46 heavy industrys down.Yet except that the measure-alike stack package structure of said chip, the utility model also can be applied in the different stack package structure of chip size, to solve the problem of routing offset.
Refer again to Fig. 9, the utility model also can be applicable in the stack package structure of multilayer chiop storehouse, as shown in Figure 9, golden finger unit 40 quantity of each golden finger group are not less than the quantity of chip 50, so, respectively going between of can directly linking to each other on each chip 50 52 can be connected on the different golden fingers unit of same golden finger group.When the utility model is applied to the stack package structure of multicore sheet, the lead-in wire that can directly link to each other on the segment chip can be connected on the same golden finger unit, and the lead-in wire that can directly link to each other on the remaining chip is connected on other golden finger unit, increase by this and use elasticity of the present utility model.In addition, golden finger group of the present utility model also can be a complete golden finger, and its top zone design is coated with welding resisting layer, so by the covering of welding resisting layer, can mark off several golden finger unit on this complete golden finger.
From the above, the utility model utilizes the improvement of golden finger structure, and avoiding in the known techniques, adhesion colloid pollutes whole golden finger, and the problem brought of routing offset.
Above-described embodiment is preferred embodiment of the present utility model only, is not in order to limit the utility model practical range.So all equalizations of doing according to the described shape of the utility model claim, structure, feature and spirit change and modify, and all should be included within the protection range of the present utility model.

Claims (7)

1, a kind of golden finger structure, be established in the package stack stack architecture, it is characterized in that package stack stack architecture has several layers of chip, and each this chip has several lead-in wires respectively, link to each other with several golden finger groups respectively, each this golden finger group has several golden finger unit, and it electrically connects to each other, and respectively this lead-in wire that directly links to each other on each this chip is connected to respectively on the golden finger unit of same this golden finger group.
2, golden finger structure as claimed in claim 1 is characterized in that each lead-in wire that directly links to each other on each this chip is connected to the different golden fingers unit of same this golden finger group respectively.
3, golden finger structure as claimed in claim 2 is characterized in that the golden finger number of unit is not less than core number.
4, golden finger structure as claimed in claim 1 is characterized in that each lead-in wire that directly links to each other on this chip of part is connected to respectively on the identical golden finger unit of same this golden finger group.
5, golden finger structure as claimed in claim 1 is characterized in that forming electrical connection by at least one lead between each this golden finger unit.
6, golden finger structure as claimed in claim 4 is characterized in that being coated with on the lead welding resisting layer.
7, the golden finger structure of stating as claim 1 is characterized in that the golden finger group is a complete golden finger, and has at least a welding resisting layer to be covered in the part surface of this complete golden finger, marks off a plurality of these golden finger unit with this.
CNU2003201266461U 2003-12-10 2003-12-10 Golden finger structure Expired - Lifetime CN2676411Y (en)

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Application Number Priority Date Filing Date Title
CNU2003201266461U CN2676411Y (en) 2003-12-10 2003-12-10 Golden finger structure

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Application Number Priority Date Filing Date Title
CNU2003201266461U CN2676411Y (en) 2003-12-10 2003-12-10 Golden finger structure

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367264A (en) * 2012-03-27 2013-10-23 南亚科技股份有限公司 Package carrier plate capable of avoiding overflow of adhesive material
CN105321895A (en) * 2014-05-26 2016-02-10 南茂科技股份有限公司 Film flip chip packaging structure and flexible circuit carrier plate thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367264A (en) * 2012-03-27 2013-10-23 南亚科技股份有限公司 Package carrier plate capable of avoiding overflow of adhesive material
CN103367264B (en) * 2012-03-27 2016-08-31 南亚科技股份有限公司 A kind of encapsulating carrier plate avoiding glue material overflow
CN105321895A (en) * 2014-05-26 2016-02-10 南茂科技股份有限公司 Film flip chip packaging structure and flexible circuit carrier plate thereof

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Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: ADVANCED SEMICONDUCTOR ENGINEERING (WEIHAI) CO., L

Free format text: FORMER OWNER: ASE ASSEMBLY AND TEST (HONG KONG), LTD.

Effective date: 20120417

C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee

Owner name: ASE ASSEMBLY AND TEST (HONG KONG), LTD.

Free format text: FORMER NAME: GAPT SEMICONDUCTOR (HONGKONG) CO., LTD.

COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: HONG KONG, CHINA TO: 264205 WEIHAI, SHANDONG PROVINCE

CP03 Change of name, title or address

Address after: Hongkong Tongluowan 33 hysanavenue Lee Garden 34/F

Patentee after: Advanced packaging and testing (Hongkong) Co.,Ltd.

Address before: 000000 Hongkong Special Administrative Region of China

Patentee before: WEIYU SEMICONDUCTOR (HONGKONG) Co.,Ltd.

TR01 Transfer of patent right

Effective date of registration: 20120417

Address after: 264205 No. 16-1, Hainan Road, export processing zone, Weihai economic and Technological Development Zone, Shandong, China

Patentee after: RIYUEGUANG SEMICONDUCTOR(WEIHAI) Co.,Ltd.

Address before: Chinese Hongkong Tongluowan 33 hysanavenue Lee Garden 34/F

Patentee before: Advanced packaging and testing (Hongkong) Co.,Ltd.

C17 Cessation of patent right
CX01 Expiry of patent term

Expiration termination date: 20131210

Granted publication date: 20050202