CN106777437B - Clock system construction method and device and clock system - Google Patents
Clock system construction method and device and clock system Download PDFInfo
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Abstract
The invention provides a clock system and a construction method and device thereof. The clock system includes: the device comprises an isolation region and a non-isolation region which are arranged on a chip layout, wherein a clock device is arranged in the isolation region, a non-clock device is arranged in the non-isolation region, the non-clock device comprises at least two loads and at least two triggers, each trigger is coupled to the output end of one load, and the at least two loads are evenly placed in the non-isolation region. According to the method and the device for constructing the clock system and the clock system, the isolation region and the non-isolation region are divided on the chip layout, so that no other component overturns nearby a clock device, the overturning current of the region nearby the clock device is effectively reduced, the influence of voltage drop on the clock device is weakened, and power supply noise is isolated and prevented; meanwhile, the load is distributed in a balanced manner, so that the load has good symmetry, clock deviation is reduced, and clock performance is improved.
Description
Technical Field
The present invention relates to integrated circuit design methods, and in particular, to a method and an apparatus for constructing a clock system, and a clock system.
Background
With the increasing integration and complexity of chips, the number of functional modules in the chip is gradually increased, and the requirements of the functional modules on the clock are different, so that the whole chip is no longer suitable for the same clock service. A clock system in the prior art generally includes a global clock network and a local clock network, and a clock signal of the global clock network is usually sent to each local clock network after being subjected to frequency division, frequency multiplication, phase adjustment, and the like.
Generally, the layout and wiring of the components and metal lines of a chip are designed according to the functions of the chip and a clock system, but with the progress of the chip manufacturing process, the characteristic size of the process is smaller, the power supply voltage of the chip is lower, the clock deviation in the chip is increased, the quality of a clock signal is poor, and the clock performance is reduced.
In the prior art, the electrical characteristics of the wires of the load devices are generally consistent through a wire winding mode to reduce clock deviation, but the mode of achieving balanced distribution of the load devices through the wire winding method can present larger difference of parasitic parameters under different process angles, and the electrical characteristics of the wires of the load devices can be consistent only under a specific process angle, so that the method has a narrower application range and lower applicability.
Disclosure of Invention
The embodiment of the invention provides a clock system and a construction method and device thereof, which are used for solving the problem of narrow application range of clock deviation by adopting a winding mode and improving the quality of clock signals and the performance of clocks.
An embodiment of the present invention provides a clock system, including: an isolation region and a non-isolation region arranged on the chip layout
The clock device is arranged in the isolation area, the non-clock device is arranged in the non-isolation area, the non-clock device comprises at least two loads and at least two triggers, each trigger is coupled and connected with the output end of one load, and the at least two loads are placed in the non-isolation area in a balanced mode.
An embodiment of the present invention provides a method for constructing a clock system, including:
determining an isolation region and a non-isolation region of a chip layout, wherein the isolation region is used for placing a clock device, the non-isolation region is used for placing a non-clock device, the non-clock device comprises at least two loads and at least two triggers, and each trigger is coupled and connected with the output end of one load;
determining the placement positions of all the loads in the non-isolation area so as to enable all the loads to be placed in the non-isolation area in a balanced mode;
and determining that the clock device is placed in the isolation region, all the loads are placed in the non-isolation region, and each trigger is coupled and connected with the output end of one load, and performing clock tree synthesis according to the current positions of the clock device, all the loads and all the triggers to generate a clock system.
Another aspect of the embodiments of the present invention provides a clock system constructing apparatus, including:
the chip layout dividing module is used for determining an isolation region and a non-isolation region of a chip layout, wherein the isolation region is used for placing a clock device, the non-isolation region is used for placing a non-clock device, the non-clock device comprises at least two loads and at least two triggers, and each trigger is coupled to the output end of one load;
the load setting module is used for determining the placement positions of all the loads in the non-isolation area so as to enable all the loads to be placed in the non-isolation area in a balanced manner;
and the generating module is used for determining that the clock device is placed in the isolation area, all the loads are placed in the non-isolation area, and each trigger is coupled and connected with the output end of one load, and performing clock tree synthesis according to the current positions of the clock device, all the loads and all the triggers to generate a clock system.
According to the method and the device for constructing the clock system and the clock system, the isolation region and the non-isolation region are divided on the chip layout, only the clock device is limited in the isolation region, and other components are not turned around the clock device, so that the turning current of the region around the clock device is effectively reduced, the influence of voltage drop on the clock device is weakened, and power supply noise is isolated and prevented; meanwhile, the load is distributed in a balanced manner, so that the load has good symmetry, clock deviation is reduced, and clock performance is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a schematic structural diagram of a clock system according to a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a second clock system according to the present invention;
FIG. 3 is a schematic structural diagram of a clock system according to a third embodiment of the present invention;
FIG. 4 is a flowchart of a first embodiment of a method for constructing a clock system according to the present invention;
FIG. 5 is a flowchart of a second embodiment of a method for constructing a clock system according to the present invention;
FIG. 6 is a flow chart of a third embodiment of a method for constructing a clock system according to the present invention;
FIG. 7 is a schematic structural diagram of a first embodiment of a clock system according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a clock system. Fig. 1 is a schematic structural diagram of a clock system according to a first embodiment of the present invention. As shown in fig. 1, the clock system includes: the non-clock device is arranged in the non-isolation area and comprises at least two loads and at least two triggers, each trigger is coupled to the output end of one load, and the at least two loads are placed in the non-isolation area in a balanced mode.
The layout of each device on the chip and the layout of the connecting lines among the devices are chip layouts, and the different chip layouts influence the performance of the chip. For example, in the specific dividing process of the chip layout, as shown in fig. 1, a rectangular region is isolated in the middle of the chip layout to serve as an isolation region, and the rest regions serve as non-isolation regions. The isolation region is only used for placing a clock device, the non-isolation region is used for placing a non-clock device, and the non-clock device comprises a plurality of loads and a plurality of triggers. The flip-flops are coupled to the output terminals of the loads, and in specific connection, the coupling connection relationship between the flip-flops and the loads is not one-to-one, and a plurality of flip-flops may be coupled to the output terminal of one load or may be unevenly distributed to the output terminals of a plurality of loads. Fig. 2 is a schematic structural diagram of a second embodiment of the clock system according to the present invention. As shown in fig. 2, in the specific dividing process of the chip layout, the non-isolation region may also be disposed around the isolation region.
The clock device is isolated in the isolation region because after the clock device is started, logic gate units or triggers distributed around the clock device continuously turn over at a turn-over rate of 200%, so that a large current is generated around the clock device, and a certain voltage drop is caused under the condition that the resistance is not changed according to ohm's law. This voltage drop is an ohmic voltage drop which lowers the actual operating voltage of the clock device. If the ohmic voltage drop is too large, the clock device will not operate properly because the actual operating voltage is too low. By dividing the layout and limiting only the clock device in the isolation region, no other device is turned around the clock device, so that the turning current of the region around the clock device is effectively reduced, and the influence of voltage drop on the clock device is weakened.
All loads are distributed in the non-isolation region in a balanced manner, and the specific balanced distribution mode can be equal spacing in the transverse direction and the longitudinal direction on a chip layout or equal spacing ring shape surrounding the isolation region. The load with balanced distribution has good symmetry, so that the electrical characteristics of the wires of the load device are consistent, the path lengths of clock signals reaching different loads are the same, clock deviation is reduced, and meanwhile, the parasitic parameters of the wires under different process corners can keep good consistency, so that the difference of the clock deviation among different process corners is small, and the clock deviation of a finally formed clock system is small.
According to the clock system provided by the embodiment of the invention, the isolation region and the non-isolation region are divided on the chip layout, and only the clock device is limited in the isolation region, so that other devices are not turned over nearby the clock device, thereby effectively reducing the turning current of the region nearby the clock device, weakening the influence of voltage drop on the clock device, and isolating and preventing power supply noise; meanwhile, the load is distributed in a balanced manner, so that the load has good symmetry, clock deviation is reduced, and clock performance is improved.
The clock system provided by the present invention is described in detail below using specific embodiments.
Optionally, on the basis of any of the above embodiments, a decoupling capacitor is further filled in the isolation region of the clock system, and the decoupling capacitor is used for performing noise reduction processing on a clock signal output by the clock device. As the positive pole and the negative pole of the decoupling capacitor can respectively store positive charges and negative charges, when the clock device starts to turn over, the charges form current through a passage of the clock device, and meet a part of current requirements, so that ohmic voltage drop is reduced, the working voltage of the clock unit is stabilized, and the reliability of the system is enhanced through the current shunting mode.
Alternatively, on the basis of any of the above embodiments, in an actual configuration, the load may be a flip-flop, a latch, a clock gating cell, or the like. Based on the consideration of low power consumption design, a clock gating unit for performing on/off processing on an input clock signal to adjust the power consumption of the chip may be selected as a load of the clock system. Because the application scenes are different, some functional modules which are not used temporarily in the chip can be closed, so that the effect of reducing power consumption is achieved. The method for closing the module is that the enabling signal of the clock gating unit is changed, so that the clock signal sent to the inside of the module is set to be a fixed value, the flip-flop in the module stops turning, and the module is in a non-working state, so that the dynamic power consumption of the chip is reduced.
Optionally, on the basis of any of the above embodiments, when the flip-flops are mounted to the output terminals of the loads, the flip-flops having the same favorable clock skew planning requirement or being logically associated may be grouped into one type, the flip-flops classified into one type are also generally distributed on a chip layout, different flip-flop types are added to the output terminals of different loads of the clock system, and the same flip-flop type is coupled to the same load output terminal, and when the number of flip-flops of the same type is too large, the flip-flops may be coupled to the output terminals of a plurality of loads. By classifying the flip-flops, the timing closure process in clock system design may be accelerated. The flip-flops related to each other logically refer to flip-flops having a relatively close logical relationship from the viewpoint of structural design. For example, the flip-flops in the same pipeline stage may belong to the same bus, or may be a group of flip-flops that are combined together to implement functions such as an adder, a selector, and the like.
Optionally, on the basis of any of the above embodiments, at least one flip-flop is coupled to an output terminal of each load. The clock system provided by the invention does not comprise a load without a mounted trigger, and although the cutting can destroy the symmetry of the load to a certain extent, the load capacitance of the clock system is reduced, so that the time delay of the clock system is reduced. Meanwhile, no redundant unit is arranged, and the power consumption of the clock system can be effectively reduced.
Fig. 3 is a schematic structural diagram of a clock system according to a third embodiment of the present invention. As shown in fig. 3, based on any of the above embodiments, the clock system provided by the present invention further includes at least one inverter chain, each inverter chain is coupled to an output terminal of a load, and the inverter chains have a one-to-one correspondence relationship with the loads. The phase adjustment of the clock signal is realized by adjusting the time delay of the inverter chain. Illustratively, the inverter chain comprises a plurality of inverters with different time delays, and the plurality of inverters are identical in shape and size. Illustratively, the phase adjustment of the clock signal can be realized by changing inverters with different time delays and adjusting the time delay of the inverter chain. The phase of the clock signal can be advanced by replacing the phase inverter with smaller time delay; the phase of the clock signal can be delayed by replacing the phase inverter with larger time delay.
Optionally, on the basis of any of the above embodiments, the clock system provided by the present invention further includes at least one frequency divider, where the frequency divider is disposed between the load and the inverter chain; or the system further comprises at least one frequency multiplier arranged between the load and the inverter chain. Frequency dividers and frequency multipliers are used to implement the adjustment of the clock frequency.
In another aspect, the present invention further provides a method for constructing a clock system, which can be used to construct the clock system according to the foregoing embodiments. FIG. 4 is a flowchart of a first embodiment of a method for constructing a clock system according to the present invention. The execution body of the embodiment may be a construction device of a clock system, the device may be implemented by software and/or hardware, and the device may also be embedded in a terminal for implementation. And manufacturing components and connecting wires thereof which realize preset functions on the semiconductor substrate, and forming a chip after subsequent treatment. The chip layout is a layout for the distribution of the components and the connecting lines thereof on the semiconductor substrate, and the purposes of reducing the chip area, reducing interference and coupling and reducing power consumption are achieved through the layout planning. The clock device for providing the clock signal and the path through which the clock signal passes form a clock system.
As shown in fig. 4, the method of construction in the embodiment of the present invention includes:
In step 401, it is determined that the chip layout is divided into isolated regions and non-isolated regions. In the specific dividing process, as shown in fig. 1, a rectangular region may be isolated in the middle of the chip layout as an isolation region, and the rest regions may be non-isolation regions. The isolation region is only used for placing a clock device, the non-isolation region is used for placing a non-clock device, and the non-clock device comprises a plurality of loads and a plurality of triggers. The flip-flops are coupled to the output ends of the loads, and when the flip-flops are specifically coupled to the outputs of the loads, the coupling relationship between the flip-flops and the loads is not one-to-one, and a plurality of flip-flops may be coupled to the output end of one load or unevenly distributed to the output ends of a plurality of loads.
In step 402, the placement of all loads within the non-isolated region is determined to be evenly distributed. The specific distribution mode can be equal spacing in the transverse direction and the longitudinal direction on the chip layout, and can also be equal spacing ring shape surrounding the isolation region. The load with balanced distribution has good symmetry, so that the electrical characteristics of the wires of the load device are consistent, the path lengths of clock signals reaching different loads are the same, clock deviation is reduced, and meanwhile, the parasitic parameters of the wires under different process corners can keep good consistency, so that the difference of the clock deviation among different process corners is small, and the clock deviation of a finally formed clock system is small.
In a practical construction, the load may be a flip-flop, a latch, a clock gating cell, or the like. Based on the consideration of low power consumption design, a clock gating unit for performing on/off processing on an input clock signal to adjust the power consumption of the chip may be selected as a load of the clock system. Because the application scenes are different, some functional modules which are not used temporarily in the chip can be closed, so that the effect of reducing power consumption is achieved. The method for closing the module is that the enabling signal of the clock gating unit is changed, so that the clock signal sent to the inside of the module is set to be a fixed value, the flip-flop in the module stops turning, and the module is in a non-working state, so that the dynamic power consumption of the chip is reduced.
In step 403, after it is determined that the clock device is placed in the isolation region, all the loads are placed in the non-isolation region, and all the flip-flops are coupled to the output end of at least one load, the clock tree synthesis is performed according to the current positions of the clock device, all the loads, and all the flip-flops, so as to generate a clock system. The clock tree synthesis can adopt an automatic design tool or a manual layout and wiring mode to construct a clock tree with triggers as leaf nodes, complete layout (Placement) and wiring (Routing) of the clock tree, and produce a clock system with smaller clock deviation.
According to the method for constructing the clock system, the isolation region and the non-isolation region are divided on the chip layout, only the clock device is limited in the isolation region, and other components are not turned around the clock device, so that the turning current of the region around the clock device is effectively reduced, the influence of voltage drop on the clock device is weakened, and power supply noise is isolated and prevented; meanwhile, the load is distributed in a balanced manner, so that the load has good symmetry, clock deviation is reduced, and clock performance is improved.
Further, on the basis of the above embodiment, because the requirements of the functional modules in the chip on the clock signal are different, the clock signal output by the clock system through the load can be adjusted according to the requirements of the modules, the adjusted clock signal in each module forms a local clock, the unadjusted clock signal is a global clock, and the global clock and the local clock form a clock system. Wherein the adjusting of the clock signal comprises: frequency division, frequency multiplication, phase adjustment, duty ratio adjustment and the like. Specifically, the counting module can be added to divide the frequency of the clock signal, adjust the duty ratio, and the like.
In a specific implementation, the following method may be adopted for adjusting the phase of the clock signal:
before clock tree synthesis, generating an insertion signal which is inserted into an inverter chain at the output end of each load so as to insert the inverter chain into the output end of each load;
and after the load output ends are inserted into the inverter chain, adjusting the phase of the clock signal by adjusting the time delay of the inverter chain.
By inserting the inverter chains with different time delays, the same size, the same shape and the same pins into the load output end, the time delay of the inverter chains can be adjusted by replacing the inverters with different time delays, so that the phase adjustment of the clock signal is realized. The phase of the clock signal can be advanced by replacing the phase inverter with smaller time delay; the phase of the clock signal can be delayed by replacing the phase inverter with larger time delay.
According to the design requirements of each module of the chip, the clock signals output by the clock system through the load are adjusted, so that the local clock input to each module by the clock system is more suitable for the local module.
FIG. 5 is a flowchart of a second embodiment of a method for constructing a clock system according to the present invention. On the basis of any of the above embodiments, as shown in fig. 5, the method includes:
The specific implementation of steps 501, 502, and 503 in this embodiment is similar to that in the above embodiment, and this embodiment is not described again.
In step 504, the isolation region is filled with decoupling capacitors to isolate the power noise on the chip. As the positive pole and the negative pole of the decoupling capacitor can respectively store positive charges and negative charges, when the clock device starts to turn over, the charges form current through a passage of the clock device, and meet a part of current requirements, so that ohmic voltage drop is reduced, the working voltage of the clock unit is stabilized, and the reliability of the system is enhanced through the current shunting mode.
Further, on the basis of the above embodiment, the method for constructing a clock system according to the present invention further includes, before performing clock tree synthesis:
and generating a deletion redundant signal, wherein the deletion redundant signal is used for indicating the deletion of the load without the added trigger.
Alternatively, if an inverter chain has been inserted at each load output, the delete redundant signal is used to indicate the deletion of the load to which no flip-flop is added and the inverter chain coupled to the load output to which no flip-flop is added.
By generating the deletion redundant signal, the clipping of the redundant unit in the clock system is realized. When the output of the load does not have a flip-flop mounted, the load and its inverter chain can be deleted. Although the clipping will destroy the symmetry of the load to some extent, the load capacitance of the clock system is reduced, thereby reducing the time delay of the clock system. Meanwhile, the redundant unit is cut, so that the power consumption of the clock system can be effectively reduced.
Fig. 6 is a flowchart of a third embodiment of a clock system construction method of the present invention. On the basis of any of the above embodiments, as shown in fig. 6, the method includes:
601, determining an isolation region and a non-isolation region of a chip layout, wherein the isolation region is used for placing a clock device, the non-isolation region is used for placing a non-clock device, the non-clock device comprises at least two loads and at least two triggers, and all the triggers are used for being coupled and connected with the output end of at least one load;
and step 604, determining that the clock device is placed in the isolation region, all the loads are placed in the non-isolation region, and all the triggers are coupled and connected with the output end of at least one load, and performing clock tree synthesis according to the current positions of the clock device, all the loads and all the triggers to generate a clock system.
The specific implementation of steps 601, 602, and 604 in this embodiment is similar to that in the above embodiment, and this embodiment is not described again.
When the flip-flops are mounted to the output terminals of the loads, the flip-flops having the same favorable clock skew planning requirement or being logically associated can be grouped into one type, the flip-flops classified into one type are generally distributed together on a chip layout, different flip-flop types are added to the output terminals of different loads of the clock system, the same flip-flop type is coupled to the same load output terminal, and when the number of the flip-flops of the same type is too large, the flip-flops of the same type can be coupled to the output terminals of a plurality of loads. By classifying the flip-flops, the timing closure process in clock system design may be accelerated.
According to the method for constructing the clock system, the clock devices are arranged in the isolation region, and the load devices are distributed in a balanced manner, so that the prevention and isolation of power supply noise are realized, and the power supply interference is reduced; meanwhile, the clock gating unit is used as a load, and the functional module can be opened and closed, so that the purpose of reducing power consumption is achieved; and by inserting inverter chains and closely associating with favorable clock skew planning, the process of timing closure can be accelerated.
In particular embodiments, the above embodiments may also be combined to form new embodiments, providing a more stable clock system.
The embodiment of the invention also provides a construction device of the clock system. FIG. 7 is a schematic structural diagram of a first embodiment of a clock system according to the present invention. As shown in fig. 7, the apparatus includes:
the layout dividing module 701 is used for determining an isolation region and a non-isolation region of a chip layout, wherein the isolation region is used for placing a clock device, the non-isolation region is used for placing a non-clock device, the non-clock device comprises at least two loads and at least two triggers, and all the triggers are used for being coupled and connected with the output end of at least one load;
a load setting module 702, configured to determine placement positions of all loads in the non-isolation area, so that all loads are placed in the non-isolation area in a balanced manner;
the generating module 703 is configured to determine that the clock device is placed in the isolation region, all the loads are placed in the non-isolation region, and all the flip-flops are coupled to the output end of at least one load, and perform clock tree synthesis according to the current positions of the clock device, all the loads, and all the flip-flops to generate a clock system.
Optionally, the apparatus further comprises;
and the adjusting module is used for adjusting the clock signal output by the load after the clock signal of the clock device is output from the load, so as to generate an adjusted clock system.
Further, the adjusting module comprises:
a phase adjusting module for generating an insertion signal inserted into the inverter chain at an output terminal of each load so that each load output terminal is inserted into the inverter chain; and after the load output ends are inserted into the inverter chain, adjusting the phase of the clock signal by adjusting the time delay of the inverter chain.
Optionally, the apparatus further comprises:
the noise reduction module is used for determining and executing filling operation of filling decoupling capacitors in the isolation region; the decoupling capacitor is used for carrying out noise reduction processing on the clock signal output by the clock device.
Optionally, the apparatus further comprises:
and the clustering module is used for dividing the triggers with the same favorable clock skew plan or the triggers related to logic into the same class, so that the triggers coupled and connected with the output end of one load are the same class of triggers.
Optionally, the apparatus further comprises:
and the redundancy removing module is used for generating a redundancy removing signal, and the redundancy removing signal is used for indicating the load without the added trigger to be removed and an inverter chain coupled to the output end of the load without the added trigger.
In the above embodiment, the load may be a clock gating unit, and the clock gating unit is configured to turn on or off an input clock signal to adjust power consumption of the chip.
The clock system constructing apparatus provided in the embodiment of the present invention may implement the above clock system constructing method embodiment, and specific implementation principles and technical effects thereof may refer to the above method embodiment, which is not described herein again.
According to the method and the device for constructing the clock system and the clock system, the isolation region and the non-isolation region are divided on the chip layout, only the clock device is limited in the isolation region, and other components are not turned around the clock device, so that the turning current of the region around the clock device is effectively reduced, the influence of voltage drop on the clock device is weakened, and power supply noise is isolated and prevented; meanwhile, the load is distributed in a balanced manner, so that the load has good symmetry, clock deviation is reduced, and clock performance is improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A clock system, comprising: an isolation region and a non-isolation region arranged on the chip layout
A clock device is arranged in the isolation area, a non-clock device is arranged in the non-isolation area, the non-clock device comprises at least two loads and at least two triggers, each trigger is coupled and connected with the output end of one load, and the at least two loads are placed in the non-isolation area in a balanced manner;
the isolation region is also filled with a decoupling capacitor, and the decoupling capacitor is used for carrying out noise reduction processing on a clock signal output by the clock device;
the load is specifically a clock gating unit, and the clock gating unit is used for turning on or off an input clock signal so as to adjust the power consumption of the chip;
the system further comprises at least one inverter chain, each inverter chain is coupled with the output end of one load, and the inverter chains and the loads have one-to-one correspondence.
2. The system of claim 1, wherein if the load is a load coupled to a flip-flop, the load is coupled to a flip-flop of a same class, the flip-flops of the same class having a same favorable clock skew schedule, or logically associated flip-flops.
3. The system of claim 1,
the system further includes at least one frequency divider disposed between the load and the inverter chain; or
The system further includes at least one frequency multiplier disposed between the load and the inverter chain.
4. The system according to any one of claims 1 to 3, wherein at least one trigger is coupled to an output of each of the loads.
5. The system of claim 4, wherein the non-isolated region comprises a first non-isolated region and a second non-isolated region, the isolated region disposed between the first non-isolated region and the second non-isolated region.
6. The system of claim 4, wherein the non-isolated region is disposed around the isolated region.
7. The system of claim 4, wherein the inverter chain comprises a plurality of inverters having different time delays, the plurality of inverters being identical in shape and size.
8. A method of constructing a clock system, comprising:
determining an isolation region and a non-isolation region of a chip layout, wherein the isolation region is used for placing a clock device, the non-isolation region is used for placing a non-clock device, the non-clock device comprises at least two loads and at least two triggers, and each trigger is coupled and connected with the output end of one load;
determining the placement positions of all the loads in the non-isolation area so as to enable all the loads to be placed in the non-isolation area in a balanced mode;
determining that the clock device is placed in the isolation region, all the loads are placed in the non-isolation region, and each of the flip-flops is coupled to an output terminal of one of the loads, performing clock tree synthesis according to current positions of the clock device, all the loads, and all the flip-flops to generate a clock system, wherein,
after the generating the clock system, the method further comprises:
determining to perform a filling operation of filling the isolation region with a decoupling capacitor; the decoupling capacitor is used for carrying out noise reduction processing on the clock signal output by the clock device;
the load is specifically a clock gating unit, and the clock gating unit is used for turning on or off an input clock signal so as to adjust the power consumption of the chip;
each preset inverter chain in at least one inverter chain is coupled and connected with the output end of one load, and the inverter chains and the loads have one-to-one correspondence.
9. The method of claim 8, wherein said determining that each of said flip-flops is coupled before an output of one of said loads, further comprises:
the flip-flops with the same favorable clock skew schedule, or logically associated flip-flops, are classified into the same class so that the flip-flops of one of the load coupling connections are the same class of flip-flops.
10. The method of claim 9, wherein prior to performing clock tree synthesis, further comprising:
and generating a deletion redundancy signal, wherein the deletion redundancy signal is used for indicating the deletion of the load without the added trigger.
11. A construction set for a clock system, comprising:
the chip layout dividing module is used for determining an isolation region and a non-isolation region of a chip layout, wherein the isolation region is used for placing a clock device, the non-isolation region is used for placing a non-clock device, the non-clock device comprises at least two loads and at least two triggers, and each trigger is coupled to the output end of one load;
the load setting module is used for determining the placement positions of all the loads in the non-isolation area so as to enable all the loads to be placed in the non-isolation area in a balanced manner;
the generating module is used for determining that the clock device is placed in the isolation area, all the loads are placed in the non-isolation area, and each trigger is coupled and connected with the output end of one load, and performing clock tree synthesis according to the current positions of the clock device, all the loads and all the triggers to generate a clock system;
the isolation region is also filled with a decoupling capacitor, and the decoupling capacitor is used for carrying out noise reduction processing on a clock signal output by the clock device;
the load is specifically a clock gating unit, and the clock gating unit is used for turning on or off an input clock signal so as to adjust the power consumption of the chip;
each preset inverter chain in at least one inverter chain is coupled and connected with the output end of one load, and the inverter chains and the loads have one-to-one correspondence.
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| CN110399331A (en) * | 2019-08-07 | 2019-11-01 | 北京智芯微电子科技有限公司 | The method of clock signal noise is reduced in SOC chip and SOC chip |
| CN111881645B (en) * | 2020-07-03 | 2021-05-04 | 广芯微电子（广州）股份有限公司 | Clock tree anti-interference method and device based on noise timing sequence |
| CN116415539A (en) * | 2021-12-30 | 2023-07-11 | 长鑫存储技术有限公司 | Layout of clock tree and forming method thereof |
| CN114896941B (en) * | 2022-07-15 | 2022-10-25 | 飞腾信息技术有限公司 | Layout optimization method, optimization device and related equipment of clock tree |
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