CN101667830A - Phase-locked loop frequency synthesizer - Google Patents
Phase-locked loop frequency synthesizer Download PDFInfo
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Abstract
The invention provides a phase-locked loop frequency synthesizer, which comprises a phase detection discriminator, a charge pump, a first expansion circuit, a second expansion circuit, a first frequency detection discriminator, a second frequency detection discriminator, a charge pump and a second frequency detection discriminator, wherein the charge pump comprises an upper power supply; the first extension circuit provides a trigger signal for the second extension circuit according to the output of the phase detection discriminator; the second expansion circuit supplies current together with the upper and lower power supplies under the control of a trigger signal. The invention expands the linear working area by expanding the phase detection discriminator/charge pump, realizes the dynamic switching of the charge pump current in the locking process and accelerates the locking process.
Description
Technical field
The present invention relates generally to the transceiver technical field, more specifically, relates to phase-locked loop frequency integrator.
Background technology
Phase-locked loop frequency integrator is a key modules in the transceiver design, and it exports a series of high accuracy frequency signals, for the frequency translation of transceiver provides local oscillation signal.Phase-locked loop frequency integrator structure commonly used as shown in Figure 1, by the phase detection discriminator 101, charge pump 102, loop filter 103, the voltage controlled oscillator 104 that connect successively and be connected phase detection discriminator 101 inputs and voltage controlled oscillator 104 outputs between frequency divider 105 constitute.
The operation principle of phase-locked loop frequency integrator is: the frequency difference of phase detection discriminator 101 comparator input signals (reference signal) fref and feedback signal fdiv and differing, export a frequency/phase difference signal, when the fref signal takes the lead the fdiv signal, the output U signal, perhaps when the fref signal falls behind the fdiv signal, output D signal, the width of phase difference signal is represented the amplitude of two input signal differences here.Charge pump 102 produces the electric charge that is equivalent to phase difference signal of some.Loop filter 103 is importing the control voltage that electric charge changes into voltage controlled oscillator 104, and control voltage raises or reduces is to depend on phase difference signal (U or D signal).The cycle output signal frequency of voltage controlled oscillator 104 is functions of input voltage.Frequency divider 105 is the modules on the feedback path, can be integer type or fractional-type, and it mainly acts on the feedback factor that provides loop.
The phase-locked loop frequency integrator that adopts said structure therefore be most widely used, but this structure still has problems because theory and technology circuit the most ripe, that designing institute is used is fairly simple all the time.Because the linear working range that phase detection discriminator 101 is limited, when differ by more than ± during 2 π scopes, phase detection discriminator 101 can only provide unit gain to charge pump 102, and this makes voltage controlled oscillator 104 correctly not reduce frequency difference, causes phase-locked loop that a slow acquisition procedure is arranged.In order to address this problem, a kind of method is to calculate the number at two input signal edges, and the major defect of this method is when differing by more than ± during 2 π, occur simultaneously as if two edges of signals, the phenomenon of miscount can occurring.Another method is to utilize the feature of phase detection discriminator to quicken locking process, but this method is not suitable for various types of phase-locked loops application scenario to the loop parameter sensitivity.
Transceiver has proposed more and more harsher requirement to the locking time of phase-locked loop frequency integrator, and above-mentioned factor has restricted the locking time of conventional phase locked loops frequency synthesizer.Therefore, the frequency synthesizer of development of new structure has just become a very urgent problem with the needs that adapt to quick lock in.
Therefore, need a kind of solution of phase-locked loop frequency integrator, can solve the problem in the above-mentioned correlation technique.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of phase-locked loop frequency integrator that enlarges the phase detection discriminator linear working range, to solve the limited and slow acquisition procedure problem that causes of phase detection discriminator linear working range in the conventional phase locked loops frequency synthesizer.
In certain embodiments, described phase-locked loop frequency integrator comprises phase detection discriminator and charge pump, and described charge pump comprises power supply and following power supply, and described phase-locked loop frequency integrator also comprises first expanded circuit and second expanded circuit;
Described first expanded circuit is output as described second expanded circuit according to described phase detection discriminator triggering signal is provided;
Described second expanded circuit under the control of triggering signal on described power supply and following power supply electric current is provided.
Preferably, described second expanded circuit comprises:
With described power supply first current source module in parallel that goes up, be used for after the triggering on described power supply electric current is provided; And
With described power supply second current source module in parallel down, be used for after triggering, providing electric current with described power supply down.
Preferably, described first current source module and described second current source module comprise one or more current sources of the parallel connection of equal number respectively.
Preferably, described current source has identical electric current.
Preferably, described first expanded circuit comprises:
Phase difference signal produces circuit, is used for producing phase difference signal according to the output signal of described phase detection discriminator; And
Delay trigger circuit, its with described phase difference signal as input signal, with and output signal be used for triggering the current source of described first current module and the current source in described second current module.
Preferably, when in the described phase difference signal differ width greater than cycle of the reference signal of described phase detection discriminator input signal the time, described delay trigger circuit triggers current source in first current module and the current source in described second current module.
Preferably, described delay trigger circuit comprises:
Delay circuit comprises the one or more inverters that are connected in series, and is used for described phase difference signal is delayed time, and is respectively the inverter place of each integral multiple in the cycle of described reference signal in time of delay and exports the phase difference signal of a time-delay respectively;
One or more d type flip flops, respectively with the phase difference signal of each described time-delay as clock signal, and all with described phase difference signal as input signal, its output signal is respectively as the triggering signal of a current source in described first current module and a current source in described second current module.
Preferably, the quantity of the current source in the quantity of described d type flip flop and described first current source module and identical with the quantity of current source in described second current source module.
Preferably, the quantity of described d type flip flop is below 4.
Preferably, described phase difference signal generation circuit is an OR circuit.
From technique scheme as can be seen, the present invention has following technique effect:
1, Kuo Zhan phase detection discriminator can effectively enlarge the linear following range of phase detection discriminator, when differing by more than fref during the signal period, the electric current that is injected into loop filter is electric current in the conventional charge pump and the electric current sum in the auxiliary current source, when differing less than fref during the signal period, only the current source of conventional charge pump is injected into loop filter.The electric current that is injected into loop filter is dynamic change, and this has enlarged linear following range, helps to quicken locking process;
2, Kuo Zhan charge pump can provide different charging or discharging currents to loop filter, and the size of electric current is with differing proportional.When loop-locking, the only current source work of conventional charge pump, other additional current sources is effectively turn-offed, and does not increase additional power consumption;
3, the phase-locked loop frequency integrator among the present invention can carry out flexible configuration according to the application scenario.
Description of drawings
Fig. 1 is the block diagram of conventional phase locked loops frequency synthesizer;
Fig. 2 is the block diagram of the phase-locked loop frequency integrator of one embodiment of the invention;
Fig. 3 is the schematic diagram of the phase-locked loop frequency integrator detailed construction of one embodiment of the invention;
Fig. 4 is the structural representation of the delay circuit of the present invention in embodiment illustrated in fig. 3;
Fig. 5 is the delay circuit of the embodiment of the invention and the sequential chart of trigger group;
Fig. 6 is the linear working range curve of the phase detection discriminator/charge pump of one embodiment of the invention;
Fig. 7 is the electrical block diagram of the expansion charge pump of one embodiment of the invention.
Embodiment
Describe embodiments of the invention in detail below in conjunction with accompanying drawing, illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.
Comparison diagram 1 and Fig. 2 as can be seen, have increased charge pump expanded circuit 204 and phase detection discriminator expanded circuit 202 according to the phase-locked loop frequency integrator of the embodiment of the invention on the basis of conventional phase locked loops frequency synthesizer.Wherein, charge pump expanded circuit 204 comprises: first current source module, be connected in parallel with last power supply, be used for after the triggering with on power supply electric current is provided; And second current source module, be connected in parallel with following power supply, be used for after triggering providing electric current with power supply down.Phase detection discriminator expanded circuit 202 is used for being output as first current source module and second current source module provides triggering signal according to phase detection discriminator 101.
Wherein, first current source module and second current source module comprise the one or more current sources that are connected in parallel of equal number respectively, and each current source has identical electric current.
Wherein, phase detection discriminator expanded circuit 202 comprises: phase difference signal produces circuit, is used for producing phase difference signal according to the output signal of phase detection discriminator 101; And delay trigger circuit, its with phase difference signal as input signal, with and output signal be used for triggering the current source of first current module and the current source in second current module.
Wherein, when in the phase difference signal differ width greater than cycle of the reference signal of phase detection discriminator 101 input signals the time, delay trigger circuit triggers current source in first current module and the current source in second current module.
Wherein, delay trigger circuit comprises: one or more delay circuits, respectively with phase difference signal as input signal, and respectively phase difference signal is postponed after time of each integral multiple in cycle of reference signal and exports the phase difference signal of a time-delay separately; One or more d type flip flops, respectively with the time-delay phase difference signal as clock signal, and all with phase difference signal as input signal, its output signal is respectively as the triggering signal of a current source in first current module and a current source in second current module.
Wherein, delay trigger circuit comprises: delay circuit, comprise the one or more inverters that are connected in series, be used for phase difference signal is delayed time, and be respectively the inverter place of each integral multiple in the cycle of reference signal in time of delay and export the phase difference signal of a time-delay respectively; One or more d type flip flops, respectively with the time-delay phase difference signal as clock signal, and all with phase difference signal as input signal, as the triggering signal of a current source in first current module and a current source in second current module, wherein delay circuit as shown in Figure 4 respectively for its output signal.
Wherein, phase difference signal generation circuit is an OR circuit.
Wherein, the quantity of the current source in the quantity of d type flip flop and first current source module and equate with the quantity of current source in second current source module, and be below 4.
As can be seen, when differing by more than cycle reference signal, the transfer function of phase detection discriminator and charge pump still satisfies linear relationship, and this makes the gain of phase detection discriminator greater than unit gain, and the electric current that is injected on the loop filter increases, and has accelerated locking process.In the foregoing description, enlarge the linear working range of phase detection discriminator and charge pump, realized the dynamic switching of charge pump charging or discharging current in locking process, thereby quickened locking process, also had the characteristics of low-power consumption and small size simultaneously.
Fig. 3 illustrates the schematic diagram of phase-locked loop frequency integrator detailed construction according to an embodiment of the invention.With reference to Fig. 3, this phase-locked loop frequency integrator is connected in sequence by phase detection discriminator 101 or door 301, delay circuit 302,303 groups on trigger, charge pump 102, loop filter 103, voltage controlled oscillator 104 and frequency divider 105.
The annexation of phase detection discriminator 101, charge pump 102, loop filter 103, voltage controlled oscillator 104 and frequency divider 105 these modules is identical with the conventional phase locked loops frequency synthesizer with operation principle, and the circuit of increase comprises or 303 groups at door 301, delay circuit 302 and trigger.Charge pump 102 has n-1 (n is the natural number greater than 1) group auxiliary current source 304,304 pairs of each auxiliary current source be controlled by 303 groups on trigger output signal S0, S1 ..., Sn-1, switch U and switch D are controlled by the output of phase detection discriminator 101, an end and the current source of switch U and switch D link together, and the other end links together as the input of loop filter 103.Frequency divider 105 is connected between voltage controlled oscillator 104 outputs and phase detection discriminator 101 inputs.
In this embodiment, delay circuit 302 is made of chain of inverters, and as shown in Figure 4, the time-delay length of whole inverter equals n-1 the cycle of reference signal.The control of time-delay mainly is that the length that changes the mos pipe of inverter 401 realizes.The input signal of this chain of inverters be from or the door 301 circuit phase difference signal, this chain of inverters has n-1 output, this n-1 output is inputed to the input end of clock of each trigger 303 in 303 groups on the trigger respectively, delay circuit shown in Figure 4 is a preferred implementation, can also realize delay circuit with other forms in other embodiments, for example a plurality of delay circuits, respectively with phase difference signal as input signal, and respectively phase difference signal is postponed after time of each integral multiple in cycle of reference signal and exports the phase difference signal of a time-delay separately, and with the phase difference signal of these time-delays respectively as the clock signal of each d type flip flop.
Trigger is used for judging that differing width in the phase difference signal is times over cycle reference signal for 303 groups, and the clock of trigger 303 is input as the phase difference signal after the time-delay, and trigger end is input as phase difference signal.When phase difference signal width n-1 be high to the output of all triggers 303 of cycle reference signal (preferably, cycle reference signal is 2 π among this embodiment) doubly, therefore, output current be the electric current of n-1 group auxiliary current source 304 and charge pump 102 electric current with.Preferably, when n is 4, be that the width of phase difference signal is during greater than three times of cycle reference signals, the transfer function of charge pump 102 and phase detection discriminator 101 begins to occur non-linear, but the output current of charge pump 102 and differing is still the monotonically increasing relation, therefore, export to the electric current of the electric current of loop filter 103 greater than charge pump 102 outputs, this will help locking process.In addition, if differ by more than three times (promptly, during n＞4) cycle reference signal, electric current still keeps linear with differing, the electric current of auxiliary current source 304 need be designed to 2 power multiple, and this makes the design complexities of auxiliary current source 304 increase, and needs control circuit to select the output of trigger 303, therefore, n≤4 preferably in the present invention.In the present embodiment, the electric current of each auxiliary current source 304 is consistent, utilizes simple mirror method to produce needed current source current, need not extra control circuit.When differing when progressively dwindling, current source progressively turn-offs, and realizes the dynamic switching of electric current.When entering lock-out state, additional current sources is all turn-offed, only the current source work in the conventional charge pump 102.
Fig. 5 is according to the sequential chart of the delay circuit of the embodiment of the invention and trigger group, as can be seen from Figure 5, works as phase difference signal
Differ width less than 2 π the time, then phase difference signal as the time-delay of trigger clock signal the rising edge of the phase difference signal of 2 π after the time be low level when arriving, thereby trigger is output as low level, therefore, does not trigger auxiliary current source.And when phase difference signal width during greater than 2 π, as the time-delay of the clock signal of trigger the rising edge of the phase difference signal of 2 π after the time when arriving, phase difference signal as the trigger input signal is a high level, thereby trigger output high level will be opened follow-up current source.To automatically shut down in case differ, the steady-state behaviour of loop will not be had influence less than these additional current sources of opening of ± 2 π.
The output of phase detection discriminator 101 is divided into two-way, one tunnel similar traditional structure, directly be used for controlling the electric current of charge pump 102, lead up in addition or door 301 produces the phase difference signal that differs between reflection reference signals and the feedback signal, the phase extent has determined the size of current of charge pump 102.Or the output loading of door 301 increases along with the increase of trigger 303 quantity, this means or door 301 output loading increases, when reference signal frequency is higher, need or the trigger end of door 301 and 303 groups on trigger between insert buffer in case alleviate or output loading.
Fig. 6 shows the linear working range curve of phase detection discriminator/charge pump according to an embodiment of the invention.Fig. 6 (a) is the linear working range curve at traditional phase detection discriminator/charge pump, therefrom can see, when differing less than 2 π, charge pump current is with differing linear.When differ by more than ± during 2 π, the charge pump output current is constant to be ICP, no longer with differing the retention wire sexual intercourse.The transient performance of phase-locked loop can not clearly be expressed with formula, and locking process slows down.Fig. 6 (b) is at the linear working range curve according to the phase detection discriminator/charge pump of the expansion of the embodiment of the invention, in this embodiment, n=4, as can be seen from this figure, when differing less than ± 8 π, charge pump with differ linear, when differ by more than ± during 8 π, charge pump current still is the dull trend that increases with differing, this makes the transient performance of phase-locked loop frequency integrator can clearly express with formula in the working region than broad, the relative traditional structure of electric current that is injected into loop filter significantly increases, and this will speed up locking process.Simultaneously, the dynamic change of charge pump current does not change the parameter of loop, thus to loop stability without any influence.
In phase-locked loop frequency integrator structure of the present invention, electric charge pump structure in the conventional phase locked loops frequency synthesizer is improved, the result of improved charge pump as shown in Figure 7 according to the present invention, charge pump according to the present invention among Fig. 7 comprises conventional charge pump 102 and auxiliary current source 304, the operate as normal all in whole locking process of the current source in the conventional charge pump 102.Other n-1 group auxiliary current source 304 is only differing by more than ± just work during 2 π.The current value of respectively organizing current source in the auxiliary current source 304 is identical, produces by the mirror image mode easily.Except the current source in the conventional charge pump 102, but other current source all is that switch is controlled, and each additional current sources is to being subjected to the control of trigger 303 outputs.
The operating state of the phase-locked loop frequency integrator among the present invention is divided into stable state and acceleration mode.When being operated in stable state, be equal to the charge pump phase lock loop of traditional structure, when being operated in acceleration mode, delayer, trigger group and additional current sources enter operating state, when the approach locking state, the only current source work of conventional charge pump, additional current sources is turn-offed.At this moment, trigger and delayer are also working on, and certain power consumption is arranged, but because trigger or door and delayer are made of the digital circuit of low speed, circuit design is fairly simple, so power consumption is lower.
In embodiments of the present invention, phase-locked loop is a charge pump phase lock loop, and its phase detection discriminator is differentiated differing/frequency difference of reference signal and feedback signal, produces phase/frequency difference signal; Charge pump produces the electric charge corresponding to the some of phase/frequency difference signal; The add up charge generation loop filter voltage of some of loop filter; Voltage controlled oscillator is used to produce pll feedback signal.When steady-working state, only the conventional charge pump work under acceleration mode, has additional current sources and conventional charge pump to work simultaneously.Acceleration mode switches to stable state smoothly to carry out, and need not adjunct circuit.
The present invention is better than the phase-locked loop frequency integrator of traditional structure, because phase detection discriminator of the present invention has wide linear working range, makes to be injected into the electric current of loop filter and to differ in big scope to be directly proportional.This makes loop can enter the tracking lock state rapidly, can effectively shorten locking time.When loop is operated in stable state, only the conventional charge pump is in work, and additional current sources is turn-offed, and the power consumption of increase seldom.
Another advantage of the present invention is to compare with the circuit engineering of traditional acceleration locking process, and the present invention does not change loop parameter, and is insensitive to loop parameter, do not change the stability margin of loop, can be applied in different application scenarios neatly.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a phase-locked loop frequency integrator comprises phase detection discriminator and charge pump, and described charge pump comprises power supply and following power supply, it is characterized in that, also comprises first expanded circuit and second expanded circuit;
Described first expanded circuit is output as described second expanded circuit according to described phase detection discriminator triggering signal is provided;
Described second expanded circuit under the control of triggering signal on described power supply and following power supply electric current is provided.
2. phase-locked loop frequency integrator according to claim 1 is characterized in that, described second expanded circuit comprises:
With described power supply first current source module in parallel that goes up, be used for after the triggering on described power supply electric current is provided; And
With described power supply second current source module in parallel down, be used for after triggering, providing electric current with described power supply down.
3. phase-locked loop frequency integrator according to claim 2 is characterized in that, described first current source module and described second current source module comprise one or more current sources of the parallel connection of equal number respectively.
4. phase-locked loop frequency integrator according to claim 3 is characterized in that described current source has identical electric current.
5. phase-locked loop frequency integrator according to claim 3 is characterized in that, described first expanded circuit comprises:
Phase difference signal produces circuit, is used for producing phase difference signal according to the output signal of described phase detection discriminator; And
Delay trigger circuit, its with described phase difference signal as input signal, with and output signal be used for triggering the current source of described first current module and the current source in described second current module.
6. phase-locked loop frequency integrator according to claim 5, it is characterized in that, when in the described phase difference signal differ width greater than cycle of the reference signal of described phase detection discriminator input signal the time, described delay trigger circuit triggers current source in first current module and the current source in described second current module.
7. phase-locked loop frequency integrator according to claim 6 is characterized in that, described delay trigger circuit comprises:
Delay circuit comprises the one or more inverters that are connected in series, and is used for described phase difference signal is delayed time, and is respectively the inverter place of each integral multiple in the cycle of described reference signal in time of delay and exports the phase difference signal of a time-delay respectively;
One or more d type flip flops, respectively with the phase difference signal of each described time-delay as clock signal, and all with described phase difference signal as input signal, its output signal is respectively as the triggering signal of a current source in described first current module and a current source in described second current module.
8. phase-locked loop frequency integrator according to claim 7 is characterized in that, the quantity of the current source in the quantity of described d type flip flop and described first current source module and identical with the quantity of current source in described second current source module.
9. phase-locked loop frequency integrator according to claim 8 is characterized in that, the quantity of described d type flip flop is below 4.
10. according to each described phase-locked loop frequency integrator of claim 5 to 9, it is characterized in that it is OR circuit that described phase difference signal produces circuit.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078636A (en) * | 2012-12-27 | 2013-05-01 | 四川和芯微电子股份有限公司 | Phase-locked loop system |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of being locked quickly |
| CN103746692A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | PLL frequency synthesizer based on all-digital dynamic acceleration locking technology |
| CN106777437A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | The building method of clock system, device and clock system |
| CN107623521A (en) * | 2017-09-29 | 2018-01-23 | 中国科学院半导体研究所 | A kind of pll clock generator |
| CN108988854A (en) * | 2018-07-04 | 2018-12-11 | 西安电子科技大学 | Phase-locked loop circuit |
| CN112953529A (en) * | 2019-12-10 | 2021-06-11 | 上海交通大学 | Linear interval expanding method for rapid frequency locking and cycle slip elimination |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1134113C (en) * | 2002-06-28 | 2004-01-07 | 清华大学 | Broadband phase-looked loop frequency synthesizer |
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2009
- 2009-06-25 CN CN200910303644.7A patent/CN101667830B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103078636A (en) * | 2012-12-27 | 2013-05-01 | 四川和芯微电子股份有限公司 | Phase-locked loop system |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of being locked quickly |
| CN103746692A (en) * | 2013-12-24 | 2014-04-23 | 北京时代民芯科技有限公司 | PLL frequency synthesizer based on all-digital dynamic acceleration locking technology |
| CN103746692B (en) * | 2013-12-24 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of PLL frequency synthesizers based on digital dynamic acceleration lock-in techniques |
| CN106777437A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | The building method of clock system, device and clock system |
| CN106777437B (en) * | 2015-11-24 | 2020-05-19 | 龙芯中科技术有限公司 | Clock system construction method and device and clock system |
| CN107623521A (en) * | 2017-09-29 | 2018-01-23 | 中国科学院半导体研究所 | A kind of pll clock generator |
| CN107623521B (en) * | 2017-09-29 | 2020-10-20 | 中国科学院半导体研究所 | Phase-locked loop clock generator |
| CN108988854A (en) * | 2018-07-04 | 2018-12-11 | 西安电子科技大学 | Phase-locked loop circuit |
| CN112953529A (en) * | 2019-12-10 | 2021-06-11 | 上海交通大学 | Linear interval expanding method for rapid frequency locking and cycle slip elimination |
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| Publication number | Publication date |
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| CN101667830B (en) | 2013-03-06 |
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