CN103903996A - Chip bonding pad layout design method suitable for multiple different encapsulation requirements - Google Patents
Chip bonding pad layout design method suitable for multiple different encapsulation requirements Download PDFInfo
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- CN103903996A CN103903996A CN201410149177.8A CN201410149177A CN103903996A CN 103903996 A CN103903996 A CN 103903996A CN 201410149177 A CN201410149177 A CN 201410149177A CN 103903996 A CN103903996 A CN 103903996A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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Abstract
The invention discloses a chip bonding pad layout design method suitable for multiple different encapsulation requirements. According to the total number of bonding pads, the number of the bonding pads at each side of a chip and the dimensions of the chip in the length direction and in the width direction are determined; a basic encapsulation type is determined; the number and the positions of the bonding pads at each side of the chip are adjusted; another encapsulation type is selected, and a bonding figure is designed; optimizing methods of bonding the different bonding pads that the bonding pads with the bonding problem or different encapsulation types are replaced by moving the bonding pad positions with the bonding problem and increasing the number of the bonding pads are adopted, so that the bonding pads can meet the requirements of the different encapsulation types; the final bonding figure is designed. By means of the optimized layout of the chip bonding pads designed by the adoption of the design method, the phenomenon that the different encapsulating can not be conducted to the same chip unless the layout design is changed is solved, the requirement that the same chip can be suitable for different encapsulating is met, flexibility of chip encapsulating and chip applying is achieved, and cost is reduced.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, relate in particular to a kind of chip bonding pad layout design method that multiple different encapsulation requires that adapts to.
Background technology
Integrated circuit (IC) chip is generally made up of two parts: a part is internal circuit part, realizes circuit logic, the function of decision-making circuit; Another part is interface circuit, comprises electrostatic discharge protective circuit and pad (PAD), realize circuit protection and with being connected of external signal.Be connected with the lead frame of adopt on certain encapsulated type by chip bonding pad, chip finally becomes an integrated circuit finished product that encapsulation is complete.In the time that chip layout designs, the general position that arranges chip bonding pad according to selected a certain encapsulated type, as the one of dip (DIP) or surface mount encapsulation (SOP) etc., by the time after layout design completes, just must adopt selected a certain encapsulated type to carry out pressure welding, once require chip to adopt other packing forms, because shell inner chamber and the lead frame of different encapsulated types are all different, cause domain pad can not meet different encapsulated type requirements, the pad of special four corners at chip, the pad being easily adjacent when pressure welding produces overlap joint phenomenon.Chinese patent CN102237282A " a kind of contactless IC chip Pad layout design method ", adopt and become diagonal position to be able to make chip to adapt to the requirement of different encapsulation 2 adjacent pad design, but its application conditions there are many restrictions: 1) number of pads is few: 2 pads; 2) pad order: landless sequence requirement, pad locations is as long as upper and lower diagonal position, no matter and left and right; 3) encapsulated type: although packaging appearance difference, real encapsulation inner chamber is basic identical.Therefore, have the chip bonding pad of sequence requirement, the encapsulated type varying (not only profile difference, and inner chamber is also different) and be not suitable with for multiple, the method does not produce better effect.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of chip bonding pad layout design method that multiple different encapsulation requires that adapts to.
For solving the problems of the technologies described above, the invention provides a kind of chip bonding pad layout design method that multiple different encapsulation requires that adapts to, it is characterized in that, comprise the following steps:
In step 1, chip design is square, carries out layout calculation by square, and the pad number of determining the every limit of chip is N/4.
In step 4, selected other encapsulated type carries out pressure welding figure while designing, considers respectively following factor:
Whether the size of chip length and width direction meets the size of other encapsulated type shell tube chamber length and width direction, whether the pressure welding silk of adjacent pad produces overlap joint phenomenon.
In step 6, according to the chip bonding pad position of final confirmation, the pressure welding silk that the size of confirming chip length and width direction meets between dimensional requirement and the pad of different encapsulated type shell tube chamber length and width directions does not produce after overlap joint phenomenon, exports the pressure welding figure of different encapsulated types.
The beneficial effect that the present invention reaches:
Adopt the chip bonding pad layout after method for designing of the present invention is optimized, avoid same chip can not carry out different encapsulation and need to change the phenomenon of layout design, meet the requirements that same chip can adapt to different encapsulation, for chip package and chip application provide flexibility, reduced cost.
Accompanying drawing explanation
Fig. 1 is pad schematic diagram.
Fig. 2 is chip bonding pad schematic layout pattern.
Fig. 3 A is DIP encapsulation schematic diagram.
Fig. 3 B is SOP encapsulation schematic diagram.
Fig. 4 increases the chip layout schematic diagram that PAD is ordered.
Fig. 5 is SOP encapsulation schematic diagram after optimizing.
Fig. 6 optimizes chip layout schematic diagram behind PAD point position.
Fig. 7 A is final chip DIP encapsulation schematic diagram.
Fig. 7 B is final chip SOP encapsulation schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.Following examples are only for technical scheme of the present invention is more clearly described, and can not limit the scope of the invention with this.
1, determine the pad sum of chip and the pad number on every limit: determine the pad sum (N) of chip, comprise essential (as input, output), redundancy (as multiple power supplys), optional (as centre test) etc.; According to pad sum, roughly determine the pad number on every limit and the size of chip length and width direction.
2, determine basic encapsulated type: according to pad sum and chip area, the lumen size that selection meets the demands and the multiple encapsulated type of tube chamber lead frame, and select a kind of encapsulated type as basic encapsulated type.
3, determine the position of chip bonding pad: according to selected basic encapsulated type, further adjust pad number and the pad locations on the every limit of chip, make the size of chip length and width direction be less than respectively the size of shell tube chamber length and width direction.By the connection diagram of actual size design chips pad and shell tube chamber lead frame, the reasonability of checking pad locations design, guarantees that chip bonding pad layout meets selected basic encapsulated type.
4, determine other encapsulated type: according to the size of the pad number on definite every limit of chip and chip length and width direction, selected other encapsulated type carries out pressure welding figure design, whether the size of considering respectively chip length and width direction meets other the size of encapsulated type shell tube chamber length and width direction and whether the pressure welding silk of adjacent pad produces overlap joint phenomenon, if all met, do not need to optimize pad locations, directly export the pressure welding figure of this type by step 6; If do not met, need to optimize pad locations by step 5, it is met.
5, pad locations optimal design: understand the pad number and the position that have pressure welding problem by pressure welding figure, because number of pads is more and chip area is larger, easily there is the unreliable phenomenons such as pressure welding silk overlap joint at the pad of four corners of chip, the optimal design of pad is carried out mainly for pad herein, therefore the pad of less important, redundancy, test is placed on to corner as far as possible, makes it not affect the performance of circuit.Do not increasing as far as possible under the prerequisite of chip area, take mobile have the pad locations of pressure welding problem, increase pad around the corner and substitute the method such as the pad of pressure welding problem or the different pad of different encapsulated type pressure welding, make it meet different encapsulated type requirements.
6, design final pressure welding figure: according to the pressure welding figure of the different encapsulated types of the chip bonding pad Position Design of final confirmation, the pressure welding silk that the size of confirming chip length and width direction meets between dimensional requirement and the pad of different encapsulated type shell tube chamber length and width directions does not produce overlap joint phenomenon, exports the pressure welding figure of different encapsulated types.
Take certain chip design as example; the explanation of advanced line interface circuit relative dimensions; interface section 10 is made up of pad 11 and corresponding esd protection circuit 12 figures that are communicated with PAD point 11, and wherein pad 11 is square, length of side D1=70 μ m; solder pad space length D2=30 μ m; esd protection circuit 12 figures are rectangle, and long is D1, and wide is D4=100 μ m; turning corner is square, length of side D3=D1+D4=170 μ m.Fig. 1 is shown in by interface circuit schematic diagram.
Carry out the design of chip bonding pad according to following steps:
1, determine the pad sum of chip and the pad number on every limit: chip bonding pad comprises 4 of address signals, 16 of data outputs, power supply, totally 4,4 of other signals, final pad sum N is 28, carries out layout calculation by square, and the pad number on every limit is M1=N/4=7, see Fig. 2, determine the square length of side according to encapsulation process ability: can obtain chip length of side X1=M1 × (D1+D2)-D2+2D3=7 × (70+30)-30+2 × 170=1010 μ m.
2, determine basic encapsulated type: this chip has 28 pads and chip area 1.01mm × 1.01mm roughly, select DIP28, SOP28 as two kinds of encapsulated types.Be square through the tube chamber of looking into DIP28, the length of side is 6.4mm × 6.4mm, each 7 pads, totally 28 pads placed in every limit; The tube chamber of SOP28 is rectangle, is of a size of 6mm × 3mm, each 10 pads, totally 20 pads, each 4 pads, totally 8 pads, altogether 28 pads placed in cross direction both sides placed in length direction both sides.Basic encapsulated type can at will be selected, but considers that the tube chamber of DIP28 is square, and convenient is reasonable scheme by chip design quadrate, and therefore selecting DIP28 is basic encapsulated type, and the encapsulated type that SOP28 is other.
3, determine the position of chip bonding pad: basic encapsulated type DIP28 is carried out to pressure welding figure design, the pad number of determining the every limit of chip is 7, determine the square that is shaped as of chip, the length of side is about 1.01mm, be less than minimum lumen size 6mm × 3mm, by the connection diagram of actual size design chips pad and shell tube chamber lead frame, see Fig. 3 A, the reasonability of checking pad locations design, guarantees that chip bonding pad layout meets selected basic encapsulated type.
4, determine other encapsulated type: selected SOP28 shell is other encapsulated type and chip bonding pad layout, design pressure welding figure, as Fig. 3 B.If chip bonding pad meets the requirement of SOP28 shell, do not need to optimize pad locations, directly export the pressure welding figure of this type by step 6.But as seen from the figure, the size of chip length and width direction meets the size of SOP28 encapsulated type shell tube chamber length and width direction, but have overlap joint phenomenon at the pressure welding silk of the adjacent pad of chip corner, therefore must optimize pad locations by step 5 can pressure welding and do not produce overlap joint.
5, pad locations optimal design: the pad to chip corner is optimized design, understands the pad number and the position that have pressure welding problem by Fig. 3 B, take to increase, move methods such as having the pad locations of pressure welding problem and optimize pad design.
The method that increases pad is as follows: according to preliminary definite chip size, the maximum PAD point number that every limit can be placed in this size range is: N1=X1/ (D1+D2)=1010/100=10.1, calculate by 10 pads, each direction ratio originally had more 3 pads, consider reality, can design by two, every limit 1 pad being communicated with the esd protection circuit 12 of end of each increase, as the outside of the outermost pad 1 in every limit of chip is increased to 1 pad 1A, the outside of pad 7 increases by 1 pad 7A, each direction has more 2 pads, the total pad number of chip has more 8, totally 36, but chip size still remains unchanged, see Fig. 4.Carry out pressure welding figure design according to this chip bonding pad figure, on DIP28 encapsulation every limit of chips, can adopt pad 1 or pad 1A, pad 7 or pad 7A to carry out pressure welding, and in SOP28 encapsulation, must adopt pad 1A, pad 7A to carry out pressure welding (and pad 1, pad 7 leave unused), see Fig. 5, the design of this chip bonding pad meets the pressure welding of two kinds of encapsulated types, and chip area and pad order constant.
The method of mobile pad is as follows: based on the above method, in order further to simplify pad design, pad 1 and pad 7 can be moved to the position of pad 1A and pad 7A, or remove pad 1 and pad 7, with pad 1A and pad 7A replacement, the pad number of the each direction of chip is 7, total pad number is 28, see Fig. 6, carry out pressure welding figure design according to this chip bonding pad figure, in DIP28 and SOP28 encapsulation, adopt pad 1A, 7A carries out pressure welding, see Fig. 7 A and Fig. 7 B, this chip bonding pad design meets the pressure welding of two kinds of encapsulated types, and chip area and pad order are constant.
6, design final pressure welding figure: according to the chip bonding pad location drawing of final design, encapsulated type design pressure welding figure with the DIP28, the CSOP28 that adopt, the pressure welding silk that the size of confirming chip length and width direction meets between dimensional requirement and the pad of different encapsulated type shell tube chamber length and width directions does not produce overlap joint phenomenon, the pressure welding figure that exports different encapsulated types, pressure welding figure as shown in Figure 7.
Chip bonding pad layout designs after optimization, avoid same chip can not carry out different encapsulation and need to change the phenomenon of layout design, meet the requirements that same chip can adapt to different encapsulation, for chip package and chip application provide flexibility, reduced cost.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the technology of the present invention principle; can also make some improvement and distortion, these improvement and distortion also should be considered as protection scope of the present invention.
Claims (4)
1. adapt to the chip bonding pad layout design method that multiple different encapsulation requires, it is characterized in that, comprise the following steps:
Step 1, the pad sum of determining chip and the pad number on every limit: determine the pad sum N of chip, according to pad sum, determine the pad number on every limit and the size of chip length and width direction;
Step 2, determine basic encapsulated type: according to pad sum and chip area, select the lumen size that meets the demands and the multiple encapsulated type of tube chamber lead frame, and selected wherein a kind of encapsulated type is as basic encapsulated type;
Step 3, determine the position of chip bonding pad: according to selected basic encapsulated type, adjust pad number and the pad locations on the every limit of chip, make the size of chip length and width direction be less than respectively the size of the shell tube chamber length and width direction of this basic encapsulated type;
Step 4, determine other encapsulated type: according to the size of the pad number on definite every limit of chip and chip length and width direction, selected other encapsulated type carries out pressure welding figure design, if also all meet other encapsulated type, do not need to optimize pad locations, directly export the pressure welding figure of this type by step 6; If do not meet, optimize pad locations by step 5;
Step 5, optimization pad locations: do not increasing under the prerequisite of chip area, take the mobile optimal way that has the pad locations of pressure welding problem, increases around the corner the different pad of number of pads or different encapsulated type pressure welding, make pad meet different encapsulated type requirements;
Step 6, design final pressure welding figure: the pressure welding figure that is applicable to different encapsulated types according to the chip bonding pad position output of final confirmation.
2. the chip bonding pad layout design method that the multiple different encapsulation of adaptation according to claim 1 require, is characterized in that, in step 1, chip design is square, carries out layout calculation by square, and the pad number of determining the every limit of chip is N/4.
3. the chip bonding pad layout design methods that the multiple different encapsulation of adaptation according to claim 1 require, is characterized in that, in step 4, selected other encapsulated type carries out pressure welding figure while designing, considers respectively following factor:
Whether the size of chip length and width direction meets the size of other encapsulated type shell tube chamber length and width direction, whether the pressure welding silk of adjacent pad produces overlap joint phenomenon.
4. the chip bonding pad layout design method requiring according to the multiple different encapsulation of the adaptation described in claim 1 or 3, it is characterized in that, in step 6, according to the chip bonding pad position of final confirmation, the pressure welding silk that the size of confirming chip length and width direction meets between dimensional requirement and the pad of different encapsulated type shell tube chamber length and width directions does not produce after overlap joint phenomenon, exports the pressure welding figure of different encapsulated types.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109585442A (en) * | 2018-11-28 | 2019-04-05 | 武汉瑞纳捷电子技术有限公司 | A kind of high-power chip domain and its layout and packaging and routing optimization method |
| CN110085566A (en) * | 2019-04-30 | 2019-08-02 | 德淮半导体有限公司 | Semiconductor package part and semiconductor element |
| CN112183012A (en) * | 2020-09-15 | 2021-01-05 | 中国兵器工业集团第二一四研究所苏州研发中心 | Layout structure of front-end readout integrated circuit pixel unit of laser radar receiver |
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Effective date of registration: 20180815 Address after: 233030 2016 Tang He road, Bengbu, Anhui Patentee after: Huadong Photoelectric Integrated Device Research Institute Address before: 215163 No. 89 Longshan Road, hi tech Zone, Suzhou, Jiangsu Patentee before: China North Industries Group Corporation No.214 Research Institute Suzhou R&D Center |
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