CN110085566A - Semiconductor package part and semiconductor element - Google Patents
Semiconductor package part and semiconductor element Download PDFInfo
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- CN110085566A CN110085566A CN201910358118.4A CN201910358118A CN110085566A CN 110085566 A CN110085566 A CN 110085566A CN 201910358118 A CN201910358118 A CN 201910358118A CN 110085566 A CN110085566 A CN 110085566A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
This disclosure relates to a kind of semiconductor package part and semiconductor element.A kind of semiconductor package part includes: encapsulating housing, and encapsulating housing includes multiple pins；Multiple leads；Semiconductor element.Semiconductor element includes: die internal circuit, and the path of external connection is used for at least one；Multiple splice terminals include at least the first splice terminal and the second splice terminal；Terminal arrangement circuit, terminal arrangement circuit is for configuring the connection of one or more splice terminals in multiple splice terminals to the corresponding path for external connection of die internal circuit, wherein, terminal arrangement circuit is configured such that can connect corresponding pin to the same path for external connection of die internal circuit by one in the first splice terminal and the second splice terminal；Wherein, it connects the orthographic projection on a semiconductor die of a lead to corresponding pin in the first splice terminal and the second splice terminal and the target area of semiconductor element is not be overlapped.
Description
Technical field
This disclosure relates to technical field of semiconductors, it particularly relates to semiconductor package part and semiconductor element.
Background technique
Encapsulation technology can fix, semiconductor die, help to protect semiconductor element, improve its reliability, together
When be connected with other circuits convenient for semiconductor element.Different semiconductor packagings may use different packing forms, phase
It answers, there are different arrangement modes for pin.However, the arrangement mode of splice terminal is logical for semiconductor element
It is often fixed.Therefore, when using different packing forms encapsulate the semiconductor element when, in some cases splice terminal with
Positional relationship between pin may not be it is highly desirable, cause the lead being connected between splice terminal and pin longer, cross over
Range is larger.Especially in the case of semiconductor element receives or emits optical signal, this lead is easy to influence optical signal
Reception and transmitting.
Therefore there is the demand of the technology for improved semiconductor package part and semiconductor element.
Summary of the invention
According to one aspect of the disclosure, a kind of semiconductor package part is provided, comprising: encapsulating housing, the encapsulating shell
Body includes multiple pins；Multiple leads；Semiconductor element, the semiconductor element is set in the encapsulating housing, described partly to lead
Body tube core includes: die internal circuit, and the path of external connection is used for at least one；Multiple splice terminals, for distinguishing
It is connected to corresponding pin by corresponding lead, the multiple splice terminal includes at least the first splice terminal and the second engagement
Terminal；Terminal arrangement circuit, the terminal arrangement circuit are used to configure one or more engagements in the multiple splice terminal
Connection of the terminal to the corresponding path for external connection of the die internal circuit, wherein the terminal arrangement circuit
Corresponding draw can be connected by one in first splice terminal and second splice terminal by being configured such that
Foot is to the same path for external connection of the die internal circuit；Wherein, first splice terminal and described is connected
Orthographic projection of one lead to the corresponding pin on the semiconductor element in second splice terminal with it is described
The target area of semiconductor element is not overlapped.
In some embodiments, first splice terminal is located at the first side of the semiconductor element, and described second connects
Close second side different from the first side that terminal is located at the semiconductor element；Pin corresponding with first splice terminal and
Pin corresponding with second splice terminal is located at the encapsulating housing with the semiconductor element the first side phase
The first adjacent side and second side adjacent with second side of the semiconductor element.
In some embodiments, the semiconductor element further include: multiple buffer circuits are connected to the terminal and match
Between circuits and corresponding splice terminal.
In some embodiments, the multiple buffer circuit is arranged in a one-to-one correspondence with the multiple splice terminal.
In some embodiments, the terminal arrangement circuit and the buffer circuit are in the target area of the semiconductor element
Except domain.
In some embodiments, the terminal arrangement circuit includes: at least one programmable electric fuse, is connected to institute
State at least one for external connection path and one or more of splice terminals between and programmed circuit, be used for root
At least one described programmable electric fuse is programmed according to command information so that the programmable electric fuse is connected or fusing,
With control it is described at least one for being connected between the path and one or more of splice terminals of external connection.
In some embodiments, the terminal arrangement circuit includes: at least one switch, is configured for being believed according to instruction
On or off is ceased, to control at least one described path for external connection and one or more of splice terminals respectively
Between connect.
In some embodiments, wherein the target area is display area or imaging region, wherein the multiple to draw
Line is arranged to not span across the display area or imaging region.
In some embodiments, at least one of first splice terminal and the second splice terminal are virtual terminals,
One or more of splice terminals include the virtual terminal.
On one side according to the disclosure, a kind of semiconductor element is additionally provided, comprising: die internal circuit has at least
One is used for the path of external connection；Multiple splice terminals, for being connected to corresponding pin, institute by corresponding lead respectively
Multiple splice terminals are stated including at least the first splice terminal and the second splice terminal；Terminal arrangement circuit, the terminal arrangement electricity
The corresponding use that road is used to configure one or more splice terminals in the multiple splice terminal to the die internal circuit
Connection in the path of external connection, wherein the terminal arrangement circuit, which is configured such that, to be engaged by described first
The corresponding pin of a connection in terminal and second splice terminal is used for externally to the same of the die internal circuit
The path of connection；Wherein, first splice terminal is located at the first side of the semiconductor element, second splice terminal position
In second side different from the first side of the semiconductor element.
In some embodiments, the semiconductor element further include: multiple buffer circuits are connected to the terminal and match
Between circuits and corresponding splice terminal.
In some embodiments, the multiple buffer circuit is arranged in a one-to-one correspondence with the multiple splice terminal.
In some embodiments, the terminal arrangement circuit and the buffer circuit are in the target area of the semiconductor element
Except domain.
In some embodiments, the terminal arrangement circuit includes: at least one programmable electric fuse, is connected to institute
State at least one for external connection path and one or more of splice terminals between and programmed circuit, be used for root
At least one described programmable electric fuse is programmed according to command information so that the programmable electric fuse is connected or fusing,
With control it is described at least one for being connected between the path and one or more of splice terminals of external connection.
In some embodiments, the terminal arrangement circuit includes: at least one switch, is configured for being believed according to instruction
On or off is ceased, to control at least one described path for external connection and one or more of splice terminals respectively
Between connect.
In some embodiments, the semiconductor element includes imaging sensor, wherein connection first splice terminal
With orthographic projection of one lead to the corresponding pin on the semiconductor element in second splice terminal
It is not be overlapped with the imaging region of described image sensor.
In some embodiments, at least one of first splice terminal and the second splice terminal are virtual terminals,
One or more of splice terminals include the virtual terminal.
By the detailed description referring to the drawings to the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become more apparent from.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and together with the description for solving
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Fig. 1 shows the structural schematic diagram of semiconductor packaging part；
Fig. 2 shows the structural schematic diagrams of another semiconductor package part；
Fig. 3 shows the structural schematic diagram of the semiconductor package part according to one exemplary embodiment of the disclosure.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below
It indicates same section or part with the same function, and omits its repeated explanation.In some cases, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, the disclosure is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the disclosure
And its application or any restrictions used.That is, structure and method herein is to show in an exemplary fashion, for
The different embodiments of structures and methods in the bright disclosure.It will be understood by those skilled in the art, however, that they be merely illustrative can
Exemplary approach with the disclosure for being used to implement, rather than mode exhausted.In addition, attached drawing is not necessarily drawn to scale, it is some
Feature may be amplified to show the details of specific component.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
In general, the demand of being directed to, IC designer can distribute requirement, packing forms etc. according to the pin (pin) of client, in conjunction with setting
Meter situation rationally designs the position of the terminal (such as pad (Pad)) of IC and the position of pin.However, this will lead to it is designed
IC throws into question in the encapsulation for being transformed into other forms, causes the scope of application of product limited.
Fig. 1 shows the structural schematic diagram of semiconductor packaging part.As shown in Figure 1, in semiconductor package part 100 ', half
Conductor tube core 110 ' is arranged in encapsulating housing 120 '.In semiconductor package part 100 ' shown in Fig. 1, semiconductor element 110 '
Splice terminal 112 ' (P1~P30) be distributed in its left and right sides.The pin 121 ' (L1~L30) of encapsulating housing 120 ' is also distributed
At left and right sides of it.
There are target areas 113 ' in semiconductor element 110 '.The target area 113 ' can be for example corresponding to optical signal
The region ((photosensitive) region or display area accordingly, is also referred to as imaged) for receiving window and/or launch window；It is also possible to
Other types of region.In semiconductor package part 100 ', if lead 130 ' across target area 113 ', can be to transistor
The operation of core 110 ' interferes, such as will cause and cannot carry out optical detection, etc. to target area.This is undesirable.
Encapsulating structure shown in FIG. 1 can be such as tool for dual in-line packing forms.The setting of the splice terminal of tube core can be with
It needs to be configured based on tool for dual in-line encapsulation.As shown, the position of splice terminal 112 ' and pin 121 ' corresponds to each other, because
This can be connected on semiconductor element 110 ' to encapsulating housing 120 ' by lead 130 '.And the length of lead 130 ' itself compared with
Short, distribution is compact, does not pass through target area 113 ', has ensured proper testing or the operation of semiconductor element 110 '.
However, will cause problem when IC shown in Fig. 1 to be applied to the encapsulation of other forms.Fig. 2 shows the other half to lead
The structural schematic diagram of body packaging part.Clear and concise for diagram, pin is shown as line segment with being simplified in Fig. 2.It is inciting somebody to action
Semiconductor element 110 ' shown in FIG. 1 is applied to packing forms shown in Fig. 2 (for example, plastic leaded chip carrier
(Plastic Leaded Chip Carrier, PLCC), quad flat pack (Plastic Quad Flat Package,
QFP) or whens plastic flat quad package (Plastic Quad Flat Package, PQFP) etc., due to encapsulating housing 120 '
Part pin 121 ' be located at upper and lower two sides, then the splice terminal 112 ' of the left and right sides that part is located at semiconductor element 110 ' can
It can need to be connected with the pin 121 ' for being located at about 120 ' two sides of encapsulating housing.In this case, as shown in Fig. 2, part is drawn
Line 130 ' will interfere the test or operation of semiconductor element 110 ' across target area 113 '.For example, working as target area 113 '
When window corresponding to the reception optical signal of semiconductor element 110 ', the presence of lead 130 ' will will lead to portions incident to partly leading
The light loss of body tube core 110 ' causes not can be carried out optic test or device cisco unity malfunction.
Fig. 3 is the structural schematic diagram according to the semiconductor package part 100 of an exemplary embodiment of the disclosure.The semiconductor
Packaging part 100 includes encapsulating housing 120, multiple leads 130 and semiconductor element 110.
Encapsulating housing 120 includes multiple pins 121.With the difference of packing forms, pin 121 is in encapsulating housing 120
Arrangement mode may also be different.In Fig. 3, the technical solution of the disclosure will be elaborated by taking PLCC as an example；It is understood that
It is that the spirit and main idea of the disclosure easily can be applied to it according to the introduction of the disclosure by those skilled in the art
Its packing forms.As shown in figure 3, pin 121 (L1~L32) is substantially uniformly distributed in encapsulating housing in PLCC encapsulation
120 surrounding.Certainly, the present disclosure is not limited thereto, in some other embodiment, pin 121 can also according to application need or
Person's industry standard arrangement.
Semiconductor element 110 is arranged in encapsulating housing 120.In one embodiment, tube core 110 can be attached to envelope
The tube core mounting portion (such as paddle board (paddle)) of shell 120 is filled, and coats die perimeter with materials such as resins.
Semiconductor element 110 may include die internal circuit 111.Die internal circuit 111 can have at least one
Path (also referred to as external connection path) 301 for external connection.The path 301 for external connection can be by right
The splice terminal 112 (for example, PAD) answered is connected to outside, to receive power supply, input/output signal etc..It is described to be used for externally
The path of connection can include but is not limited to node or route etc..Although clear for diagram, one is illustrated only in Fig. 3
A external connection path 301, it should be appreciated that die internal circuit 111 can have multiple external connection paths.
Splice terminal 112 can be connected to corresponding pin 121 by corresponding lead 130 respectively.The splice terminal
112 may include the first splice terminal 112a and the second splice terminal 112b.Note that in the fig. 3 embodiment, compared to Fig. 2
30 terminals, increase two terminals.The two increased terminals can be illusory (dummy) terminal.First splice terminal
At least one of 112a and the second splice terminal 112b can be virtual terminal.In some implementations, virtual terminal can
To be not directly connected to the path for external connection of tube core, such as can be by the terminal arrangement circuit that is described below
It is connected to the corresponding path for external connection.In the implementation of substitution, virtual terminal can be redundant terminals, can
It is configured with same as objective terminal, to be connected to corresponding external connection path with objective terminal substantially similar way.For example,
Redundant terminals and corresponding objective terminal can be all by the terminal arrangement circuit connection that is described below to corresponding external
Connection path.
The semiconductor element further includes terminal arrangement circuit 114.Terminal arrangement circuit 114 can be configured for selecting
Connect the splice terminal that die internal circuit 111 arrives pin 121.Terminal arrangement circuit can be used for configuring the multiple abutting end
The connection of one or more splice terminals in son to the corresponding path for external connection of the die internal circuit.Example
Such as, terminal arrangement circuit can be used for configuring one or more of the first splice terminal 112a and the second splice terminal 112b
(if necessary) to the connection in the corresponding path for external connection of the die internal circuit.In some embodiments
In, the terminal arrangement circuit is configured such that can be by configuring the first splice terminal 112a and the second splice terminal 112b
In one connect corresponding pin to the same path 301 for external connection of the die internal circuit.In this way, can
So that by the first splice terminal 112a and passing through the second splice terminal 112b and the external connection of die internal circuit 111
Electrical connection between path 301 is substantially equivalent.
In example as shown in Figure 3, terminal arrangement circuit 114 is configured such that the external connection path 301 of tube core is logical
Terminal 112a is crossed (without by terminal 112b) connection pin L22.At this point, terminal 112b is not connected to corresponding pin L27.
In this way, connecting one (112a) in first splice terminal and second splice terminal to described right
Answer orthographic projection of the lead of pin on the semiconductor element and the target area of the semiconductor element not be overlapped.And if
By terminal 112b connection pin L22, will cause lead across and block the objective function region 113 of tube core 111.Such as
This, in accordance with an embodiment of the present disclosure, can to avoid lead across and block the objective function region 113 of tube core 111.And it can increase
Add the flexibility ratio of meter and the application range of product.
In a specific example, as shown in figure 3, the first splice terminal 112a can be located at the first of semiconductor element 110
Side, the second splice terminal 112b can be located at second side different from the first side of semiconductor element 110.Meanwhile with terminal
The corresponding pin 121 (L1) of 112a is located at first side adjacent with the first side of semiconductor element 110 of encapsulating housing 120.Figure
In pin L22 and the first splice terminal 112a be correspondingly arranged, by terminal arrangement circuit 114 selection facilitate lead 130 connect
The first splice terminal 112a.To realize the transmission of the signal between semiconductor element 110 and external circuit, and avoid lead
130 interfere across 113 bring of target area.
The lead 130 connected between the first splice terminal 112a and pin L22 is shorter, so as to increase the stabilization of lead
Property, reduce lead vibration, improves the reliability and yields of product.In some embodiments of the present application, end can be passed through
Sub- configuration circuit 114 disconnects the connection between the second splice terminal 112b and the path 301 of die internal circuit 110.However, this
It is open to be not limited to this.It in some cases, can also be by both terminal 112a and 112b come respectively from different pin L22
Power supply or signal are received with L27.Pin L27 can be set in the adjacent in that side of tube core with terminal 112b of encapsulating housing
Side.Certainly the present disclosure is not limited to as long as lead does not block objective function region 113.
As shown in figure 3, semiconductor element 110 can also include buffer circuit 115.Buffer circuit 115 is connected to terminal and matches
Between circuits and corresponding splice terminal 112.The form of buffer circuit 115 can be multiplicity, can be using in this field
Known or exploitation in the future technology, therefore it is omitted here detailed description thereof.As unrestricted example, buffering
Circuit can include but is not limited to such as output stage, the phase inverter, etc. of antiparallel setting.
In some embodiments, buffer circuit 115 can also be arranged in a one-to-one correspondence with splice terminal 112.For example, each connect
It closes terminal 112 and there is its corresponding buffer circuit 115, to ensure the normal operation of each 112 place branch of splice terminal.
In order to avoid interfering to target area 113, terminal arrangement circuit 114 and buffer circuit 115 be can be set
Except the target area 113 of semiconductor element 110.
In some embodiments of the present disclosure, terminal arrangement circuit 114 can specifically include at least one programmable electric smelting
Silk or programmable electric fuse array (not shown).Programmable electric fuse can connect in die internal circuit 111 (for example, its is right
Outer connection path 301) and corresponding splice terminal 112 (for example, 112A) between, with control die internal circuit 111 and engagement
Being turned on or off between terminal 112.In a specific example, programmable electric fuse can directly be connected in series in die internal
Between the external connection path and corresponding splice terminal 112 of circuit 111.By the way that undesirable splice terminal 112 will be connected to
The programmable electric fuse of place branch road fuses, and disconnects external connection path and the splice terminal 112 of die internal circuit
Connection, to connect the external connection path by desired joint terminal to pin.
The terminal arrangement circuit further includes programmed circuit, is used for according to command information at least one described programmable electricity
Fuse is programmed so that programmable electric fuse conducting or fusing, with control it is described at least one for external connection
It is connected between path and one or more of splice terminals.
In other embodiments of the disclosure, terminal arrangement circuit 114 may include at least one switch, be configured to use
According to command information on or off, with control respectively it is described at least one for external connection path and it is one or
It is connected between multiple splice terminals.
For example, terminal arrangement circuit 114 may include path selecting circuit system, it may include that one or more is opened
Close, with control it is described at least one for being connected between the path and one or more of splice terminals of external connection.Path
Selection circuit system can select path according to command information.Path selecting circuit system may include such as multi-path choice
Device.Multiple selector can select needed for it one to be exported from multiple inputs.In one example, a multichannel
Multiple input terminals of selector circuit are connected to the first splice terminal and second splice terminal in one group of splice terminal etc.,
And the output end of the multiple selector circuit is connected to die internal circuit.In another example, path selecting circuit system can
To input the external connection path for being connected to die internal circuit with one, but there are multiple selectable outputs.
Passage path selection circuit system selects the required splice terminal to be connected with die internal circuit, to make tube core
Internal circuit is connected on pin by suitable splice terminal, the interference to avoid lead to target area.
Here, command information can store in the register in tube core or in terminal arrangement circuit；Alternatively, can lead to
Pin is crossed to receive from outside.
In accordance with an embodiment of the present disclosure, such as when semiconductor element shown in Fig. 3 is applied to packaging body shown in Fig. 2,
It (can not have to pass through terminals P 8) connection pin L8 by terminal 112a, and equally realize the function of tube core.Similar, may be used also
(not have to pass through terminals P 10) connection pin L10 by another terminal 112a, and equally realize the function of tube core.In this way, root
According to embodiment of the disclosure, can to avoid lead across and block the objective function region of tube core.And the spirit of design can be increased
The application range of activity and product.
So far, it is to be understood that the disclosure is contemplated that a kind of semiconductor element comprising: die internal circuit has extremely
Few one is used for the path of external connection；Multiple splice terminals, for being connected to corresponding pin by corresponding lead respectively,
The multiple splice terminal includes at least the first splice terminal and the second splice terminal；Terminal arrangement circuit, the terminal arrangement
Circuit is used to configure one or more splice terminals in the multiple splice terminal to the corresponding of the die internal circuit
The connection in the path for external connection, wherein the terminal arrangement circuit, which is configured such that, to be connect by described first
The corresponding pin of a connection in terminal and second splice terminal is closed to be used for pair to the same of the die internal circuit
The path of outer connection；Wherein, first splice terminal is located at the first side of the semiconductor element, second splice terminal
Positioned at second side different from the first side of the semiconductor element.
In some embodiments, the semiconductor element further include: multiple buffer circuits are connected to the terminal and match
Between circuits and corresponding splice terminal.
In some embodiments, the multiple buffer circuit is arranged in a one-to-one correspondence with the multiple splice terminal.
In some embodiments, the terminal arrangement circuit and the buffer circuit are in the target area of the semiconductor element
Except domain.
In some embodiments, the terminal arrangement circuit includes: at least one programmable electric fuse, is connected to institute
State at least one for external connection path and one or more of splice terminals between and programmed circuit, be used for root
At least one described programmable electric fuse is programmed according to command information so that the programmable electric fuse is connected or fusing,
With control it is described at least one for being connected between the path and one or more of splice terminals of external connection.
In some embodiments, the terminal arrangement circuit includes: at least one switch, is configured for being believed according to instruction
On or off is ceased, to control at least one described path for external connection and one or more of splice terminals respectively
Between connect.
In some embodiments, the semiconductor element includes imaging sensor, wherein connection first splice terminal
With orthographic projection of one lead to the corresponding pin on the semiconductor element in second splice terminal
It is not be overlapped with the imaging region of described image sensor.
In some embodiments, at least one of first splice terminal and the second splice terminal are virtual terminals,
One or more of splice terminals include the virtual terminal.
The semiconductor element may include imaging sensor.The imaging sensor may include in the multiple of array setting
Photoelectric sensor, multiple photoelectric sensors are respectively positioned in the target area of imaging sensor.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can in this institute
It is operated in those of description show or other other different orientations of orientation.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
It is preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technique, summary of the invention or specific embodiment
Given in go out theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
In addition, the description of front may be referred to and be " connected " or " coupling " element together or node or feature.Such as
It is used herein, unless explicitly stated otherwise, " connection " mean an element/node/feature and another element/node/
Feature is being directly connected (or direct communication) electrically, mechanically, in logic or in other ways.Similarly, unless separately
It clearly states outside, " coupling " means that an element/node/feature can be with another element/node/feature with direct or indirect
Mode link mechanically, electrically, in logic or in other ways to allow to interact, even if the two features may
It is not directly connected to be also such.That is, " coupling " is intended to encompass the direct connection and indirectly of element or other feature
Connection, including the use of the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can with the similar terms such as " first " used herein, " second ", and
And it thus is not intended to limit.For example, unless clearly indicated by the context, be otherwise related to structure or element word " first ", "
Two " do not imply order or sequence with other such digital words.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
It can be combined into single operation, single operation can be distributed in additional operation, and operating can at least portion in time
Divide and overlappingly executes.Moreover, alternative embodiment may include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of semiconductor package part characterized by comprising
Encapsulating housing, the encapsulating housing include multiple pins；
Multiple leads；
Semiconductor element, the semiconductor element are set in the encapsulating housing, and the semiconductor element includes:
Die internal circuit is used for the path of external connection at least one；
Multiple splice terminals, for being connected to corresponding pin by corresponding lead respectively, the multiple splice terminal is at least
Including the first splice terminal and the second splice terminal；
Terminal arrangement circuit, the terminal arrangement circuit are used to configure one or more abutting ends in the multiple splice terminal
Son arrives the connection in the corresponding path for external connection of the die internal circuit,
Wherein, be configured such that can be by first splice terminal and second abutting end for the terminal arrangement circuit
One in son connects corresponding pin to the same path for external connection of the die internal circuit；
Wherein, one drawing to the corresponding pin in first splice terminal and second splice terminal is connected
Orthographic projection of the line on the semiconductor element and the target area of the semiconductor element be not be overlapped.
2. semiconductor package part according to claim 1, which is characterized in that first splice terminal is partly led positioned at described
First side of body tube core, second splice terminal are located at second side different from the first side of the semiconductor element；
And the corresponding pin of the first splice terminal and pin corresponding with second splice terminal are located at the envelope
Fill first side adjacent with the first side of the semiconductor element of shell and adjacent with second side of the semiconductor element
Second side.
3. semiconductor package part according to claim 1, which is characterized in that the semiconductor element further include:
Multiple buffer circuits are connected between the terminal arrangement circuit and corresponding splice terminal.
4. semiconductor package part according to claim 3, which is characterized in that the multiple buffer circuit connects with the multiple
Terminal is closed to be arranged in a one-to-one correspondence.
5. semiconductor package part according to claim 3, which is characterized in that the terminal arrangement circuit and buffering electricity
Road is except the target area of the semiconductor element.
6. semiconductor package part according to any one of claim 1 to 5, which is characterized in that the terminal arrangement circuit
Include:
At least one programmable electric fuse, be connected to it is described at least one for external connection path and it is one or
Between multiple splice terminals, and
Programmed circuit, for being programmed at least one described programmable electric fuse so that described compile according to command information
The conducting of journey electric fuse or fusing, to control at least one described path for external connection and one or more of abutting ends
It is connected between son.
7. semiconductor package part according to any one of claim 1 to 5, which is characterized in that the terminal arrangement circuit
Include:
At least one switch, is configured for according to command information on or off, with control respectively it is described at least one be used for
It is connected between the path of external connection and one or more of splice terminals.
8. semiconductor package part according to any one of claim 1 to 5, which is characterized in that
Wherein, the target area is display area or imaging region,
Wherein, the multiple lead is arranged to not span across the display area or imaging region.
9. semiconductor package part according to any one of claim 1 to 5, which is characterized in that
At least one of first splice terminal and the second splice terminal are virtual terminals, one or more of abutting ends
Attached bag includes the virtual terminal.
10. a kind of semiconductor element characterized by comprising
Die internal circuit is used for the path of external connection at least one；
Multiple splice terminals, for being connected to corresponding pin by corresponding lead respectively, the multiple splice terminal is at least
Including the first splice terminal and the second splice terminal；
Terminal arrangement circuit, the terminal arrangement circuit are used to configure one or more abutting ends in the multiple splice terminal
Son arrives the connection in the corresponding path for external connection of the die internal circuit,
Wherein, be configured such that can be by first splice terminal and second abutting end for the terminal arrangement circuit
One in son connects corresponding pin to the same path for external connection of the die internal circuit；
Wherein, first splice terminal is located at the first side of the semiconductor element, and second splice terminal is located at described
Second side different from the first side of semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910358118.4A CN110085566A (en) | 2019-04-30 | 2019-04-30 | Semiconductor package part and semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910358118.4A CN110085566A (en) | 2019-04-30 | 2019-04-30 | Semiconductor package part and semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110085566A true CN110085566A (en) | 2019-08-02 |
Family
ID=67417858
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910358118.4A Pending CN110085566A (en) | 2019-04-30 | 2019-04-30 | Semiconductor package part and semiconductor element |
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| CN (1) | CN110085566A (en) |
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| CN1525561A (en) * | 2003-08-29 | 2004-09-01 | 北京中星微电子有限公司 | Chip having input and output terminal configurable function and method thereof |
| CN101083250A (en) * | 2006-06-01 | 2007-12-05 | 恩益禧电子股份有限公司 | Semiconductor device cutting fusing wire and method |
| CN101442050A (en) * | 2007-11-23 | 2009-05-27 | 瑞昱半导体股份有限公司 | Integrated circuit suitable for various encapsulation modes |
| US20100127366A1 (en) * | 2008-11-27 | 2010-05-27 | Upek, Inc. | Integrated Leadframe And Bezel Structure And Device Formed From Same |
| CN103903996A (en) * | 2014-04-14 | 2014-07-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Chip bonding pad layout design method suitable for multiple different encapsulation requirements |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1525561A (en) * | 2003-08-29 | 2004-09-01 | 北京中星微电子有限公司 | Chip having input and output terminal configurable function and method thereof |
| CN101083250A (en) * | 2006-06-01 | 2007-12-05 | 恩益禧电子股份有限公司 | Semiconductor device cutting fusing wire and method |
| CN101442050A (en) * | 2007-11-23 | 2009-05-27 | 瑞昱半导体股份有限公司 | Integrated circuit suitable for various encapsulation modes |
| US20100127366A1 (en) * | 2008-11-27 | 2010-05-27 | Upek, Inc. | Integrated Leadframe And Bezel Structure And Device Formed From Same |
| CN103903996A (en) * | 2014-04-14 | 2014-07-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Chip bonding pad layout design method suitable for multiple different encapsulation requirements |
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