CN112183012B - Laser radar receiver front end readout integrated circuit pixel unit layout structure - Google Patents
Laser radar receiver front end readout integrated circuit pixel unit layout structure Download PDFInfo
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- CN112183012B CN112183012B CN202010965679.3A CN202010965679A CN112183012B CN 112183012 B CN112183012 B CN 112183012B CN 202010965679 A CN202010965679 A CN 202010965679A CN 112183012 B CN112183012 B CN 112183012B
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- 239000002184 metal Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 230000002411 adverse Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02A—TECHNOLOGIES FOR ADAPTATION TO CLIMATE CHANGE
- Y02A90/00—Technologies having an indirect contribution to adaptation to climate change
- Y02A90/10—Information and communication technologies [ICT] supporting adaptation to climate change, e.g. for weather forecasting or climate simulation
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- Optical Radar Systems And Details Thereof (AREA)
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Abstract
The invention discloses a laser radar receiver front end reading integrated circuit pixel unit layout structure, wherein a first layout area is connected with a second layout area, the second layout area is connected with a third layout area, and the third layout area is connected with a fourth layout area and a fifth layout area; the first plate region is an In column interconnection plate region; the second version of the region is a trans-impedance amplifier version of the region; the third edition of region is a time sequence control circuit edition of region; the fourth edition of drawing area is a row selection bus wiring edition of drawing area; the fifth version of the field is the input line drive version of the field. The invention can complete the layout design of all pixel units in a limited area, optimize the area and reduce the cost of the chip; the column interconnection area, the analog circuit module and the digital circuit module are effectively isolated, the adverse effects on the clock and the wiring of the power supply of the array circuit are considered due to RC parasitic effect and uneven process processing, and the consistency and the anti-interference capability of the pixel unit circuit are improved.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a chip layout structure, and particularly relates to a pixel unit layout structure of a laser radar receiver front end readout integrated circuit.
Background
In the fields of aerospace, shipbuilding, rail transit, high-end manufacturing, and the like, lidar is widely used for target tracking and positioning. The laser radar mainly comprises a laser transmitter, a receiver, a signal processing module and a display, wherein the receiver is one of core components of the laser radar, and the receiver system structure comprises a photodiode and a front-end reading circuit pixel unit array. Along with the continuous expansion of the array scale, RC parasitic effect and uneven process processing bring adverse effects to the clock and the wiring of the power supply of the array circuit, so that the design difficulty of the pixel unit layout of the read-out processing circuit matched with the array is increased.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, designs the proper position of a detector and the influence interference of the parasitic capacitance on the detector signal by considering the capacitance parasitic effect of an interconnection In column In the pixel unit layout, and lays out and routes the positions of an In column interconnection, a transimpedance amplifier and a digital processing circuit, thereby providing a pixel unit layout structure of a laser radar receiver front end readout integrated circuit.
In order to solve the technical problems, the invention adopts the following technical scheme:
a layout structure of a pixel unit of a front-end readout integrated circuit of a laser radar receiver,
the system comprises a first edition region, a second edition region, a third edition region, a fourth edition region and a fifth edition region, wherein the first edition region is connected with the second edition region, the second edition region is connected with the third edition region, and the third edition region is connected with the fourth edition region and the fifth edition region;
the first plate region is an In column interconnection plate region;
the second version of the region is a trans-impedance amplifier version of the region, and is powered by an independent analog power supply and an analog ground;
the third edition of drawing area is a time sequence control circuit board drawing area, which comprises a digital logic control circuit board drawing area, and adopts an independent digital power supply and digital power supply;
the fourth edition of drawing area is a line selection bus wiring edition of drawing area, and metal intervals of different layers are adopted for parallel wiring;
the fifth edition of image area is the input line driving edition of image area, which adopts independent digital power supply and digital power supply to generate line selection bus, and the redundant wiring is added to make the signal lines equal in length.
Further, a substrate isolation ring is added in the first layout area for isolation.
Further, a preset distance of 3-10 μm is provided between the first plate region and the substrate spacer ring.
Further, the first layout area and the second layout area are provided with a preset distance of 3-5 μm.
Further, a substrate isolation ring is added in the second layout area for isolation.
Further, the second plate region and the third plate region have a preset distance of 5 μm to 10 μm.
Further, the second edition of region is arranged adjacent to the first edition of region; the third edition of region is arranged adjacent to the second edition of region; the fourth edition of region is arranged adjacent to the third edition of region; the fifth layout area is arranged adjacent to the fourth layout area.
Further, the first edition region and the third edition region are respectively arranged at two adjacent sides of the second edition region; the second layout area and the fourth layout area are respectively arranged at two opposite sides of the third layout area; the third layout area and the fifth layout area are respectively arranged on two opposite sides of the fourth layout area.
The invention has the beneficial effects that:
the layout structure can complete the layout design of all pixel units in a limited and specified area, the layout of each layout area is reasonable and compact, the area is optimized, and the cost of a chip is reduced; meanwhile, the In column interconnection area, the analog circuit module and the digital circuit module are effectively isolated, the adverse effects on the clock and the wiring of the power supply of the array circuit are considered due to RC parasitic effect and uneven process processing, and the consistency and the anti-interference capability of the pixel unit circuit are improved.
Drawings
FIG. 1 is a schematic diagram of a front-end readout integrated circuit pixel cell layout of a lidar receiver embodying the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
Referring to fig. 1, a schematic diagram of a layout structure of a pixel unit of a front-end readout integrated circuit of a lidar receiver according to an embodiment of the present invention is shown. In this embodiment, the pixel unit layout area is 100 μm and 100 μm, the array scale is 64×64, and a 0.18 μm and 6 layer metal process is adopted. The layout structure comprises a first edition area 10, a second edition area 20, a third edition area 30, a fourth edition area 40 and a fifth edition area 50. Wherein first plate region 10 is connected to second plate region 20, second plate region 20 is connected to third plate region 30, third plate region 30 is connected to fourth plate region 40 and fifth plate region 50.
The first plate region 10 is positioned In the right side area below the chip and is an In column interconnection plate region, a top metal layer and a passivation layer are adopted to design 25 μm by 25 μm, a substrate isolating ring is added for isolation, a preset distance of 3 μm-10 μm is arranged between the first plate region and the isolating ring, and a preset distance of 3 μm-5 μm is arranged between the second plate region 20; the second plate region 20 is positioned in the left area below the chip, is a transimpedance amplifier plate region, adopts an independent analog power supply and analog ground power supply, adopts M3-M6 multilayer metal walking wires, has the metal width of 3-5 μm, is isolated by adding a substrate isolating ring, and has a preset distance of 5-10 μm from the third plate region 30; the third plate region 30 is positioned in the middle region of the chip and is a time sequence control circuit plate region, and comprises a digital logic control circuit plate region, and is designed by using standard units, adopts an independent digital power supply and digital power supply, adopts M1, M5-M6 multilayer metal walking wires, and has the width of 1.5-2 mu M; the fourth plate region 40 is located in the middle upper region of the chip, and selects bus wiring plate regions for rows, wherein different odd metal layers are used for spacing the wires in the horizontal direction, such as M3, M5, M3 and M5, and different even metal layers are used for spacing the wires in the vertical direction, such as M2, M4, M2 and M4, so that interference and parasitic capacitance between buses are reduced; the fifth version of the region 50 is located at the top of the chip, and is a single digital power supply and digital power supply for the input row driving version of the region, so that a row selection bus is generated, redundant wires are added, signal wires are equal in length, and consistency of the pixel array is improved. The designed pixel unit layout passes the DRC inspection, and the left and right edges of the pixel unit array are processed in consideration of the splicing of the pixel unit array, so that the pixel unit layout can be directly spliced into an array to meet the DRC requirement.
The invention is not limited to the embodiments discussed above, and the above description of specific embodiments is intended to describe and illustrate the technical solutions to which the invention relates. Obvious variations or substitutions based on the teachings of the present invention should also be considered to fall within the scope of the present invention; the above description is provided to disclose a best mode for practicing the invention, so as to enable any person skilled in the art to utilize the invention in various embodiments and with various alternatives.
Claims (6)
1. A layout structure of a pixel unit of a laser radar receiver front end readout integrated circuit is characterized in that,
the system comprises a first edition region, a second edition region, a third edition region, a fourth edition region and a fifth edition region, wherein the first edition region is connected with the second edition region, the second edition region is connected with the third edition region, and the third edition region is connected with the fourth edition region and the fifth edition region;
the first plate region is an In column interconnection plate region;
the second version of the region is a trans-impedance amplifier version of the region, and is powered by an independent analog power supply and an analog ground;
the third edition of drawing area is a time sequence control circuit board drawing area, which comprises a digital logic control circuit board drawing area, and adopts an independent digital power supply and digital power supply;
the fourth edition of drawing area is a line selection bus wiring edition of drawing area, and metal intervals of different layers are adopted for parallel wiring;
the fifth edition of drawing area is an input row driving edition of drawing area, an independent digital power supply and digital ground power supply are adopted to generate a row selection bus, and the signal lines are equal in length by adding redundant wiring;
wherein the second edition region is arranged adjacent to the first edition region; the third edition of region is arranged adjacent to the second edition of region; the fourth edition of region is arranged adjacent to the third edition of region; the fifth edition of region is arranged adjacent to the fourth edition of region;
the first layout area and the third layout area are respectively arranged on two adjacent sides of the second layout area; the second layout area and the fourth layout area are respectively arranged at two opposite sides of the third layout area; the third layout area and the fifth layout area are respectively arranged on two opposite sides of the fourth layout area.
2. The lidar receiver front-end readout integrated circuit pixel cell layout structure of claim 1, wherein the first layout region is isolated from the second layout region by adding a substrate isolation ring.
3. The laser radar receiver front-end readout integrated circuit pixel unit layout structure according to claim 2, wherein a preset distance of 3 μm-10 μm is arranged between the first pattern region and the substrate isolating ring.
4. The laser radar receiver front-end readout integrated circuit pixel unit layout structure according to claim 1, wherein the first layout region and the second layout region are provided with a preset distance of 3 μm-5 μm.
5. The lidar receiver front-end readout integrated circuit pixel cell layout structure of claim 1, wherein the second layout region is isolated from the third layout region by adding a substrate isolation ring.
6. The laser radar receiver front-end readout integrated circuit pixel unit layout structure according to claim 1, wherein the second pattern area and the third pattern area have a preset distance of 5 μm to 10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010965679.3A CN112183012B (en) | 2020-09-15 | 2020-09-15 | Laser radar receiver front end readout integrated circuit pixel unit layout structure |
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| CN202010965679.3A CN112183012B (en) | 2020-09-15 | 2020-09-15 | Laser radar receiver front end readout integrated circuit pixel unit layout structure |
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| CN112183012A CN112183012A (en) | 2021-01-05 |
| CN112183012B true CN112183012B (en) | 2023-11-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114152929A (en) * | 2021-10-15 | 2022-03-08 | 探维科技(北京)有限公司 | Laser transmitter, laser radar and method for determining characteristic information |
| CN116050015A (en) * | 2023-01-28 | 2023-05-02 | 西南应用磁学研究所(中国电子科技集团公司第九研究所) | Automatic modeling and layout checking method for multi-layer chip device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103268380A (en) * | 2013-05-24 | 2013-08-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Analogue integrated circuit layout designing method capable of improving layout efficiency |
| CN103606547A (en) * | 2013-11-29 | 2014-02-26 | 深圳市德赛微电子技术有限公司 | Integrated circuit layout structure using laser trimming process and integrated chip |
| CN103903996A (en) * | 2014-04-14 | 2014-07-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Chip bonding pad layout design method suitable for multiple different encapsulation requirements |
| CN209000014U (en) * | 2018-11-21 | 2019-06-18 | 紫光同芯微电子有限公司 | USB KEY chip layout structure |
| CN111209715A (en) * | 2018-11-21 | 2020-05-29 | 紫光同芯微电子有限公司 | Layout structure of USB KEY chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10885259B2 (en) * | 2019-08-30 | 2021-01-05 | Intel Corporation | Random forest model for prediction of chip layout attributes |
-
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- 2020-09-15 CN CN202010965679.3A patent/CN112183012B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103268380A (en) * | 2013-05-24 | 2013-08-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Analogue integrated circuit layout designing method capable of improving layout efficiency |
| CN103606547A (en) * | 2013-11-29 | 2014-02-26 | 深圳市德赛微电子技术有限公司 | Integrated circuit layout structure using laser trimming process and integrated chip |
| CN103903996A (en) * | 2014-04-14 | 2014-07-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Chip bonding pad layout design method suitable for multiple different encapsulation requirements |
| CN209000014U (en) * | 2018-11-21 | 2019-06-18 | 紫光同芯微电子有限公司 | USB KEY chip layout structure |
| CN111209715A (en) * | 2018-11-21 | 2020-05-29 | 紫光同芯微电子有限公司 | Layout structure of USB KEY chip |
Non-Patent Citations (2)
| Title |
|---|
| A linear-mode LiDAR sensor using a multi-channel CMOS transimpedance amplifier array;Chaerin Hong 等;《IEEE Sensors Journal》;第18卷(第17期);7032-7040 * |
| 成像激光雷达接收器模拟前端集成电路与系统研究;郑浩;《中国博士学位论文全文数据库 信息科技辑》(第7期);I135-25 * |
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