CN105550432A - Three-dimensional integrated circuit chip and power network layout method thereof - Google Patents
Three-dimensional integrated circuit chip and power network layout method thereof Download PDFInfo
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- CN105550432A CN105550432A CN201510911851.6A CN201510911851A CN105550432A CN 105550432 A CN105550432 A CN 105550432A CN 201510911851 A CN201510911851 A CN 201510911851A CN 105550432 A CN105550432 A CN 105550432A
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- chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention provides a three-dimensional integrated circuit chip and a power network layout method thereof. The method comprises the following steps: providing at least two layers of chips which are mutually communicated; arranging a re-routing layer on the top layer of chip in the at least two layers of chips, wherein the re-routing layer is communicated with the middle area of the top layer of chip; and communicating the re-routing layer with an external power. The three-dimensional integrated circuit chip and the power network layout method thereof are characterized in that the re-routing layer is arranged on the top layer of chip, the external power is introduced into the middle area of the top layer of chip through the re-routing layer, other chips obtain power supply from the top layer of chip through a silicon through hole positioned in the middle area, the thickness and the width of a conductor on the re-routing layer can be designed to a large size to greatly reduce resistance on the conductor since the re-routing layer is free from the limitation of the own thickness and area of the top layer of chip and does not occupy the winding resources of the top layer of chip, and therefore, the power supply effect of the top layer of chip is greatly improved so as to improve the power performance of the whole 3DIC (Three-Dimensional Integrated Circuit) chip.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of three dimensional integrated circuits chip and power network path approach method thereof.
Background technology
Along with SoC(system integrated chip) scale increasing, 3DIC(three dimensional integrated circuits) chip becomes main flow.Ultra-large 3DIC chip is faced with huge challenge in the design of power supply network network, and power supply deliverability deficiency can cause whole 3DIC chip normally to work.Therefore how on the basis of the two-dimentional power supply network network of traditional SoC, being expanded to three-dimensional, and ensure power supply deliverability, is an important technology.
Fig. 1 is existing 3DIC chip power supply option schematic diagram.As shown in the figure, at least two-layer (being depicted as three layers at this) chip 10 is by TSV(silicon through hole) 20 to communicate with each other, wherein, top layer chip 11 is connected to the pad 40 being positioned at fringe region by wire 30, pad 40 is communicated with external power source (not shown) thus external power source is introduced top layer chip 11, and other chip 12 obtains power supply supply by the silicon through hole 20 being positioned at zone line from top layer chip 11 again.Prior art has stronger power supply capacity for other chip 12 except top layer chip 11, but the power supply bottleneck of whole 3DIC chip is the top layer chip 11 that is connected with outside by wire 30 and pad 40, this is because be limited to thickness and the area of top layer chip 11, coiling resource on top layer chip 11 is very limited, cause the condition of power supply of top layer chip 11 only similar with ordinary two dimensional chip, for the top layer chip 11 bearing whole 3DIC chip power supply responsibility, such design may cause electricity shortage thus have influence on the performance of whole 3DIC chip.
Summary of the invention
The object of the present invention is to provide a kind of three dimensional integrated circuits chip and power network path approach method thereof, improve the power supply effect of top layer chip, improve the power supply performance of whole three dimensional integrated circuits chip.
Based on above consideration, one aspect of the present invention provides a kind of power network path approach method of three dimensional integrated circuits chip, comprising: provide at least layers of chips communicated with each other; Top layer chip in described at least layers of chips is arranged and to reroute layer, described in the layer that reroutes be communicated with the zone line of described top layer chip; The described layer that reroutes is communicated with external power source.
Preferably, the layer that reroutes described in is communicated with the zone line of described top layer chip by the silicon through hole or non-silicon through hole being positioned at zone line.
Preferably, the layer that reroutes described in is communicated with described external power source by the pad being positioned at fringe region.
Preferably, at least two-layer layer that reroutes communicated with each other is set on described top layer chip.
Preferably, described at least two-layer rerouting between layer is communicated with by non-silicon through hole.
Another aspect of the present invention provides a kind of three dimensional integrated circuits chip, comprising: at least layers of chips communicated with each other; The layer that reroutes on top layer chip described in being arranged at least in layers of chips, described in the layer that reroutes be communicated with the zone line of described top layer chip; The described layer that reroutes is communicated with external power source.
Preferably, the layer that reroutes described in is communicated with the zone line of described top layer chip by the silicon through hole or non-silicon through hole being positioned at zone line.
Preferably, the layer that reroutes described in is communicated with described external power source by the pad being positioned at fringe region.
Preferably, described top layer chip is provided with at least two-layer layer that reroutes communicated with each other.
Preferably, described at least two-layer rerouting between layer is communicated with by non-silicon through hole.
Three dimensional integrated circuits chip of the present invention and power network path approach method thereof, on top layer chip, the layer that reroutes is set, by the layer that reroutes, external power source is introduced the zone line of top layer chip, other chip obtains power supply supply by the silicon through hole being positioned at zone line from top layer chip again, due to thickness and the area of top layer chip itself need not be limited to, do not take the coiling resource of top layer chip, the conductor thickness rerouted on layer, it is very large that width can design, thus the resistance greatly reduced on wire, the power supply effect of such top layer chip will be improved greatly, thus improve the power supply performance of whole 3DIC chip.
Accompanying drawing explanation
Read the following detailed description to non-limiting example by referring to accompanying drawing, other features, objects and advantages of the present invention will become more obvious.
Fig. 1 is the electric power network schematic diagram of existing three dimensional integrated circuits chip;
Fig. 2 is the electric power network schematic diagram of three dimensional integrated circuits chip of the present invention;
Fig. 3 is layer schematic diagram that reroute of three dimensional integrated circuits chip of the present invention.
In the drawings, run through different diagrams, same or similar Reference numeral represents same or analogous device (module) or step.
Embodiment
For solving above-mentioned the problems of the prior art, the invention provides a kind of three dimensional integrated circuits chip and power network path approach method thereof, on top layer chip, the layer that reroutes is set, by the layer that reroutes, external power source is introduced the zone line of top layer chip, other chip obtains power supply supply by the silicon through hole being positioned at zone line from top layer chip again, due to thickness and the area of top layer chip itself need not be limited to, do not take the coiling resource of top layer chip, the conductor thickness rerouted on layer, it is very large that width can design, thus the resistance greatly reduced on wire, the power supply effect of such top layer chip will be improved greatly, thus improve the power supply performance of whole 3DIC chip.
In the specific descriptions of following preferred embodiment, with reference to the accompanying drawing formed appended by a part of the present invention.Appended accompanying drawing shows by way of example and can realize specific embodiment of the present invention.The embodiment of example is not intended to limit according to all embodiments of the present invention.Be appreciated that under the prerequisite not departing from scope of the present invention, other embodiments can be utilized, also can carry out amendment that is structural or logicality.Therefore, following specific descriptions are also nonrestrictive, and scope of the present invention limited by appended claim.
One aspect of the present invention provides a kind of power network path approach method of three dimensional integrated circuits chip, comprising: provide at least layers of chips 110 communicated with each other; Top layer chip 111 in described at least layers of chips 110 is arranged and to reroute layer 150, described in the layer 150 that reroutes be communicated with the zone line of described top layer chip 111; The described layer 150 that reroutes is communicated with external power source.
As shown in Figure 2, provide at least two-layer (being depicted as three layers at this) that communicate with each other chip 110, these three layers of chips 110 are communicated with each other by silicon through hole 120.On original top layer chip 111, increase one deck RDL(again to reroute layer) 150, this layer 150 that reroutes is connected to the pad 140 being positioned at fringe region by wire 130, pad 140 is communicated with external power source (not shown) thus external power source is introduced the zone line of the layer 150 that reroutes, reroute layer 150 again by being positioned at the silicon through hole of zone line or non-silicon through hole 160 and being communicated with top layer chip 111 thus the power supply rerouted on layer 150 being fed the zone line of top layer chip 111, due to thickness and the area of top layer chip 111 itself need not be limited to, do not take the coiling resource of top layer chip 111, reroute the thickness of the wire 130 on layer 150, it is very large that width can design, such as, large area power-supply wiring as shown in Figure 3, rerouting in layer region except the signal wire of necessity, under meeting the prerequisite of design rule, all fill out power supply cabling, to reduce the resistance on wire 130, the power supply effect of such top layer chip 111 will be improved greatly, other chip 112 obtains power supply supply by the silicon through hole 120 being positioned at zone line from top layer chip 111 again, thus improve the power supply performance of whole 3DIC chip.
It will be understood by those skilled in the art that according to actual needs, also can arrange on top layer chip 111 two-layer more than to reroute layer 150, each layer is rerouted between layer 150 and is communicated with each other by non-silicon through hole.
Non-silicon through hole of the present invention, namely not through the through hole (Via) of silicon.
Another aspect of the present invention provides a kind of three dimensional integrated circuits chip, comprising: at least layers of chips 110 communicated with each other; The layer 150 that reroutes on top layer chip 111 described in being arranged at least in layers of chips 110, described in the layer 150 that reroutes be communicated with the zone line of described top layer chip 111; The described layer 150 that reroutes is communicated with external power source.
Preferably, the layer 150 that reroutes described in is communicated with the zone line of described top layer chip 111 by the silicon through hole or non-silicon through hole 160 being positioned at zone line.
Preferably, the layer 150 that reroutes described in is communicated with described external power source by the pad 140 being positioned at fringe region.
Preferably, described top layer chip 111 is provided with at least two-layer layer 150 that reroutes communicated with each other, described at least two-layer rerouting between layer 150 is communicated with by non-silicon through hole.
Three dimensional integrated circuits chip of the present invention and power network path approach method thereof, on top layer chip, the layer that reroutes is set, by the layer that reroutes, external power source is introduced the zone line of top layer chip, other chip obtains power supply supply by the silicon through hole being positioned at zone line from top layer chip again, due to thickness and the area of top layer chip itself need not be limited to, do not take the coiling resource of top layer chip, the conductor thickness rerouted on layer, it is very large that width can design, thus the resistance greatly reduced on wire, the power supply effect of such top layer chip will be improved greatly, thus improve the power supply performance of whole 3DIC chip.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, in any case, all should embodiment be regarded as exemplary, and be nonrestrictive.Such as, according to different packaged types, the top layer chip in multilayer chiop may be positioned at above or below packaging part, and therefore " top layer " does not limit specific direction.In addition, significantly, " comprising " one word do not get rid of other elements and step, and wording " one " does not get rid of plural number.Multiple elements of stating in device claim also can be realized by an element.First, second word such as grade is used for representing title, and does not represent any specific order.
Claims (10)
1. a power network path approach method for three dimensional integrated circuits chip, is characterized in that, comprising:
At least layers of chips communicated with each other is provided;
Top layer chip in described at least layers of chips is arranged and to reroute layer, described in the layer that reroutes be communicated with the zone line of described top layer chip;
The described layer that reroutes is communicated with external power source.
2. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 1, is characterized in that, described in the layer that reroutes be communicated with the zone line of described top layer chip by the silicon through hole or non-silicon through hole being positioned at zone line.
3. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 1, is characterized in that, described in the layer that reroutes be communicated with described external power source by the pad being positioned at fringe region.
4. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 1, is characterized in that, arranges at least two-layer layer that reroutes communicated with each other on described top layer chip.
5. the power network path approach method of three dimensional integrated circuits chip as claimed in claim 4, it is characterized in that, described at least two-layer rerouting between layer is communicated with by non-silicon through hole.
6. a three dimensional integrated circuits chip, is characterized in that, comprising:
At least layers of chips communicated with each other;
The layer that reroutes on top layer chip described in being arranged at least in layers of chips, described in the layer that reroutes be communicated with the zone line of described top layer chip;
The described layer that reroutes is communicated with external power source.
7. three dimensional integrated circuits chip as claimed in claim 6, is characterized in that, described in the layer that reroutes be communicated with the zone line of described top layer chip by the silicon through hole or non-silicon through hole being positioned at zone line.
8. three dimensional integrated circuits chip as claimed in claim 6, is characterized in that, described in the layer that reroutes be communicated with described external power source by the pad being positioned at fringe region.
9. three dimensional integrated circuits chip as claimed in claim 6, is characterized in that, described top layer chip is provided with at least two-layer layer that reroutes communicated with each other.
10. three dimensional integrated circuits chip as claimed in claim 9, it is characterized in that, described at least two-layer rerouting between layer is communicated with by non-silicon through hole.
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| CN201510911851.6A CN105550432A (en) | 2015-12-11 | 2015-12-11 | Three-dimensional integrated circuit chip and power network layout method thereof |
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| CN201510911851.6A CN105550432A (en) | 2015-12-11 | 2015-12-11 | Three-dimensional integrated circuit chip and power network layout method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113821098A (en) * | 2021-09-17 | 2021-12-21 | 东科半导体(安徽)股份有限公司 | Low-power consumption power supply |
| WO2022160102A1 (en) * | 2021-01-26 | 2022-08-04 | 华为技术有限公司 | Chip stacking structure and production method therefor, chip stacking package, and electronic device |
| CN115985862A (en) * | 2023-01-12 | 2023-04-18 | 之江实验室 | Integrated substrate structure for on-chip system and on-chip system |
| WO2023202147A1 (en) * | 2022-04-19 | 2023-10-26 | 珠海欧比特宇航科技股份有限公司 | Field-effect transistor array and multi-module heterogeneous chip |
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Application publication date: 20160504 |