CN101930971A - Multichip packaging structure and the method that forms multichip packaging structure - Google Patents
Multichip packaging structure and the method that forms multichip packaging structure Download PDFInfo
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- CN101930971A CN101930971A CN2010101992792A CN201010199279A CN101930971A CN 101930971 A CN101930971 A CN 101930971A CN 2010101992792 A CN2010101992792 A CN 2010101992792A CN 201010199279 A CN201010199279 A CN 201010199279A CN 101930971 A CN101930971 A CN 101930971A
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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Abstract
A kind of multichip packaging structure and the method that forms multichip packaging structure, the encapsulation of multicore sheet comprises: chip carrier; Semiconductor bare chip, the bare chip that is arranged on chip carrier depends on the face, wherein, a plurality of i/o pads be positioned within the semiconductor bare chip or on; The laminar structure that reroutes is positioned on the semiconductor bare chip, comprises a plurality of bond pads of redistributing that couple these a plurality of i/o pads; At least one closing line is in order to redistribute at least one the interconnection of bond pad and chip carrier; Chip Packaging, be arranged at least another this redistribute on the bond pad; And colloid, at least a portion of encapsulation closing line.Utilize the present invention, can solve the bond pad spacing restricted problem that reduces to cause owing to the bare chip volume, and realized the multicore sheet encapsulation of stacked package structure, thereby can improve chip performance.
Description
Technical field
The present invention is relevant for semiconductor packages, more specifically, and relevant for a kind of multichip packaging structure.
Background technology
As known in the art, there has been various chips (chip) encapsulation technology, for example, ball bar battle array row (BallGrid Array, BGA), line engages (wire bonding), brilliant (flip-chip) or the like, can pass through the junction point (bonding points) on bare chip (die) and the substrate (substrate), bare chip is placed on the substrate.For the miniaturization that guarantees electronic product or communication device and multi-functional, semiconductor packages needs, and as far as possible little on the volume, many pins connect, at a high speed and high function.
Because to the ever-increasing demand of littler, faster and more cheap electronic installation, semiconductor industry is advanced to more and more higher rank with cheap line joining technique continuously.Yet the crystal technique that falls has become institute's selecting technology of higher I/O (I/O) number of pads and higher clock rate.This trend not only can be reflected by most processor, and, high-end Application Specific Integrated Circuit (Application-Specific Integrated Circuit, ASIC) and digital signal processor (DigitalSignal Processor DSP) also uses the assembling of falling the crystal technique.But main flow (mainstream) encapsulation remains line and engages, because for the device less than 500 I/O pads, the price advantage that line engages is still obvious.When brilliant assembling (assembly) was benefited high performance device, for the mainstream applications of majority, cost just became great challenge.Therefore, on industry still is placed on main effort and reduces cost.
Product cost, packaging system performance and whole volume determined fall brilliant with select between line engages to be used for IC interconnect (interconnecting), in the current application, the advantage of the maximum that line engages is that manufacturing process quantity (sheer quantity) flexible and wire bonder (wire bonder) is more.Therefore, it has been mature technique that line engages, and its product manufacture has also carried out thorough research and deeply understood.Therefore, wire bonder has been staple, and depends on platform unlike being used for down the brilliant senior bare chip that engages, and in addition, the line joining technique is very flexible.In the frequency applications, the strictness control of new package design and line length has further expanded the electrical property scope of line bond package.
However, along with developing rapidly of the semiconductor fabrication techniques of last decade, the volume of naked core lamellar body dwindles rapidly, and similarly, the I/O bond pad spacing (pitch) on the bare chip has also reached the limit of wire bonder.Therefore, be necessary in the industry cycle to provide a kind of improved encapsulating structure, extending to next-generation technology node (for example, 55nm following) useful life with the line joining technique, and solve the bond pad spacing restricted problem that reduces to cause owing to the bare chip volume.
Summary of the invention
In view of this, one of the object of the invention is to provide the method for a kind of multichip packaging structure and formation multichip packaging structure.
The invention provides a kind of multichip packaging structure, comprise: chip carrier; Semiconductor bare chip, the bare chip that is arranged on this chip carrier depends on the face, wherein, a plurality of i/o pads be positioned within this semiconductor bare chip or on; The laminar structure that reroutes is positioned on this semiconductor bare chip, and this laminar structure that reroutes comprises a plurality of bond pads of redistributing, and wherein, a plurality of this redistributed bond pad and coupled this a plurality of i/o pads; At least one closing line, this redistributes bond pad and the interconnection of this chip carrier with at least one; Chip Packaging, be arranged at least another this redistribute on the bond pad; And colloid, encapsulate at least a portion of this closing line.
The present invention provides a kind of method that forms multichip packaging structure again, comprises: chip carrier is provided; The semiconductor bare chip is set depends on the face at a bare chip of this chip carrier, wherein, a plurality of i/o pads be positioned within this semiconductor bare chip or on; Provide the laminar structure that reroutes on this semiconductor bare chip, this laminar structure that reroutes comprises a plurality of bond pads of redistributing, and wherein, a plurality of this redistributed bond pad and coupled this a plurality of i/o pads; This is redistributed between bond pad and this chip carrier and is connected at least one closing line at least one; At least another this redistribute a Chip Packaging be set on the bond pad; And at least a portion that encapsulates this closing line by colloid.
Utilize the present invention, can solve the bond pad spacing restricted problem that reduces to cause owing to the bare chip volume, and realized the multicore sheet encapsulation of stacked package structure, thereby improve chip performance.
Description of drawings
Fig. 1 is the principle plane graph of the diffused wafer-level packaging of example according to an embodiment of the invention.
Fig. 2 is along the schematic cross-section of the diffused WLP of line I-I ' among Fig. 1.
Fig. 3 is the schematic diagram of the step of manufacturing diffused WLP as shown in Figure 2.
Fig. 4 is a diffused WLP schematic cross-section according to another embodiment of the invention.
Fig. 5 is the schematic cross-section of joint chip encapsulation according to still a further embodiment.
Fig. 6 is the schematic cross-section of the wire bond chip encapsulation of another embodiment according to the present invention.
Fig. 7 is the schematic cross-section of wire bond chip encapsulation according to still a further embodiment.
Fig. 8 is the schematic cross-section of wire bond chip encapsulation according to still a further embodiment.
Fig. 9 and Figure 10 for according to cross sectional view of the present invention some signal distortion of redistributing bond pad.
Figure 11 is the schematic cross-section that the multicore sheet of the stacked package structure of another embodiment according to the present invention encapsulates.
Figure 12 is the schematic cross-section of the multicore sheet encapsulation of stacked package structure in accordance with another embodiment of the present invention.
Figure 13 is the schematic cross-section of the multicore sheet encapsulation of stacked package structure in accordance with another embodiment of the present invention.
Figure 14 is the schematic cross-section of lead frame multicore sheet encapsulation in accordance with another embodiment of the present invention.
Figure 15 is the schematic cross-section of E-pad LQFP multicore sheet encapsulation in accordance with another embodiment of the present invention.
Figure 16 is the schematic cross-section of QFN multicore sheet encapsulation in accordance with another embodiment of the present invention.
The schematic cross-section that Figure 17 encapsulates for the multicore sheet that has the stacked package structure in accordance with another embodiment of the present invention.
The schematic cross-section that Figure 18 encapsulates for the E-pad LQFP multicore sheet that has the stacked package structure in accordance with another embodiment of the present invention.
The schematic cross-section that Figure 19 encapsulates for the QFN multicore sheet that has the stacked package structure in accordance with another embodiment of the present invention.
Embodiment
In describing below, provided a plurality of specific details and described and be used for thorough the present invention, yet those skilled in the art can understand that the present invention is not limited to this.In addition, some system configuration known and treatment step disclose in this application no longer in detail.
Similarly, the schematic diagram of device embodiment mostly is half principle, is not limited to the size described in graphic, and graphic size only is used to illustrate the present invention, be shown in so it is exaggerated graphic in.When a plurality of embodiment that disclose had common feature, in order to illustrate and to illustrate, similar assembly had identical label, and one of ordinary skill in the art can understand.So follow-up graphic in, do not give unnecessary details.
See also Fig. 1 and Fig. 2.Fig. 1 is diffused (fan-outtype) wafer level packaging structure (Wafer Level Package, WLP) 1 the floor map of example according to an embodiment of the invention.Fig. 2 is along the schematic cross-section of the diffused WLP 1 of line I-I ' among Fig. 1.As Fig. 1 and shown in Figure 2, diffused WLP 1 comprises semiconductor bare chip 10, and wherein, semiconductor bare chip 10 comprises initiatively unilateral (active die face) 10a of naked core and the back side (backside surface) 10b.A plurality of i/o pads 12 are arranged on the unilateral 10a of active naked core of semiconductor bare chip 10.As shown in Figure 1, a plurality of i/o pads 12 can be provided with multirow (row) along four limits of semiconductor bare chip 10, for example, can be triplex row.
Certainly, the line number of i/o pads 12 only is used to illustrate the present invention.For example, among other embodiment, it is two row or four lines that i/o pads 12 can be arranged.I/o pads 12 is arranged so that solder pad space length is approximating closely on the unilateral 10a of active naked core, and the solder pad space length restriction that can exceed senior wire bonder closely.One of purpose of the present invention just is to handle this problem that produces owing to the bare chip volume-diminished.
As shown in Figure 2, provide support structure (support structure) 16 of present embodiment is surrounded (encompass) semiconductor bare chips 10.More preferably, supporting structure 16 comprises glue cake (molding compound).Supporting structure 16 can have end face 16a, and end face 16a flushes (flush) substantially with the unilateral 10a of active naked core.Illustrate, except the unilateral 10a of active naked core that i/o pads 12 forms, supporting structure 16 surrounds other surfaces of semiconductor bare chip 10.
Still consult Fig. 2, the laminar structure that reroutes (rewiring laminate structure) 20 is being provided on the unilateral 10a of active naked core and on the end face 16a in supporting structure 16.The laminar structure 20 that reroutes comprises rerouting metal level (re-routed metal layer) 21, and rerouting metal level 21 is formed in the dielectric layer (dielectriclayer) 24, wherein dielectric layer 24 can be for for example silica (silicon oxide), silicon nitride (siliconnitride), pi (polyimide), based on the condensate dielectric (benzocyclobutane of photosensitive benzocyclobutene, BCB-based polymer dielectric) and above-mentioned several persons' combination (combination), perhaps any material that other is fit to.Rerouting metal level 21 can be formed by copper, aluminium or the two combination, perhaps other any suitable material.Reroute in the laminar structure 20 rerouting metal level 21 with within the semiconductor bare chip 10 or on i/o pads 12 redistribute (redistribute) with among the dielectric layer 24 or on form and redistribute bond pad (redistribution band pad) 22.According to one embodiment of present invention, redistributing bond pad 22 can be formed by copper, aluminium, titanium (titanium), nickel (nickel), vanadium (vanadium) or above-mentioned several persons' combination, perhaps other any suitable material.I/o pads 12 can be formed by copper, aluminium or the two combination, perhaps other any suitable material.Be understandable that,, only be used to illustrate the present invention as the described cross section structure of redistributing bond pad 22 of Fig. 2 to Fig. 8.Redistribute other configurations of bond pad 22, just can use as long as can be couple to i/o pads 12.Illustrate, Fig. 9 and Figure 10 are some signal distortion of redistributing bond pad 22, wherein as shown in Figure 9 redistribute the part that bond pad 22 can be used as rerouting metal level 21, perhaps with the combination of other material shown in Figure 10.
According to one embodiment of present invention, a plurality of bond pads 22 of redistributing can be arranged and are multirow, for example two go or triplex rows, a plurality of bond pads 22 of redistributing can throw (project) outside the 10c of the bare chip side of semiconductor bare chip 10 (die edge) (beyond).In another embodiment, only some is redistributed bond pad 22 and is incident upon outside the 10c of bare chip side.And in another embodiment, at least a portion of redistributing bond pad 22 is not incident upon outside the 10c of bare chip side.In another embodiment, do not redistribute bond pad 22 and be incident upon outside the 10c of bare chip side.Be understandable that the number of the row of i/o pads 12 can be different with the number of the row of redistributing bond pad 22.Illustrate, i/o pads 12 can be placed becomes four lines, redistributes bond pad 22 and then can arrange and be triplex row.
According to another embodiment of the invention, semiconductor bare chip 10 can be Power Management Unit or power supply IC, wherein being arranged in initiatively, the unilateral 10a of naked core goes up some power pads or the ground pad that inboard (inner) goes, mode by the laminar structure 20 that reroutes, can on dielectric layer 24, redistribute for the outside (outer) of the multirow of redistributing bond pad 22 OK, perhaps outermost (outmost) is OK.Through operation thus, chip performance just can improve.In other words, in this invention, bond pad just can be redistributed to adapt to encapsulation and performance requirement.
Fig. 3 is the schematic diagram of the step of manufacturing diffused WLP 1 as shown in Figure 2.As shown in Figure 3, the manufacturing of diffused WLP 1 shown in Figure 1 can be divided into following several stages: wafer cutting (dicing) (step 51), wafer reconfigure (step 52), redistribute (step 53) and encapsulated moulding (singulation) (step 54).After encapsulated moulding, selectively, can implement polishing (polishing process) (step 55) to remove a part of glue cake, therefore the back side 10b of semiconductor bare chip 10 can be come out.If to step 54, back side 10b comes out in step 51, do not come out if perhaps do not wish it, step 55 just can be omitted so.Be understandable that, can use other method and make diffused WLP.The different company of technology is redistributed in use, may use different materials and processing procedure to realize diffused WLP.However, required step all is similar.
The re-distribution layer technology is used extra step and has been expanded the manufacturing process of traditional wafer manufacturing (fabrication), wherein, extra step is will conduct electricity rerouting (conductive rerouting) and interconnection system deposition (deposit) to each device (for example chip) of wafer.Expand traditional wafer manufacturing process can use the technology of similar and compatible photoetching (photolithography) and thin film deposition (thin filmdeposition) and reach, wherein, photoetching and film deposition techniques are made in self at device and are used.Other interconnection of additional layer (additional layer of interconnection) can be redistributed periphery connection (peripheral contact) pad of each chip and be the area array of the conductive welding disk that is arranged on chip surface (area array).
Fig. 4 is according to another embodiment of the invention, diffused WLP 1a schematic cross-section.As shown in Figure 4, similarly, diffused WLP 1a comprises semiconductor bare chip 10, and wherein, semiconductor bare chip 10 has initiatively unilateral 10a of naked core and back side 10b.And on the unilateral 10a of active naked core of semiconductor bare chip 10, can provide a plurality of i/o pads 12 (for example aluminum bond pads).I/o pads 12 can be along 4 bare chip side 10c of semiconductor bare chip 10 and is provided with.
Provide support structure 16 of present embodiment is surrounded semiconductor bare chips 10.More preferably, supporting structure 16 can comprise and has better mechanical strength and and the glue cake of 10 good bondings of semiconductor bare chip (adhesion) power.Supporting structure 16 can have end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.In this embodiment, supporting structure 16 only covers the bare chip side 10c of semiconductor bare chip 10.Supporting structure 16 is not surrounded back side 10b, and back side 10b comes out.
Similarly, provide the laminar structure 20 that reroutes on the end face 16a of unilateral 10a of active naked core and supporting structure 16, the laminar structure 20 that wherein reroutes comprises the rerouting metal level 21 that is formed on the dielectric layer 24.Reroute in the laminar structure 20 rerouting metal level 21 with within the semiconductor bare chip 10 or on a plurality of i/o pads 12 redistribute, redistribute bond pad 22 to form in dielectric layer 24 or on the dielectric layer 24.
Fig. 5 is the schematic cross-section of demonstration wire bond chip encapsulation 100 according to still a further embodiment.As shown in Figure 5, semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c, the bare chip that is arranged on chip carrier (chip carrier) 40 depends on face (attach surface) 40a, wherein, chip carrier 40 can be for example base plate for packaging or printed circuit board (PCB), wherein, a plurality of i/o pads 12 be positioned on the semiconductor bare chip 10 or within.Supporting structure 16 can be surrounded semiconductor bare chip 10.And supporting structure 16 has end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
The laminar structure 20 that reroutes is provided on the semiconductor bare chip 10, the laminar structure 20 that reroutes comprises a plurality of bond pads 22 of redistributing, and a plurality of bond pads 22 of redistributing can be incident upon outside the 10c of bare chip side, perhaps also can not be incident upon outside the 10c of bare chip side.The corresponding engagement pad 42 that uses a plurality of closing lines (bond wire) 50 will redistribute on bond pad 22 and the chip carrier 40 interconnects.Provide colloid (mold cap) 60 to encapsulate (encapsulate) semiconductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16 and closing line 50 at least.According to this embodiment, colloid 60 and supporting structure 16 can be made by different glue cakes.
According to this embodiment, closing line 50 can comprise gold, copper or the two combination, perhaps other material that is fit to.According to one embodiment of present invention, redistribute bond pad 22 and form, and closing line 50 is a copper cash by copper.
Because the i/o pads with tight solder pad space length 12 on the semiconductor bare chip 10 is redistributed at peripheral (peripheral), be incident upon the exterior lateral area (outer area) outside the 10c of bare chip side, therefore redistributing bond pad 22 has the loose solder pad space length that is used for the line joint applications.But, as previously mentioned,, redistribute bond pad 22 and can be incident upon outside the 10c of bare chip side according to designing requirement, perhaps be not incident upon outside the 10c of bare chip side.
Fig. 6 is the schematic cross-section of the wire bond chip encapsulation 100a of another embodiment according to the present invention.As shown in Figure 6, via tack coat (adhesive layer) 152, diffused WLP 1a is arranged on chip carrier (in this embodiment, for example lead frame 140) bare chip depend on face or the bare chip pad 140a, wherein diffused WLP 1a comprises having the initiatively semiconductor bare chip 10 of the unilateral 10a of naked core and bare chip side 10c, a plurality of i/o pads 12 be positioned within the semiconductor bare chip 10 or on.Diffused WLP 1a can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 has end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
Diffused WLP 1a further comprises the laminar structure 20 that reroutes, and the laminar structure 20 that reroutes is on the semiconductor bare chip 10 and on the end face 16a of supporting structure 16.The laminar structure 20 that reroutes can be made in encapsulation factory (assembly house).The laminar structure 20 that reroutes comprises a plurality ofly redistributes bond pad 22, and a plurality of bond pad 22 of redistributing can be incident upon outside the 10c of bare chip side, and redistributes bond pad 22 and can have the loose solder pad space length that is used for the line joint applications.In another embodiment, be pursuant to designing requirement, redistribute bond pad 22 and can not be incident upon outside the 10c of bare chip side, perhaps only wherein a part be incident upon outside the 10c of bare chip side.In another embodiment, a part of redistributing bond pad 22 at least is not incident upon outside the 10c of bare chip side.
Using a plurality of closing lines 50 will redistribute bond pad 22 interconnects with the corresponding inboard pin (inner lead) 142 of lead frame (leadframe) 140.Colloid 60 is packaged into not a half conductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16, bare chip pad 140a, inboard pin 142 and closing line 50.According to this embodiment, closing line 50 can comprise gold, copper, the perhaps combination of said two devices, perhaps other material that is fit to.
Fig. 7 is the schematic cross-section of wire bond chip encapsulation 100b according to still a further embodiment.As shown in Figure 7, by tack coat 152, the diffused WLP 1a that comprises semiconductor bare chip 10 is arranged on the bare chip pad 140a of lead frame 140, and semiconductor bare chip 10 has initiatively unilateral 10a of naked core and bare chip side 10c, wherein, a plurality of i/o pads 12 be positioned within the semiconductor bare chip 10 or on.Diffused WLP 1a can comprise the supporting structure 16 of surrounding semiconductor bare chip 10, and wherein supporting structure 16 has end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.Diffused WLP 1a further is included in the laminar structure 20 that reroutes on the end face 16a of semiconductor bare chip 10 and supporting structure 16.Similarly, the laminar structure 20 that reroutes comprises a plurality ofly redistributes bond pad 22, and a plurality of bond pad 22 of redistributing can be incident upon outside the 10c of bare chip side, perhaps is not incident upon outside the 10c of bare chip side.
A plurality of closing lines 50 are used for interconnecting redistributing the inboard pin 142 of bond pad 22 with lead frame 140.Closing line 50 can comprise the combination of gold, copper or said two devices, perhaps other material that is fit to.Colloid 60 is packaged into not a half conductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16, inboard pin 142 and closing line 50.According to this embodiment, the bottom surface 140b of bare chip pad 140a can't help colloid 60 and surrounds, and therefore, can expose in the air.Such encapsulating structure can be referred to as exposed pad (Exposed-Pad, E-pad) slim four limit pin flat packaging (Low-Profile Quad FlatPackage, LQFP).
Fig. 8 is the schematic cross-section of wire bond chip encapsulation 100c according to still a further embodiment.As shown in Figure 8, the diffused WLP 1a that comprises semiconductor bare chip 10, be arranged on the bare chip pad 240a of lead frame 240, and semiconductor bare chip 10 has initiatively unilateral 10a of naked core and bare chip side 10c, wherein, a plurality of i/o pads 12 be positioned within the semiconductor bare chip 10 or on.Bare chip pad 240a further can comprise cavity (recess) 240c, and semiconductor bare chip 10 can be arranged in the cavity 240c.Diffused WLP 1a can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 can have end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.Diffused WLP 1a further is included in the laminar structure 20 that reroutes on the semiconductor bare chip 10.Similarly, the laminar structure 20 that reroutes comprises a plurality ofly redistributes bond pad 22, and a plurality of bond pad 22 of redistributing can be incident upon outside the 10c of bare chip side, perhaps is not incident upon outside the 10c of bare chip side.
A plurality of closing lines 50 are used for interconnecting with the corresponding interconnect pad 242 of lead frame 240 redistributing bond pad 22.Closing line 50 can comprise the combination of gold, copper or said two devices, perhaps other material that is fit to.Colloid 60 is packaged into not a half conductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16, the top of bare chip pad 240a, the top and the closing line 50 of interconnect pad 242.Package arrangements as shown in Figure 8 can be referred to as square flat non-pin, and (quad flat non-leaded, QFN) encapsulation or advanced quad flat do not have pin (advanced quad flat non-leaded, aQFN) encapsulating structure.
In other embodiments, can omit to supporting structure 16 shown in Figure 10 as Fig. 2, Fig. 4.In other embodiments, on semiconductor bare chip 10, can have another semiconductor bare chip.Another semiconductor bare chip can be couple to semiconductor bare chip 10 via at least one closing line.In other embodiments, another semiconductor bare chip can be couple to not project in the semiconductor bare chip 10 and redistribute bond pad 22 outside the 10c of bare chip side.
Figure 11 is stacked package (package-on-package, the POP) schematic cross-section of the multicore sheet of structure encapsulation 200, wherein identical identical zone, layer or the assembly of label representative of another embodiment according to the present invention.As shown in figure 11, multicore sheet encapsulation 200 comprises diffused WLP 1b, and wherein diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c.The bare chip that diffused WLP 1b is arranged on chip carrier 40 depends on the face 40a, chip carrier 40 is base plate for packaging, printed circuit board (PCB) or lead frame for example, wherein, a plurality of i/o pads 12 and the 12a unilateral 10a of active naked core that is positioned at semiconductor bare chip 10 goes up or is positioned at semiconductor bare chip 10.Supporting structure 16 (for example glue cake) is surrounded semiconductor bare chip 10.Supporting structure 16 has end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
The laminar structure 20 that reroutes is provided on semiconductor bare chip 10, and the laminar structure 20 that reroutes comprises a plurality of bond pad 22 and 22a of redistributing, and is used for i/o pads 12 and 12a. Redistribute bond pad 22 and 22a and can be incident upon outside the 10c of bare chip side, perhaps also can not be incident upon outside the 10c of bare chip side.Use at least one closing line 50 at least one to be redistributed corresponding engagement pad 42 interconnects on bond pad 22 and 22a and the chip carrier 40.
Provide colloid 60 with encapsulation at least a portion closing line 50, and further at least a portion of encapsulated semiconductor bare chip 10, reroute laminar structure 20 and supporting structure 16.According to this embodiment, colloid 60 and supporting structure 16 can be made by different glue cakes.According to another embodiment, closing line 50 can comprise gold, copper or the two combination, perhaps other material that is fit to.According to another embodiment of the present invention, redistribute bond pad 22 and form, and closing line 50 is a copper cash by copper.
The unilateral 10a of active naked core that i/o pads 12a is positioned at semiconductor bare chip 10 goes up or is positioned at semiconductor bare chip 10.I/o pads 12a by re-wiring layer (Re-distribute Layer, RDL) 21a reassign to separately redistribute bond pad 22a.Have cavity 60a in the colloid 60 and redistribute bond pad 22a with exposure.Chip Packaging 1c is arranged on the diffused WLP1b of cavity 60a inside.In the present embodiment, Chip Packaging 1c is electrically connected with diffused WLP 1b by projection (bump) 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Figure 12 is the schematic cross-section of the multicore sheet encapsulation 200a of stacked package structure in accordance with another embodiment of the present invention, wherein identical identical zone, layer or the assembly of label representative.A main distinction of the multicore sheet encapsulation 200 shown in the multicore sheet encapsulation 200a shown in Figure 12 and Figure 11 is that the Chip Packaging 1c of multicore sheet encapsulation 200a is arranged on the projection 322 that is encapsulated by colloid 60.Projection 322 is electrically connected the projection 222 of Chip Packaging 1c with the bond pad 22a that redistributes of diffused WLP 1b.In another embodiment, projection 222, projection 322 or the two can be replaced by the copper post simultaneously, thus Chip Packaging 1c can by the copper post with redistribute bond pad 22a and be electrically connected.According to present embodiment, in colloid 60, there is not cavity.
Figure 13 is the schematic cross-section of the multicore sheet encapsulation 200b of stacked package structure in accordance with another embodiment of the present invention, wherein identical identical zone, layer or the assembly of label representative.As shown in figure 13, multicore sheet encapsulation 200b comprises diffused WLP 1b, and wherein diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c.The bare chip that diffused WLP 1b is arranged on chip carrier 40 depends on the face 40a, chip carrier 40 is base plate for packaging, printed circuit board (PCB) or lead frame for example, wherein, a plurality of i/ o pads 12 and 12a are positioned on the semiconductor bare chip 10 or are positioned at semiconductor bare chip 10.Supporting structure 16 (for example glue cake) is surrounded semiconductor bare chip 10.Supporting structure 16 has end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
The laminar structure 20 that reroutes is provided on semiconductor bare chip 10, and the laminar structure 20 that reroutes comprises a plurality of bond pad 22 and 22a of redistributing, and is used for i/o pads 12 and 12a.Redistribute bond pad 22 and 22a and can be incident upon outside the 10c of bare chip side, perhaps also can not be incident upon outside the 10c of bare chip side.Use at least one closing line 50 at least one to be redistributed corresponding engagement pad 42 interconnects on bond pad 22 and the chip carrier 40.The unilateral 10a of active naked core that i/o pads 12a is positioned at semiconductor bare chip 10 goes up or is positioned at semiconductor bare chip 10.I/o pads 12a by re-wiring layer 21a reassign to separately redistribute bond pad 22a.In the present embodiment, Chip Packaging 1c is electrically connected with diffused WLP 1b by projection 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Provide colloid 60 with encapsulation at least a portion closing line 50, and further at least a portion of encapsulated semiconductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16, and the further part of packaged chip encapsulation 1c.According to an embodiment, colloid 60 and supporting structure 16 can be made by different glue cakes.According to another embodiment, closing line 50 can comprise gold, copper or the two combination, perhaps other material that is fit to.According to another embodiment of the present invention, redistribute bond pad 22 and form, and closing line 50 is a copper cash by copper.
Figure 14 is the schematic cross-section of lead frame multicore sheet encapsulation 200c in accordance with another embodiment of the present invention.As shown in figure 14, diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c.And via tack coat 152, the bare chip that diffused WLP 1b is arranged on lead frame 140 depends on face or the bare chip pad 140a, wherein, a plurality of i/o pads 12 and the 12a unilateral 10a of naked core that is positioned at semiconductor bare chip 10 go up or semiconductor bare chip 10 within.Diffused WLP 1b can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 has end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
Diffused WLP 1b further comprises the laminar structure 20 that reroutes, and the laminar structure 20 that reroutes is on the semiconductor bare chip 10 and on the end face 16a of supporting structure 16.The laminar structure 20 that reroutes can be made in encapsulation factory.The laminar structure 20 that reroutes comprises a plurality of bond pad 22 and 22a of redistributing, a plurality ofly redistribute bond pad 22 and 22a can be incident upon outside the 10c of bare chip side, also can not be incident upon outside the 10c of bare chip side, and redistribute bond pad 22 and can have the loose solder pad space length that is used for the line joint applications.On the unilateral 10a of naked core that a plurality of i/o pads 12a are positioned at semiconductor bare chip 10 or within the semiconductor bare chip 10.I/o pads 12a by re-wiring layer (Re-distribute Layer, RDL) 21a reassign to separately redistribute bond pad 22a.In the present embodiment, Chip Packaging 1c is arranged on the diffused WLP 1b, and is electrically connected with diffused WLP 1b by projection 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Using at least one closing line 50 that at least one is redistributed bond pad 22 interconnects with the corresponding inboard pin 142 of lead frame 140.Colloid 60 encapsulation at least a portion closing lines 50, and the further part in encapsulated semiconductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16, bare chip pad 140a, the inboard pin 142, and the part of further packaged chip encapsulation 1c.According to this embodiment, closing line 50 can comprise gold, copper, the perhaps combination of said two devices, perhaps other material that is fit to.
Figure 15 is the schematic cross-section of E-pad LQFP multicore sheet encapsulation 200d in accordance with another embodiment of the present invention.As shown in figure 15, diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c.And via tack coat 152, diffused WLP 1b is arranged on the bare chip pad 140a of lead frame 140, and wherein, a plurality of i/ o pads 12 and 12a are positioned on the semiconductor bare chip 10 or within the semiconductor bare chip 10.Diffused WLP 1b can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 has end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
Diffused WLP 1b further comprises the laminar structure 20 that reroutes, and the laminar structure 20 that reroutes is on the semiconductor bare chip 10 and on the end face 16a of supporting structure 16.The laminar structure 20 that reroutes comprises a plurality of bond pad 22 and 22a of redistributing, and a plurality ofly redistributes bond pad 22 and 22a can be incident upon outside the 10c of bare chip side, also can not be incident upon outside the 10c of bare chip side.On the unilateral 10a of naked core that a plurality of i/o pads 12a are positioned at semiconductor bare chip 10 or within the semiconductor bare chip 10.I/o pads 12a by re-wiring layer 21a reassign to separately redistribute bond pad 22a.In the present embodiment, Chip Packaging 1c is arranged on the diffused WLP 1b, and is electrically connected with diffused WLP 1b by projection 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Using at least one closing line 50 that at least one is redistributed bond pad 22 interconnects with the corresponding inboard pin 142 of lead frame 140.Closing line 50 can comprise gold, copper, the perhaps combination of said two devices, perhaps other material that is fit to.At least a portion of colloid 60 encapsulation closing lines 50, and the further part in encapsulated semiconductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16, bare chip pad 140a, the inboard pin 142, and the part of further packaged chip encapsulation 1c.According to this embodiment, colloid 60 does not encapsulate the bottom surface 140b of bare chip pad 140a, and bottom surface 140b is exposed in the air.
Figure 16 is the schematic cross-section of QFN multicore sheet encapsulation 200e in accordance with another embodiment of the present invention.As shown in figure 16, diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c.And diffused WLP 1b is arranged on the bare chip pad 240a of lead frame 240, and wherein, a plurality of i/ o pads 12 and 12a are positioned on the semiconductor bare chip 10 or within the semiconductor bare chip 10.Bare chip pad 240a further can comprise cavity (recess) 240c, and semiconductor bare chip 10 can be arranged in the cavity 240c.Diffused WLP 1b can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 can have end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
Diffused WLP 1b further is included in the laminar structure 20 that reroutes on the semiconductor bare chip 10.The laminar structure 20 that reroutes comprises a plurality ofly redistributes bond pad 22 and 22a, and a plurality ofly redistributes bond pad 22 and 22a can be incident upon outside the 10c of bare chip side, perhaps is not incident upon outside the 10c of bare chip side.I/o pads 12a is positioned on the unilateral 10a of active naked core of semiconductor bare chip 10 or within the semiconductor bare chip 10.I/o pads 12a by re-wiring layer 21a reassign to separately redistribute bond pad 22a.In the present embodiment, Chip Packaging 1c is arranged on the diffused WLP1b, and is electrically connected with diffused WLP 1b by projection 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Using at least one closing line 50 that at least one is redistributed bond pad 22 interconnects with the corresponding interconnection pin 242 of lead frame 240.Closing line 50 can comprise gold, copper, the perhaps combination of said two devices, perhaps other material that is fit to.Colloid 60 encapsulation at least a portion closing lines 50, and the further part in the top of the top of encapsulated semiconductor bare chip 10, the laminar structure 20 that reroutes, supporting structure 16, bare chip pad 240a, interconnection pin 242, and at least a portion of further packaged chip encapsulation 1c.
Figure 17 encapsulates the schematic cross-section of 200f for the multicore sheet that has the stacked package structure in accordance with another embodiment of the present invention.As shown in figure 17, diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c, and via tack coat 152, the bare chip that diffused WLP 1b is arranged on lead frame 140 depends on face or the bare chip pad 140a, wherein, a plurality of i/ o pads 12 and 12a are positioned on the unilateral 10a of naked core of semiconductor bare chip 10 or within the semiconductor bare chip 10.Diffused WLP 1b can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 can have end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
Diffused WLP 1b further be included on the semiconductor bare chip 10 and the end face 16a of supporting structure 16 on the laminar structure 20 that reroutes.The laminar structure 20 that reroutes can be made in encapsulation factory.The laminar structure 20 that reroutes comprises a plurality ofly redistributes bond pad 22 and 22a, and a plurality ofly redistributes bond pad 22 and 22a can be incident upon outside the 10c of bare chip side, perhaps is not incident upon outside the 10c of bare chip side.And redistribute bond pad 22 and can have the loose solder pad space length that is used for the line joint applications.I/o pads 12a is positioned on the unilateral 10a of active naked core of semiconductor bare chip 10 or within the semiconductor bare chip 10.I/o pads 12a by re-wiring layer 21a reassign to separately redistribute bond pad 22a.Have cavity 60a in the colloid 60 and redistribute bond pad 22a with exposure.Chip Packaging 1c is arranged on the diffused WLP 1b of cavity 60a inside.In the present embodiment, Chip Packaging 1c is electrically connected with diffused WLP 1b by projection 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Using at least one closing line 50 that at least one is redistributed bond pad 22 interconnects with the corresponding inboard pin 142 of lead frame 140.Colloid 60 encapsulation at least a portion closing lines 50.According to present embodiment, closing line 50 can comprise gold, copper, the perhaps combination of said two devices, perhaps other material that is fit to.
Figure 18 encapsulates the schematic cross-section of 200g for the E-pad LQFP multicore sheet that has the stacked package structure in accordance with another embodiment of the present invention.As shown in figure 18, diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c, and via tack coat 152, diffused WLP1b is arranged on the bare chip pad 140a of lead frame 140, wherein, a plurality of i/ o pads 12 and 12a are positioned on the unilateral 10a of naked core of semiconductor bare chip 10 or within the semiconductor bare chip 10.Diffused WLP 1b can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 can have end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
Diffused WLP 1b further be included on the semiconductor bare chip 10 and the end face 16a of supporting structure 16 on the laminar structure 20 that reroutes.The laminar structure 20 that reroutes comprises a plurality ofly redistributes bond pad 22 and 22a, and a plurality ofly redistributes bond pad 22 and 22a can be incident upon outside the 10c of bare chip side, perhaps is not incident upon outside the 10c of bare chip side.I/o pads 12a is positioned on the unilateral 10a of active naked core of semiconductor bare chip 10 or within the semiconductor bare chip 10.I/o pads 12a by re-wiring layer 21a reassign to separately redistribute bond pad 22a.Have cavity 60a in the colloid 60 and redistribute bond pad 22a with exposure.Chip Packaging 1c is arranged on the diffused WLP1b of cavity 60a inside.In the present embodiment, Chip Packaging 1c is electrically connected with diffused WLP 1b by projection 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Using at least one closing line 50 that at least one is redistributed bond pad 22 interconnects with the corresponding inboard pin 142 of lead frame 140.Closing line 50 can comprise gold, copper, the perhaps combination of said two devices, perhaps other material that is fit to.At least a portion of colloid 60 encapsulation closing lines 50.According to present embodiment, colloid 60 does not encapsulate the bottom surface 140b of bare chip pad 140a, and bottom surface 140b is exposed in the air.
Figure 19 encapsulates the schematic cross-section of 200h for the QFN multicore sheet that has the stacked package structure in accordance with another embodiment of the present invention.As shown in figure 19, diffused WLP 1b comprises the semiconductor bare chip 10 with the unilateral 10a of naked core and bare chip side 10c.And diffused WLP 1b is arranged on the bare chip pad 240a of lead frame 240, and wherein, a plurality of i/ o pads 12 and 12a are positioned on the semiconductor bare chip 10 or within the semiconductor bare chip 10.Bare chip pad 240a further can comprise cavity (recess) 240c, and semiconductor bare chip 10 can be arranged in the cavity 240c.Diffused WLP 1b can comprise supporting structure 16, and supporting structure 16 is surrounded semiconductor bare chip 10.Supporting structure 16 can have end face 16a, and end face 16a flushes substantially with the unilateral 10a of active naked core.
Diffused WLP 1b further is included in the laminar structure 20 that reroutes on the semiconductor bare chip 10.The laminar structure 20 that reroutes comprises a plurality ofly redistributes bond pad 22 and 22a, and a plurality ofly redistributes bond pad 22 and 22a can be incident upon outside the 10c of bare chip side, perhaps is not incident upon outside the 10c of bare chip side.I/o pads 12a is positioned on the unilateral 10a of active naked core of semiconductor bare chip 10 or within the semiconductor bare chip 10.I/o pads 12a by re-wiring layer 21a reassign to separately redistribute bond pad 22a.Have cavity 60a in the colloid 60 and redistribute bond pad 22a with exposure.Chip Packaging 1c is arranged on the diffused WLP 1b of cavity 60a inside.In the present embodiment, Chip Packaging 1c is electrically connected with diffused WLP 1b by projection 222, and wherein projection 222 is engaged to and redistributes bond pad 22a.In another embodiment, Chip Packaging 1c can be electrically connected with diffused WLP 1b by the copper post, and wherein the copper post is engaged to and redistributes bond pad 22a.
Using at least one closing line 50 that at least one is redistributed bond pad 22 interconnects with the corresponding interconnection pin 242 of lead frame 240.Closing line 50 can comprise gold, copper, the perhaps combination of said two devices, perhaps other material that is fit to.At least a portion of colloid 60 encapsulation closing lines 50.
Those skilled in the art without departing from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is appendedly applied for a patent the claim person of defining and is as the criterion when looking.
Claims (20)
1. multichip packaging structure comprises:
Chip carrier;
Semiconductor bare chip, the bare chip that is arranged on this chip carrier depends on the face, wherein, a plurality of i/o pads be positioned within this semiconductor bare chip or on;
The laminar structure that reroutes is positioned on this semiconductor bare chip, and this laminar structure that reroutes comprises a plurality of bond pads of redistributing, and wherein, a plurality of this redistributed bond pad and coupled this a plurality of i/o pads;
At least one closing line, this redistributes bond pad and the interconnection of this chip carrier with at least one;
Chip Packaging, be arranged at least another this redistribute on the bond pad; And
Colloid encapsulates at least a portion of this closing line.
2. multichip packaging structure as claimed in claim 1, wherein, this redistribute in the bond pad at least one be incident upon outside the bare chip side of this semiconductor bare chip.
3. multichip packaging structure as claimed in claim 1 is characterized in that this Chip Packaging is arranged in the cavity of this colloid.
4. multichip packaging structure as claimed in claim 1 is characterized in that this colloid further encapsulates at least a portion of this Chip Packaging.
5. multichip packaging structure as claimed in claim 1 is characterized in that, this Chip Packaging is electrically connected with this semiconductor bare chip by at least one projection, redistributes bond pad on wherein this bump bond to this Chip Packaging is arranged at.
6. multichip packaging structure as claimed in claim 1 is characterized in that, this chip carrier is base plate for packaging or printed circuit board (PCB).
7. multichip packaging structure as claimed in claim 1 is characterized in that, this chip carrier is a lead frame.
8. multichip packaging structure as claimed in claim 7 is characterized in that, this multicore sheet is encapsulated as slim four limit pin flat packaging or square flat non-pin encapsulation.
9. multichip packaging structure as claimed in claim 1 is characterized in that, this closing line is gold thread or copper cash.
10. multichip packaging structure as claimed in claim 1 is characterized in that, further comprises supporting structure, and this supporting structure is surrounded this semiconductor bare chip.
11. multichip packaging structure as claimed in claim 10 is characterized in that, the end face of this supporting structure flushes substantially with the naked core of this semiconductor bare chip is unilateral.
12. multichip packaging structure as claimed in claim 11 is characterized in that, this laminar structure that reroutes also is formed on this end face of this supporting structure.
13. multichip packaging structure as claimed in claim 10 is characterized in that, this supporting structure is become by different glue cheeses with this colloid.
14. multichip packaging structure as claimed in claim 1 is characterized in that, this Chip Packaging can be electrically connected with this semiconductor bare chip by at least one copper post, and wherein this copper post is engaged to this Chip Packaging and redistributes bond pad on being arranged at.
15. a method that forms multichip packaging structure comprises:
Chip carrier is provided;
Semiconductor bare chip is set depends on the face at the bare chip of this chip carrier, wherein, a plurality of i/o pads be positioned within this semiconductor bare chip or on;
Provide the laminar structure that reroutes on this semiconductor bare chip, this laminar structure that reroutes comprises a plurality of bond pads of redistributing, and wherein, a plurality of this redistributed bond pad and coupled this a plurality of i/o pads;
This is redistributed between bond pad and this chip carrier and is connected at least one closing line at least one;
At least another this redistribute Chip Packaging be set on the bond pad; And
Encapsulate at least a portion of this closing line by colloid.
16. the method for formation multichip packaging structure as claimed in claim 15 is characterized in that, at least one this redistribute outside the bare chip side that bond pad is incident upon this semiconductor bare chip.
17. the method for formation multichip packaging structure as claimed in claim 15 is characterized in that, this Chip Packaging is arranged in the cavity of this colloid.
18. the method for formation multichip packaging structure as claimed in claim 15 is characterized in that, this colloid further encapsulates at least a portion of this Chip Packaging.
19. the method for formation multichip packaging structure as claimed in claim 15, it is characterized in that, this Chip Packaging is electrically connected with this semiconductor bare chip by at least one projection, redistributes bond pad on wherein this bump bond to this Chip Packaging is arranged at.
20. the method for formation multichip packaging structure as claimed in claim 15, it is characterized in that, this Chip Packaging can be electrically connected with this semiconductor bare chip by at least one copper post, and wherein this copper post is engaged to this Chip Packaging and redistributes bond pad on being arranged at.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/485,923 | 2009-06-17 | ||
| US12/485,923 US20100213588A1 (en) | 2009-02-20 | 2009-06-17 | Wire bond chip package |
| US12/704,517 US20100213589A1 (en) | 2009-02-20 | 2010-02-11 | Multi-chip package |
| US12/704,517 | 2010-02-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101930971A true CN101930971A (en) | 2010-12-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101992792A Pending CN101930971A (en) | 2009-06-17 | 2010-06-09 | Multichip packaging structure and the method that forms multichip packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101930971A (en) |
| TW (1) | TW201112387A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403281A (en) * | 2011-10-11 | 2012-04-04 | 常熟市广大电器有限公司 | High-performance packaging structure of chip |
| CN103337486A (en) * | 2013-05-31 | 2013-10-02 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN105550432A (en) * | 2015-12-11 | 2016-05-04 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power network layout method thereof |
| CN112151523A (en) * | 2019-06-28 | 2020-12-29 | 中芯长电半导体（江阴）有限公司 | Packaging structure and packaging method of fan-out type fingerprint identification chip |
| CN112786460A (en) * | 2019-11-08 | 2021-05-11 | 珠海格力电器股份有限公司 | Chip packaging method and chip packaging module |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI552293B (en) * | 2014-09-26 | 2016-10-01 | 矽品精密工業股份有限公司 | Semiconductor package and method of manufacture |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020024151A1 (en) * | 1999-08-17 | 2002-02-28 | Jicheng Yang | Multi-chip module with extension |
| US20040140559A1 (en) * | 2002-10-29 | 2004-07-22 | Bernd Goller | Electronic device configured as a multichip module, leadframe, panel with leadframe positions, and method for producing the electronic device |
| US20070262436A1 (en) * | 2006-05-12 | 2007-11-15 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
-
2010
- 2010-05-31 TW TW099117489A patent/TW201112387A/en unknown
- 2010-06-09 CN CN2010101992792A patent/CN101930971A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020024151A1 (en) * | 1999-08-17 | 2002-02-28 | Jicheng Yang | Multi-chip module with extension |
| US20040140559A1 (en) * | 2002-10-29 | 2004-07-22 | Bernd Goller | Electronic device configured as a multichip module, leadframe, panel with leadframe positions, and method for producing the electronic device |
| US20070262436A1 (en) * | 2006-05-12 | 2007-11-15 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102403281A (en) * | 2011-10-11 | 2012-04-04 | 常熟市广大电器有限公司 | High-performance packaging structure of chip |
| CN103337486A (en) * | 2013-05-31 | 2013-10-02 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN103337486B (en) * | 2013-05-31 | 2015-10-28 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacture method thereof |
| CN105550432A (en) * | 2015-12-11 | 2016-05-04 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power network layout method thereof |
| CN112151523A (en) * | 2019-06-28 | 2020-12-29 | 中芯长电半导体（江阴）有限公司 | Packaging structure and packaging method of fan-out type fingerprint identification chip |
| CN112786460A (en) * | 2019-11-08 | 2021-05-11 | 珠海格力电器股份有限公司 | Chip packaging method and chip packaging module |
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