201112387 六、發明說明： 【發明所屬之技術領域】 本發明有關於半導體封裝，更具體地，有關於一種多晶片封裝。 【先前技術】 如先前技術所知’已存在多種晶片（chip)封裝技術，例如，球柵陣 列(Ball Grid Array，BGA)、線接合(Wire bonding)、覆晶(flip-chip)等等， 可通過裸晶(die)和基板(substrate)上的接合點(bonding points)，將裸晶 安置在基板上。爲了保證電子產品或者通訊裝置的小型化以及多功 能，半導體封裝需要體積上盡量小、多引腳連接、高速以及高功能。 由於對更小、更快以及更便宜的電子裝置不斷增長的需求，半導 體產業連續將價格低廉的線接合技術推進到越來越高的級別。然而， 覆晶技術已經成爲更高的輸入/輸出（!/〇)墊數量以及更高的時鐘速率 的所選技術。這個趨勢不僅僅可以由多數處理器所反映出來，而且， 咼端特殊應用積體電路(Application-Specific Integrated Circuit, ASIC)以 及數位訊號處理器(Digital Signal Processor，DSP)也使用覆晶技術組 裝。但是，主流（mainstream)封裝仍然是線接合，因爲對於小於5〇〇 個I/O墊的裝置來説，線接合的價格優勢仍然明顯。當覆晶裝配 (assembly)使高效能裝置受益時，對於多數的主流應用而言，成本 201112387 就成爲了巨大的挑戰。因此，業界仍然將主要的努力放在降低成本上。 " 產品成本、封裝裝置效能以及整體的體積決定了在覆晶與線接合 之間進行選擇以用於1C互連(interconnecting)，當前應用中，線接合的 最大的優勢在於，製程靈活以及打線機(wire bonder)的數量(sheer quantity)較多。因此，線接合已經是成熟的技術，並且其產品製程也已 進行了透徹研究以及被深入理解。因此，打線機已是常用品，並不像 用於覆晶接合的高級裸晶依附平台，此外，線接合技術很靈活。高頻 鲁應科，賴裝設計錢線長度的嚴格控制已經進—步擴展了線接合 封裝的電效能範圍。 儘管如此，隨著最近十年的半導體生減_迅紐展，裸晶體 的體積已經迅速縮小，相似地，裸晶上的I/Q接合_距（PM)也 已經達到了打線機的極限。耻，有必要在㈣提供—種改進的封裝 結構’以將線接合技術的侧壽命延長到下―代技術節點（例如，55肺 鲁、下）U及解决由於裸晶體賴小㈣起的接合侧雜制問題。 【發明内容】 在於提供一種多晶片封裝結構以及形 有鑑於此’本發明目的之— 成多晶片封裝結構的方法。 裸晶 本發明提供一 ，設置在該晶 種夕曰曰片封骏結構，包含:一晶片載體；一半導體 片載體的—裸晶依附面上，其中，多個輸入/輸出塾 201112387 位t半導雜晶之岐者之上；1赌疊層結構，餘該半導體 裸曰曰之上，該重接線疊層結構包含多個麵分配接対 該重新分配接合·接該多個輸人/輪㈣；至少―個接⑼= -個該重新分配接合墊與該晶片載體互連；一二、少 另-個該重新分配接合墊之上；以及 H、、’ 6又置在至少 加八 膠體，封裝該接合線的至少- 部分。 掃明冉概-獅衫以封201112387 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a semiconductor package, and more particularly to a multi-chip package. [Prior Art] As is known in the prior art, there are various chip packaging technologies, such as Ball Grid Array (BGA), Wire Bonding, flip-chip, etc. The die can be placed on the substrate by bonding points on the die and the substrate. In order to ensure the miniaturization and versatility of electronic products or communication devices, semiconductor packages require as small a size as possible, multi-pin connection, high speed, and high functionality. Due to the growing demand for smaller, faster and cheaper electronic devices, the semiconductor industry continues to push the low-cost wire bonding technology to ever higher levels. However, flip chip technology has become the technology of choice for higher input/output (!/〇) pads and higher clock rates. This trend can be reflected not only by most processors, but also by application-specific integrated circuits (ASICs) and digital signal processors (DSPs) using flip chip technology. However, the mainstream package is still wire bonded because the price advantage of wire bonding is still significant for devices with less than 5 I I/O pads. When flip-chip assemblies benefit high-performance devices, the cost of 201112387 is a huge challenge for most mainstream applications. Therefore, the industry still puts major efforts to reduce costs. " Product cost, package performance and overall volume determine the choice between flip chip and wire bond for 1C interconnection. In current applications, the biggest advantage of wire bonding is that process flexibility and wire bonding There are many sheer quantities in the wire bonder. Therefore, wire bonding is already a mature technology, and its product process has been thoroughly studied and understood. Therefore, the wire bonding machine is a common item, unlike the advanced bare die attachment platform for flip chip bonding. In addition, the wire bonding technology is flexible. High-frequency Lu Yingke, strict control of the length of the money line has been extended to expand the range of electrical performance of the wire bond package. Despite this, with the semiconductor production reduction in the last decade, the volume of bare crystals has rapidly shrunk. Similarly, the I/Q junction _ distance (PM) on the bare crystal has reached the limit of the wire machine. Shame, it is necessary to provide an improved package structure in (4) to extend the side life of the wire bonding technology to the next-generation technology node (for example, 55 lungs, lower) U and to solve the bonding due to the bare crystals. Side miscellaneous problems. SUMMARY OF THE INVENTION It is an object to provide a multi-chip package structure and a method of forming a multi-chip package structure in view of the present invention. The present invention provides a substrate disposed on the seed crystal, comprising: a wafer carrier; a semiconductor wafer carrier on the bare die attach side, wherein the plurality of input/output ports 201112387 bits t half Above the conductive crystal; 1 gambling laminated structure, on top of the semiconductor bare ridge, the re-wiring laminated structure includes a plurality of surface distribution interfaces, the redistribution joint, and the plurality of input/wheels (d); at least one (9) = one of the redistribution pads is interconnected with the wafer carrier; one or two more of the redistribution pads; and H, , '6 are placed at least eight gels Encapsulating at least a portion of the bond wire. Sweeping 冉 - - lion shirt to seal
片載體；設置—半導體裸晶在該晶片栽體的-裸晶_面上，^：中曰，I 多個輸入/輸出墊位_半導體裸晶之内或者之上；在辭導體裸晶々 上提供-重接線疊層結構，該重接線疊層結構包含多個重新分配接/ 整，其中，細_分配接合墊她_輸人/輸岭；在至^ 個該重新分配接合麵該晶片載體之間連接至少—個接合線；在至,i 另^該重新分配接合墊上設置―晶片封裝；以及由—膠體封裝剌 合線的至少一部分。 利用本發明’可解決由於裸晶體積減小而引起的接合墊間距限制 問題，魏實現了疊層封裝結構的多晶片封裝，從而提高晶片效能。 【實施方式】 下田述中、”。出了多個特定的細節描述用於透徹理解本發明， 然而，熟習此項技藝者可以了解本發明並不僅限於此。此外，一些孰 知的系統配置和處理步驟在本申請+不再詳細揭露。 201112387 . 相似地，装置實施例的示意圖多為半原理性的，不限於圖式中描 —述的尺寸’而且圖式尺寸個於説明本㈣，_其誇大喃示於圖 式中。當揭露㈣個實關具有制_時，爲了制以及示意，相 似的元件具有相_標號’所屬領域習知技藝者可以了解。所以在後 續的圖式中，不進行贅述。 請參閱第！圖以及第2圖。第！圖為根據本發明一個實施例的示 ♦例的擴散型(fan_out ty㈨晶圓級封裝結構(Wafer Levd心㈣體)1 的平面示意圖。第2圖為第丨圖中沿著線w，的擴散型wlpI的截面 示意圖。如第1圖以及第2圖所示，微型WLP1包含半導體裸晶1〇, 射，半_裸晶1〇包含-個主動裸晶面（activedieface)伽以及 背面（backsidesurface)勘。多個輸入/輸出替12設置在 :〇的主動裸晶面l〇a上。如第i圖所示，多個輸入/輸出塾12可以沿 著半導體裸晶1G的四邊以多列（_)設置，例如，可以為三列。 當然’輸入/輸出塾12的列數僅用於説明本發明。例如，立他實 施例中，輸入/輸出塾12可以排佈為兩列或者四列。輸入/輸出塾12 在主動裸晶面10a上，以緊密的塾間距彼此接近的排佈，而緊密的塾 間距可以超出高級打線機的限制。本發明的目的之一就在於處理由於 裸晶體積縮小而產生的此問題。 如第2圖所示，本實施例提供支援、结構（supportstructure) 10包 圍（—ass)半導體裸晶10。較優地，支援結構％包含膠餅(祕叩 201112387 compound)。支援結構ι6可以具有頂面16a，而頂面16a與主動裸晶 面l〇a實質上齊平（flush)。舉例説明，除了輸入/輸出墊12形成的主 動裸晶面10a，支援結構16包圍住半導體裸晶10的其他表面。Chip carrier; setting—semiconductor die on the die-side of the wafer carrier, ^: mid-turn, I multiple input/output pads _ within or above the semiconductor die; Providing a rewiring laminate structure comprising a plurality of re-distribution connections, wherein the thin-distribution bonding pad is her/input/transmission; the wafer is transferred to the re-distribution bonding surface At least one bonding wire is connected between the carriers; at the same time, the redistribution bonding pad is provided with a "wafer package"; and at least a portion of the bonding wire is encapsulated by the -colloid. With the present invention, the problem of the pad pitch limitation due to the reduction in the volume of the die can be solved, and the multi-chip package of the stacked package structure is realized, thereby improving the wafer performance. [Embodiment] The following detailed description is provided to provide a thorough understanding of the present invention. However, those skilled in the art will understand that the invention is not limited thereto. In addition, some well-known system configurations and The processing steps are not disclosed in detail in the present application. 201112387. Similarly, the schematic diagrams of the device embodiments are mostly semi-principle, and are not limited to the dimensions described in the drawings, and the dimensions are shown in the description (4), _ The exaggeration is shown in the drawings. When the disclosure of (four) real-times has a system, similar elements have the same phase as the ones of the art in the art, so in the following figures, Please refer to Fig. 2 and Fig. 2. Fig. is a plan view showing a diffusion type (fan_out ty) wafer level package structure (Wafer Levd core) according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of the diffusion type wlpI along the line w in the second diagram. As shown in Fig. 1 and Fig. 2, the micro WLP1 includes a semiconductor bare crystal, a shot, and a half-small crystal. Contains - active bare Activedieface gamma and backside surface survey. Multiple inputs/outputs are placed on the active bare plane l〇a of 〇. As shown in Figure i, multiple input/output 塾12 can be along The four sides of the semiconductor bare crystal 1G are arranged in a plurality of columns (_), for example, may be three columns. Of course, the number of columns of the input/output ports 12 is only for explaining the present invention. For example, in the embodiment, input/output塾12 can be arranged in two or four columns. The input/output ports 12 are arranged on the active bare faces 10a in close proximity to each other at a close turn spacing, and the tight pitch can exceed the limits of the advanced wire machine. One of the purposes of this is to deal with this problem due to the shrinkage of the bare crystal. As shown in Fig. 2, this embodiment provides support, support structure 10 to surround (-ass) the semiconductor die 10. Preferably, The support structure % comprises a rubber cake (secret 201112387 compound). The support structure ι6 may have a top surface 16a, and the top surface 16a is substantially flush with the active bare crystal surface l〇a. For example, except for the input/output pad 12 formed active bare face 10 a, the support structure 16 surrounds the other surfaces of the semiconductor die 10.
仍然參閱第2圖’在主動裸晶面10a上以及在支援結構16的頂面 16a上^供重接線疊層結構（revvjringiaminatestructure) 2〇。重接線暴 層結構20包含重新佈線金屬層（re_r〇utecj metal layer ) 21，而重新佈 線金屬層21开>成於電介質層（dieiectric iayer) 24中，其中電介質声 24可以為例如氧化石夕（silic〇n〇xide)、氮化石夕（silic〇nn_e)、聚 亞醢胺(polyimide)、基於光敏苯并环丁烯的聚合體電介質 (benzocyclobutane，BCB-based polymer dielectric)以及上述幾者的組，Still referring to Fig. 2', a rewiring laminated structure (revvjringiaminate structure) is provided on the active bare face 10a and on the top surface 16a of the support structure 16. The rewiring layer structure 20 includes a re-wiring metal layer 21, and the rewiring metal layer 21 is formed in a dielectric layer 24, wherein the dielectric sound 24 may be, for example, an oxidized stone eve. (silic〇n〇xide), nitrite 〇_e, polyimide, benzocyclobutane-based BCB-based polymer dielectric, and the like group,
(combination)，或者任何其它適合的材料。重新佈線金屬層η可^ 由銅、鋁或者上述兩者的組合而形成，或者其它任何適合的材料。重 接線疊層結構20中的重新佈線金屬層21將半導體裸晶1〇之内或者戈 上的輸入/輸出塾12重新分配（redistribute)以在電介質屛之中戈 者之上形成重新分配接合墊（redistributi〇nbandpad) 22。根據本發甲 的-個實施例，簡分配接合墊22可以由銅、、鈦= (mckel)、M (vanadium)或者上述幾者敝合而形成，或者其它书 何合適的材料。輸人/輸岭丨2可糾銅、喊者上述兩者的組合匕而3 形成，或者其它任何適合的材料。可以理解的是，如第2 ^. 1 * 腹1 第8廣 w田述的重新分配接合墊22賴面結構，僅用於説明本發明。重新夕 配接合墊22的其他配置，只要可以耦接到輸入/輸出墊^就可以使女 用。舉例説明，第9圖以及第10圖為重新分配接合墊22的—^^_立 叫、眉 8 201112387 變形’其中如第9圖所示的重新分配接合墊22可作為重新佈線金屬層 21的一部分，或者與第10圖所示其它材料的組合。 根據本發明的一個實施例，多個重新分配接合墊22可以排佈為多 列例如兩列或者三列，多個重新分配接合墊22可以投射（pr〇ject) 在半導體裸晶10的裸晶側面（dieedge) l〇c之外（beyond)。在另一 個實施例中’僅有一部分重新分配接合塾22投射在裸晶側面10c之 外。而在再一個實施例中’重新分配接合墊22的至少一部分不投射在 鲁裸晶側® l〇c之外。在再一個實施例中，沒有重新分配接合塾22投射 在裸晶側面l〇c之外。可以理解的是，輸入/輸出墊12的列的數目可 以與重新分配接合墊22的列的數目不同。舉例説明，輸入/輸出墊12 可以放置成爲四列，而重新分配接合墊22則可以排佈為三列。 根據本發明的另一個實施例，半導體裸晶1〇可以為電源管理單元 或者電源1C，其中排佈在主動裸晶面i〇a上内側（inner)列的一些電 馨源墊或者接地墊，通過重接線疊層結構2〇的方式，可以在電介質層 24上重新分配為重新分配接合墊22的多列的外側（〇uter)列，或者 最外側（outmost)列。經由此操作，晶片效能就可以提高。換言之， 在此發明中，接合塾就可以重新分配以適應封裝以及效能要求。 第3圖為製造如第2圖所示的擴散型WLP1的步驟的示意圖。如 第3圖所示’第1圖所示的擴散型WLP1的製造可分為以下幾個階段: 晶圓切割(dicing)(步驟51)、晶圓重新配置（步驟52)、重新分配（步 驟53)以及封裝成型(singulation)(步驟54)。在封裝成型之後，可選 201112387 擇地，可實施抛光製程（polishingprocess)(步驟55)以去除一部分 膠餅’因此可以將半導體裸晶10的背面10b暴露出來。如果在步驟 51至步驟54中，背面10b已經暴露出來的話，或者如果不希望其暴 露出來的話，那麽步驟55就可以省略。可以理解的是，可以使用其它 方法而製造擴散型WLP。使用重新分配技術的不同的公司，可能使用 不同的材料以及製程實現擴散型WLP。儘管如此，所需步驟都是相似 的。 重新分配層技術使用額外的步驟而擴展了傳統的晶圓製造 (fabrication)製程，其中’額外的步驟為將導電重佈(conductive reiOuting) 以及互連系統沉積(deposit)到晶圓的每個裝置（例如，晶片）上。擴 展傳統的晶圓製造製程可以使用類似以及相容的光刻 (photolkhography)以及薄膜沉積（thin film deposition)的技術而達 到，其中’光刻以及薄膜沉積技術在裝置製造自身中應用。額外層別 的互連（additional layer of interconnection )可將每個晶片的外圍連接 (peripheral contact)墊重新分配為設置在晶片表面的導電墊的區域陣 歹丨J ( area array ) ° 第4圖為根據本發明的另一個實施例的，擴散型WLP la截面示 意圖。如第4圖所示，相似地，擴散型WLp la包含半導體裸晶1〇， 其中’半導體裸晶10具有主動裸晶面l〇a以及背面10b。而在半導體 裸晶10的主動裸晶面l〇a上可提供多個輸入/輸出墊12 (例如鋁接合 墊）。輸入/輸出墊12可以沿著半導體裸晶1〇的4個裸晶側面他而 201112387 設置。 本實把例提供支援結構1ό包圍半導體裸晶1Q。較優地，支援結 構16可以包含具錄好機械強度以及與半導體裸晶ίο間優良的點結 (adhesion)力的膠餅。支援結構16可以具有頂面⑹，而頂面如 與主動裸晶面l〇a實質上齊平。在此實施例中，支援結構^僅覆蓋半 導體裸晶10的裸晶側面10c。支援結構16不包圍背面勸背面勘 暴露出來。 相似地’在絲裸晶面1Ga以及支援結構16的頂面⑹上提供重 接線疊層結構2G’其中重接線疊層結構20包含形成在電介質層24上 的重新佈線金屬層21。重接線疊層結構2()中的顏佈線金屬層2ι將 半導體裸阳10之喊者之上的錢輸人/輸出㈣重新分配，以在電 介質層24巾或者電介㈣24上形成重新分配接合塾22。(combination), or any other suitable material. The rewiring metal layer η can be formed of copper, aluminum, or a combination of the two, or any other suitable material. The rewiring metal layer 21 in the rewiring stack structure 20 redistributes the input/output ports 12 within or within the semiconductor die to form a redistribution bond pad over the dielectric germanium (redistributi〇nbandpad) 22. According to an embodiment of the present hairpin, the simple dispensing pad 22 may be formed of copper, titanium = (mckel), M (vanadium) or a combination of the above, or other suitable materials. The input/transmission ridge 2 can be used to correct copper, the combination of the above two, and 3, or any other suitable material. It can be understood that the structure of the redistribution joint pad 22 as described in the second paragraph of the second paragraph is only used to explain the present invention. Other configurations of the bonding pad 22 can be made female as long as it can be coupled to the input/output pad. For example, FIG. 9 and FIG. 10 are the redistribution of the bonding pad 22, and the eyebrow 8 201112387 is deformed. The redistribution bonding pad 22 as shown in FIG. 9 can be used as the rewiring metal layer 21. Part, or combination with other materials shown in Figure 10. According to one embodiment of the invention, the plurality of redistribution bond pads 22 may be arranged in a plurality of columns, such as two columns or three columns, and the plurality of redistribution bond pads 22 may project a die in the semiconductor die 10 The side of the diedie l〇c (beyond). In another embodiment, only a portion of the redistribution joint 22 is projected outside of the bare side 10c. In yet another embodiment, at least a portion of the redistribution bond pad 22 is not projected beyond the bare die side ® l〇c. In still another embodiment, no re-distribution joint 22 is projected beyond the bare side l〇c. It will be appreciated that the number of columns of input/output pads 12 may be different than the number of columns in which bond pads 22 are reassigned. By way of example, the input/output pads 12 can be placed in four columns, and the redistribution bond pads 22 can be arranged in three columns. According to another embodiment of the present invention, the semiconductor die 1 can be a power management unit or a power supply 1C, wherein some of the electric source pads or ground pads arranged on the inner column of the active bare face i〇a are arranged. The outer rows of the plurality of columns of the bond pads 22, or the outermost columns, can be redistributed over the dielectric layer 24 by means of a rewiring laminate structure 2''. Through this operation, the wafer performance can be improved. In other words, in this invention, the joints can be redistributed to accommodate packaging and performance requirements. Fig. 3 is a schematic view showing the steps of manufacturing the diffusion type WLP 1 shown in Fig. 2. As shown in Fig. 3, the manufacture of the diffusion type WLP1 shown in Fig. 1 can be divided into the following stages: wafer dicing (step 51), wafer reconfiguration (step 52), and reallocation (step) 53) and singulation (step 54). After package molding, optional 201112387, a polishing process (step 55) may be performed to remove a portion of the gumcake' so that the backside 10b of the semiconductor die 10 may be exposed. If in step 51 to step 54, the back side 10b has been exposed, or if it is not desired to be exposed, then step 55 can be omitted. It will be appreciated that other methods may be used to fabricate the diffusion type WLP. Different companies that use redistribution techniques may use different materials and processes to implement a diffused WLP. Still, the steps required are similar. The redistribution layer technology extends the traditional wafer fabrication process with additional steps, where 'an additional step is to deposit a conductive reiOuting and interconnect system to each device of the wafer. (for example, on a wafer). Extending traditional wafer fabrication processes can be achieved using similar and compatible techniques of photolkhography and thin film deposition, where 'lithography and thin film deposition techniques are applied in device fabrication itself. An additional layer of interconnection can redistribute the peripheral contact pads of each wafer into an area array of conductive pads disposed on the surface of the wafer. A schematic cross-sectional view of a diffusion type WLP la according to another embodiment of the present invention. As shown in Fig. 4, similarly, the diffusion type WLp la includes a semiconductor die 1 , wherein the semiconductor die 10 has an active bare face 10a and a back surface 10b. A plurality of input/output pads 12 (e.g., aluminum bond pads) may be provided on the active bare face 10a of the semiconductor die 10. The input/output pad 12 can be placed along the four bare sides of the semiconductor die 12011 and 201112387. This example provides a support structure 1 to surround the semiconductor die 1Q. Preferably, the support structure 16 can comprise a cake having a mechanical strength and an excellent adhesion force with the semiconductor die. The support structure 16 can have a top surface (6) while the top surface is substantially flush with the active bare surface 10a. In this embodiment, the support structure ^ covers only the bare side 10c of the semiconductor die 10. The support structure 16 is not surrounded by the back side and is exposed. Similarly, a re-wiring laminated structure 2G' is provided on the bare side 1Ga of the wire and the top surface (6) of the support structure 16 wherein the re-wiring laminated structure 20 includes the rewiring metal layer 21 formed on the dielectric layer 24. The wiring metal layer 2ι in the rewiring laminate structure 2() redistributes the money input/output (4) on the shunt of the semiconductor bare yang 10 to form a redistribution joint on the dielectric layer 24 or the dielectric (4) 24.塾 22.
第^圖為根據本發明的再一個實施例的示範線接合晶片封裝觸 的截面不思圖如第5圖所不’具有裸晶面收以及裸晶側面心的 半導體裸晶1G ’設置在晶片載體（啊earrie相的裸晶依附面⑽也 surface) 40a上’其中’晶片載體4〇可以為例如封裝基板或者印刷電 路板’其中，多個輸入/輸出塾12位於半導體裸晶ι〇上或者之内。支 援結構〗6可以⑽半導體裸晶1G。以援結構16具有頂面⑹，而 頂面16a與主動裸晶面i0a實質上齊平。 ’重接線疊層結構20包 半導體裸晶10上提供重接線疊層結構2〇 201112387 含多個重新分配接合墊22，而多個重新分配接合墊22可以投射在裸 晶侧面10c之外，或者也可不投射在裸晶側面1〇c之外。使用多個接 合線（bond wire) 50將重新分配接合墊22與晶片載體4〇上的對應的 接合墊42互連起來。提供膠體（m〇Mcap) 6〇以封裝（enc叩如1扣£) 至少半導體裸晶10、重接線疊層結構2〇、支援結構16以及接合線5〇。 根據此貫把例，膠體60以及支援結構π可以由不同的膠餅製成。 根據此實施例，接合線50可以包含金、銅或者上述兩者的組合， 或者其它適合的材料。根據本發明的—個實關，麵分配接合墊22 _ 由銅形成，而接合線50為銅線。 由於半導體裸晶10上的具有緊密塾間距的輸入/輸出塾12重新分 配在外圍（peripheral)，投射在裸晶側面收之外的外側區域（〇咖 匪> 因此重新分配接合塾22具有線接合制的寬鬆的塾間距。 但是，如前所述，根據設計要求’重新分配接合墊22可以投射在裸晶 側面10c之外，或者不投射在裸晶側面1〇c之外。 曰曰 第6圖為根據本發明再一個實施例的線接合晶片封裝職的截面 示意圖。如第6圖所示’經由枯結層（adhesivelaye〇 152，擴散型 WLP la設置在晶片載體（在此實施例中’例如導線架i州的裸晶依 附面或者裸晶墊14〇a上，其中擴散型WLp u包括具有主動裸晶面恤 和裸晶侧面10c的半導體裸晶1〇，多個輸入/輸出塾12位於半導體裸 晶ίο之内或者之上。擴散型WLP la可包含支援結構16，支祕構-16包圍半導體裸晶1()。支援結構16具有頂面⑹，而頂面恤齡 12 201112387 動裸晶面10a實質上齊平。 ' 擴散型WLpla進一步包含重接線疊層結構20，而重接線疊層結 構20在半導體裸晶1〇上以及支援結構16的頂面1如上。重接線疊層 結構20可以在封裝廠（assembly house)製造。重接線疊層結構20包 含多個重新分配接合墊22 ’而多個重新分配接合墊22可以投射在裸 晶側面10c之外，並且重新分配接合墊22可以具有用於線接合應用的 寬鬆的墊間距。在另一實施例中，根據於設計要求，重新分配接合墊 鲁22可不投射在裸晶側面1Ge之外，或者僅其巾—部分投射在裸晶側面 i〇c之外。在再一個實施例中，至少重新分配接合墊22的一部分不投 射在裸晶側面l〇c之外。 使用多個接合線50將重新分配接合墊22與導線架(leadframe) 14〇 的對應内側引腳（innerlead) 142互連起來。膠體60封裝至少半導體 裸晶1〇、重接線疊層結構20、支援結構16、裸晶墊14〇a、内側引聊 鲁H2以及接合線50。根據此實施例，接合線5〇可以包含金、銅，或者 上述二者的組合’或者其它適合的材料。 第7圖為根據本發明的再一個實施例的線接合晶片封裝1〇〇1)的戴 面示思圖。如第7圖所示，通過钻結層152，包含半導體裸晶的擴 政型WLP la設置在導線架140的裸晶墊i4〇a上，而半導體裸晶 具有主動裸晶面l〇a以及裸晶側面i〇c，其中，多個輸入/輸出墊I]位 於半導體裸晶10之内或者之上。擴散型WLP la可包括包圍半導體裸 晶10的支援結構16,其中支援結構16具有頂面16a，而頂面16a與 13 201112387 主動裸晶面l〇a實質上齊平。擴散型^^〇>13進一步包含在半導體裸 晶10以及支援結構16之頂面16a上的重接線疊層結構20。相似地， 重接線疊層結構20包含多個重新分配接合墊22，而多個重新分配接 合墊22可以投射在裸晶側面i〇c之外，或者不投射在裸晶側面i〇c之 外〇 多個接合線50用於將重新分配接合墊22與導線架14〇的内側引 腳142互連起來。接合線5〇可以包含金、銅、或者上述二者的組合， 或者其它適合的材料。膠體60封裝至少半導體裸晶1〇、重接線疊層 結構20、支援結構16、内侧引腳142以及接合線50。根據此實施例， 裸晶墊140a的底面14〇b不由膠體60包圍，因此，可以外露於空氣中。 這樣的封裝結構可以稱之爲外露式墊（EXp〇se(j_pad，E_pad )薄型四方 扁平封裝（Low-Profile Quad Hat Package, LQFP )。 第8圖為根據本發明的再一個實施例的線接合晶片封裝1〇〇c的截 面示意圖。如第8圖所示，包含半導體裸晶1〇的擴散型WLpia，設 置在導線架240的裸晶墊24㈨上，而半導體裸晶1〇具有主動裸晶面 l〇a以及裸晶側面i〇c，其中，多個輸入/輸出墊12位於半導體裸晶1〇 之内或者之上。裸晶墊240a進一步可以包含凹腔（recess) 24〇c，而 半導體裸晶ίο可以設置在凹腔240(；内。擴散型WLPla可以包含支 援結構16,而支援結構16包圍半導體裸晶1〇。支援結構16可以具有 頂面16a ’而頂面16a與主動裸晶面i〇a實質上齊平。擴散型WLp la 進一步包含在半導體裸晶10上的重接線疊層結構2〇。相似地，重接 201112387 線疊層結構2G包含多個重新分配接合塾22，而多個重新分配接合塾 22可以投射在裸晶側面l〇c之外，或者不投射在裸晶側面收之外。 多個接合線5〇用於將重新分配接合塾22與導線架的對應的 互連塾242互連起來。接合線50可以包含金、銅、或者上述二者_ 合’或者其它適合的·。膠體6G封裝至少轉體裸晶1()、重接線 疊層結構20、支援結構16、裸晶墊24〇a的上部、互連塾242的上部 以及接合線50。如第8圖所示的封裝配置可以稱之為四方扁平無引腳 #(quad flat麵-leaded，QFN)封褒或者先進四方扁平無引腳㈤職以 quad flat non-leaded，aQFN)封裝結構。 在其它實施例中，如第2 @、第4圖至第1G圖所示的支援結構 16可以省略。在其他實關巾，在半導體裸晶1()上可以具有另一個 半導_晶。另-個半導體裸晶可以經由至少—接合線崎接到半導 體裸晶10。在其他實施例中，另-個半導體裸晶可以麵接到半導體裸 春晶10中不投射到裸晶側面l〇c之外的重新分配接合塾22。 第11圖為根據本發明再一個實施例的疊層封裝 (PaCkage-〇n-package，POP)結構的多晶片封裝2〇〇的戴面示意圖，其中 相同的標號代表相同的區域、層或者元件。如第η圖所示，多晶片封 裝200包括擴散型WLPlb’其中擴散型WLPlb包括具有裸晶面1〇& 以及裸晶側面10c的半導體裸晶1〇。擴散型WLPlbK置在晶片載體 40的裸晶依附面40a上，晶片載體40可例如封裝基板、印刷電路板 15 201112387 2導線架’其中’多個輸入/輸出塾12和仏位於半導體裸晶ι〇的 面1〇a上或者位於半導體裸晶10内。支援結構膠餅) =半導體裸晶K)。支援結構16具有頂面16a，且頂面 晶面10a實質上齊平。 功俅 ，+導體裸晶1G上提供娜_結構Μ，重接線疊層結制 包t夕個重新分配接合塾22和瓜，用於輸入/輸出塾12和12a。重 =配接合墊22和22a可以投射在裸晶側面⑽之外，或者也可不投 晶側面W之外。使用至少一個接合線料至少—個重新分配 〇 22和22a與晶片載體40上對應的接合墊42互連起來。 提供膠體60以封裝至少—部分接合線％，並進—步封裝半導體 曰0重接線疊層結構2〇和支援結構16的至少一部分。根據此實 施例’膠體㈣及支援結構16可以由不__^根據另一實 知例’接合線5〇可吨含金、銅或者上述兩者的組合，或者其它適合 的材料。根據本發_另—實施例，重新分配接合塾Μ由銅形成，而 接合線50為銅線。 ，輸入/輸出塾12a位於半導體裸晶1〇的主動裸晶面恤上或者位 於轉體裸晶10内。輸人/輸出墊12a通過重新佈線層 Layer’ RDL) 21a重新分配至各自的重新分配接合塾咖。膠體财具 有空腔60a以暴露重新分配接合塾22a。晶片封裝^設置於空腔· 内部的擴散型WLP lb上。在本實施例中，晶片封裝化通過凸塊 (bumP)222與擴散型WLpib電連接，其中凸塊奶接合至重新分配 201112387 接合墊22a。在另一個實施例中，晶片封裝ic可通過銅桂與擴散型 • WLP lb電連接，其中銅柱接合至重新分配接合墊22a。 重新分配接合墊22和22a可投射至裸晶侧面1〇c之外，也可不投 射在裸晶側面10c之外。在一個實施例中，重新分配接合墊22和2仏 投射至裸晶側面10c之外。在另一個實施例中，只有部分重新分配接 合墊22和22a投射至裸晶側面l〇c之外。在另一實施例中，至少有部 分重新分配接合墊22和22a不投射至裸晶側面1〇c之外。以及在再一 籲實施例中’沒有重新分配接合墊22和22a投射至裸晶側面i〇c之外。 可對重新分配接合塾22和22a進行重新分配，以最好的滿足封裝和效 能需求。 > 第12圖為根據本發明另-個實施例的疊層封裝結構的多晶片封 裝200a的戴面示意圖’其中相同的標號代表相同的區域、層或者元 件。第12圖中所示的多晶片封裝2〇〇a與第u圖中所示的多晶片封裝 鲁2〇0的-個主要區別在於多晶片封裝職的晶片封裝^設置於由膠 體6〇封裝的凸塊322上。凸塊322將晶片封裝卜的凸塊從與擴散 型WLP lb的重新分配接合墊瓜電連接。在另一個實施例中，凸塊 222、凸塊322或者二者同時可由銅柱代替，因此晶片封裝卜可通過 銅柱與重新分配接合塾22a電連接。根據本實施例，在膠體 空脓。 又负 第13圖為根據本發明另—個實施綱疊層封裝結構的多晶片封 裝200b賴面示意圖，其中相同的標號代表相同的區域、層或者元 17 201112387 件。如第13圖所示，多晶片封裝200b包括擴散型WLP lb，其中擴 月文型WLP lb包括具有裸晶面1〇a以及裸晶側面1〇c的半導體裸晶 ⑴擴散型WLP lb設置在晶片載體4〇的裸晶依附面他上，晶片載 體40可例如封裝基板、_電路板或者導線架，其中，多個輸入/輸 出墊12和12a位於半導體裸晶1〇之上或者位於半導體裸晶1〇内。= 援結構16(例如膠餅）㈣半導體裸晶1〇。支援結構16具有頂面· 且頂面16a與主動裸晶面1〇a實質上齊平。 在半導體裸晶10上提供重接線疊層結構2〇,重接線疊層結構2〇 # 包含多個重新分配接合墊22和22a，用於輸入/輸出塾以和仏。重 新分配接合墊22和22a可以投射在裸晶側面1〇c之外，或者也可不投 射在裸晶側面l0c之外。使用至少一健合線5〇將至少一個重新分配 接合墊22與晶片健4G上對應的接合$ 42互連起輸出塾 12a位於半導體裸晶1〇的主動裸晶面1〇a上或者位於半導體裸晶 内。輸入/輸出塾i2a通過重新佈線層21a重新分配至各自的重新分配 接合塾22a。在本實施例中，晶片封裝卜通過凸塊222與擴散型術 lb電連接’其中凸塊222接合至重新分配接合塾22&。在另一個實施· 例中’晶片封震1c可通過銅柱與擴散型WLp 合至重新分配接合塾22a。 戰，、中銅柱接 提供膠體60㈣敍少-部分接合線％，並進—頻裝 ^晶川、重接線疊層結構2〇、支援結構16的至少_部分，並進—牛 憤晶片封裝lc的-部分。根據—個實施例，膠體6〇以及支援处構 201112387 可以料同的賴製成。根據另—實施例，接合線料以包含金、 銅或者上述兩者的組合’或者其它適合的材料。根據本發明的另一實 -施例，重新分配接合塾22由銅形成，而接合線5〇為銅線。 第14圖為根據本發明另一個實施例的導線架多晶片封裝臟的 截面示意圖。如第14圖所示，擴散型體lb包括具有裸晶面10a 以及裸晶側面H)C的半導體裸晶1〇。且經由枯結層152，擴散型wLp lb設置在導線架140的裸晶依附面或者裸晶整顺上，其中，多個 鲁輸入/輸出塾12和12a位於半導體裸晶1〇的裸晶面1〇a上或者半導體 裸晶 Η) 半導體裸晶10。支援結構16具有頂面16a，而頂面16a與主動裸晶面 10a實質上齊平。 擴散型WLP lb進-步包含重接線疊層結構2〇，而重接線疊層結 構20在半導體裸晶10上以及支援結構16的頂面16&上。重接線疊層 籲結構2〇可以在封裝薇製造。重接線疊層結構Μ包含多個重新分配接 。墊22和22a，多個重新分配接合塾22和22a可以投射在裸晶側面 10c之外’也可以不投射在裸晶側面1〇c之外，並且重新分配接合墊 22可以具有用於線接合應㈣寬鬆的賴距。多個輸人/輸出塾仏 位於半導體裸晶1〇的裸晶面1〇a上或者半導體裸晶1〇之内。輸入/輸 出墊12a通過重新佈線層(Re_distribute Layer，2U重新分配至各 自的重新分配接合墊22a。在本實施例中，晶片封裝lc設置在擴散型 WLP lb上’並通過凸塊(bump)222與擴散型WLp比電連接’其中凸 201112387 ==:=::::: 使用至J -個接合線5G將至少—個重新分配接合塾Μ與導 140的對應_引腳142互連起來。膠體⑼封裝至少—部分接合: 50 ’並且進-步封裝半導體裸晶⑴、重接線疊層結構如、支援沾播 16、裸晶墊施、内側引腳142中的—部分，並且進—步封裂曰: 裝1C的-部分。根據此實施例，接合線5〇可以包含金、銅1卜 述二者的組合，或者其它適合的材料。 第15圖為根據本發明另一個實施例的Epad LQFp多 2_的截面示意圖。如第15圖所示，擴散型wLp ib包括^有裸f 面10a以及裸晶側面10c的半導體裸晶1〇。且經由枯結層152， 变 lb設置在導線架140的裸晶塾施上，其中，多個輪入= 墊i2和歸於半導體裸晶1〇之上或者半導體裸晶ι〇之 暫lb可包含支援結構16，支援結構16包圍轉體裸日日日ω。支^ 構16具有頂面16a ’而頂面16a與主動裸晶面收實質上齊平。。 擴散型WLP lb進-步包含重接線疊層結構2〇，而重接線叠層结 構20在半導體裸晶1〇上以及支援結構16的頂面恤上。重接線 結構20包含多個重新分配接合塾22和瓜’多個重新分配接合^ 和22a可以投射在裸晶側面10c之外，也可以不投射在裸晶側面收 之外。多個輸入/輸出塾以位於半導體裸晶1〇的裸晶面伽上 20 201112387 半導體裸晶ίο之内。輸入/輸出墊12a通過重新佈線層21a重新分配 至各自的重新分配接合墊22a。在本實施例中，晶片封裝lc設置在擴 散型WLP lb上，並通過凸塊222與擴散型WLP lb電連接，其中凸 塊222接合至重新分配接合墊22a。在另一個實施例中，晶片封裝卜 可通過銅柱與擴散型WLP lb電連接，其中銅柱接合至重新分配接合 墊 22a。 ° 使用至少一個接合線50將至少一個重新分配接合墊22與導線架 • 140的對應内側引腳142互連起來。接合線5〇可以包含金 '銅，或者 上述二者的組合，或者其它適合的材料。膠體60封裝接合線5〇的至 夕。卩刀，並且進一步封裝半導體裸晶10、重接線疊層結構20、支援 結構16、裸晶墊140a、内側引腳142中的一部分，並且進一步封裝晶 片封裝lc的一部分。根據此實施例，膠體6〇不封裝裸晶墊14加的底 面140b，底面140b暴露在空氣中。 _ • 第16圖為根據本發明另一個實施例的QFN多晶片封裝2〇〇e的截 面示意圖。如第16圖所示，擴散型WLP lb包括具有裸晶面1〇a以及 裸晶側面IGe的半導體裸晶1G。且擴散型乳卩lb設置在導線架· 的裸曰曰墊240a上，其中，多個輸入/輸出墊12和12a位於半導體裸晶 10之上或者半導體裸晶1Q之内。裸日日日塾·a進_步可以包含凹腔 (reCeSS )240c ’而半導體裸晶1 〇可以設置在凹腔240c内。擴散型WLP lb可以包含支援結構16，而支援結構16包圍半導體裸㉟ω。支援結 構16可以具有頂面16a，而頂面他與主動裸晶面i〇a實質上齊平。 21 201112387 擴散型WLP lb進-步包含在半導體裸晶1〇上的重接線疊層結構 20。重接線叠層結構20包含多個重新分配接合墊22和22a，而多個 重新分配接合墊22和22a可以投射在裸晶侧面1〇c之外，或者不投射 在稞晶側面10c之外。輸入/輸出塾12a位於半導體裸晶⑴的主動裸 b曰面10a之上或者半導體裸晶1〇之内。輸入/輸出墊以通過重新佈 線層21a f新分配至各自的重新分配接合墊仏。在本實施例中，晶 片封裝lc設置在擴散型WLP lb上，並通過凸塊222與擴散型術 lb電連接’其中凸塊222接合至重新分配接合塾瓜。在另一個實施 例中’晶片封裝lc可通過銅柱與擴散型WLp lb電連接，其中鋼柱接 合至重新分配接合墊22a。 使用至少-個接合線5〇將至少一個重新分配接合塾^與導線架 240的對應互連引腳242互連起來。接合線％可以包含金、銅，或者 上述二者的組合，或者其它適合的材料。_⑼封裝至少—部分接合 、’’复〇並且進步封裝半導體裸曰曰曰10、重接線疊層結構Μ、支援結 構16、裸晶塾240a的上部、互連引腳242的上部中的一部分，並且 進一步封裝晶片封裝lc的至少一部分。 第Π圖為根據本發明另一個實施例的具有疊層封I结構 片封裝200f的截面示意圖。如第17圖所示，擴散型饥仏包括^ 有裸晶面以及裸晶側面1〇c的半導體裸晶1〇，且經由枯結声❿ =散型WLP lb設置在導線架⑽的裸晶依附面或者裸㈣^上， 、中’多個輸入/輸出墊12和12a位於半雜裸晶1〇的裸晶面收之 22 201112387 上或者半導體裸晶1〇之内。擴勒划 —而古鮮椹心阁 可以包含支援結構l —而頂面吨動裸=二f可以具有㈣， =WUMb進―嫩在半物晶iq上嫩結構Μ的 W⑹上的重接線疊層結構2〇。重接線疊層結構2〇可以在封裝薇 製造。重接線疊層結構2〇包含㈣錄分配接合塾22和瓜，而多 個重新分配接合独和22a可峨射在裸晶側面⑽之外，或者不投 射在裸晶側面10c之外。並且重新分配接合塾22可以具有用於線接: 應用的寬鬆的塾間距。輸入/輸出塾12a位於半料裸晶⑴的主動裸 晶面l〇a之上或者轉體裸晶1〇之内。輸入/輸出塾仏通過重新佈 線層21a重新分配至各自的重新分配接合塾瓜。膠體⑹中具有空腔 6〇a以暴露重新分配接合塾22a。晶片封们c設置於空腔_内部= 擴散型WLP lb上。在本實施例中，晶片封裝lc通過凸塊從與擴散 型WLP lb電連接，其中凸塊222接合至重新分配接合墊22a。在另 一個貫施例中，晶片封裝1C可通過銅柱與擴散型WLp lb電連接，其 中銅柱接合至重新分配接合墊22a。 使用至少一個接合線50將至少一個重新分配接合墊22與導線架 140的對應内側引腳142互連起來。膠體60封裝至少一部分接合線 。根據本實施例，接合線50可以包含金、銅，或者上述二者的組合， 或者其它適合的材料。 第18圖為根據本發明另一個實施例的具有疊層封裝結構的E_pad 23 201112387 LQFP多晶片封裝200g的戴面示意圖。如第18圖所示，擴散型肌p ib包括具有裸晶自10&以及裸晶側面1〇c的半導體裸晶ι〇，且經由枯. 結層152，擴散型WLP lb設置在導線架14〇的裸晶塾隐上其中，_ 多個輸入/輸出墊12和12a位於半導體裸晶1〇的裸晶面伽之上或者 半導體裸晶ίο之内。擴散型WLP lb可吨含支援賴16，而支援 結構16包圍半導體裸晶10。支援結構16可以具有頂面恤，而頂面 16a與主動裸晶面i〇a實質上齊平。 擴散型WLP lb進-步包含在半導體裸晶1〇上和支援結構16的籲 頂面16a上的重接線疊層、结構2〇。重接線疊層結構包含多個重新 分配接合墊22和22a ’而多個重新分配接合塾22和22a可以投射在 裸晶側© 10c之外，或者不投射在裸晶_ 1〇c之外。輸入/輸出塾仏 位於半導體裸晶1〇的主動裸晶面1〇a之上或者半導體裸晶ι〇之内。 輸入/輸出塾12a通過重新佈線層21a重新分配至各自的重新分配接合 墊22a。膠體60中具有空腔60a以暴露重新分配接合墊22a。晶片封 裝lc設置於空腔60a内部的擴散型WLp lb上。在本實施例中，晶片 封裝lc通過凸塊222與擴散型WLP lb電連接，其中凸塊222接合至 重新分配接合塾22a。在另-個實施例中，晶片封裝lc可通過鋼柱與 擴散型WLP lb電連接’其中銅柱接合至重新分配接合塾瓜。 使用至少一個接合線50將至少一個重新分配接合墊22與導線架 140的對應内側引腳142互連起來。接合線5〇可以包含金、銅，或者 上述二者的組合，或者其它適合的材料。膠體6〇封裝接合線5〇的至 24 201112387 少一部分。根據本實施例，膠體6〇不封裝裸晶塾喻的底面邊， 底面140b暴露在空氣中。 第19圖為根據本發明另一個實施例的具有疊層封裝結構的_ 多晶片封裝200h的截面示意圖。如第19圖所示，擴散型體化包 括具有裸晶面H)a以及裸晶側面1〇c的半導體裸晶ι〇。且擴散型WLp 1 b設置在導線架24〇的裸晶墊織上，其中，多個輸入/輸出塾】2和 12a位於半導!！裸晶1〇之上或者半導體裸晶ι〇之内。裸晶塾遍進 >步可以包含凹腔（recess)織，而半導體裸曰曰曰1〇可以設置在凹腔 240c内。擴散型WLP lb可以包含支援結構16，而支援結構π包圍 半導體裸曰曰10。支援結構16可以具有頂面16a，而頂面⑽與主動裸 晶面10a實質上齊平。 擴散型WLP lb進-步包含在半導體裸晶1〇上的重接線疊層結構 20。重接線疊層結構2〇包含多個重新分配接合墊22和22a，而多個 _重新分配接合墊22和22a可以投射在裸晶側面10c之外，或者不投射 在裸晶側面10c之外。輸入/輸出墊12a位於半導體裸晶1〇的主動裸 曰曰面10a之上或者半導體裸晶1〇之内。輸入/輸出墊12&通過重新佈 線層21a重新分配至各自的重新分配接合墊22a。膠體6〇中具有空腔 60a以暴路重新分配接合塾22a。晶片封裝ic設置於空腔6〇a内部的 擴散型WLP lb上。在本實施例中’晶片封裝lc通過凸塊222與擴散 型WLP lb電連接’其中凸塊222接合至重新分配接合墊22a。在另 一個貫施例中，晶片封裝lc可通過銅柱與擴散型WLp lb電連接，其 25 201112387 中銅柱接合至重新分配接合墊22a。 使用至少一個接合線50將至少一個重新分配接合墊22與導線架 240的對應互連引腳242互連起來。接合線可以包含金、銅，或者 上述一者的組合，或者其它適合的材料。膠體6〇封裝接合線5〇的至 少一部分。 任何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可做 午的更動與潤飾，因此本發明之保護範圍當視所附之申請專利範圍籲 所界定者為準。 【圖式簡單說明】 第1圖為根據本發明的一個 原理平面圖。 實施例的示例的擴散型晶圓級封裝的 圖為第1圖中，沿著線W，的擴散型WLP的截面示意圖。 3圖為製造如第2圖所示的擴散型WLP的步驟的示意圖。· Γ5 It眺本發明的另—個實施例的，擴散型wlp戴面示意圖。 ‘”根據本發明的再一個實施例的接合晶片封裝的截面示意 。“圖為根據本發明再—個實施例的線接合晶片封裝的截面示意 哥第7圖為_本㈣的再—靡_曝叫裝的截面示 26 201112387 第8圖為根據本發明的再一個實施例的線接合晶片封裝的截面示 意圖。 - 第9圖和第圖為根據本發明的截面視圖的的重新分配接合塾的 一些示意變形。 第11圖為根據本發明再一個實施例的疊層封裝結構的多晶片封 裝的戴面示意圖。 第12圖為根據本發明另一個實施例的疊層封裝結構的多晶片封 裝的截面示意圖。 • 第U圖為根據本發明另一個實施例的疊層封裝結構的多晶片封 裝的截面示意圖。 第14圖為根據本發明另一個實施例的導線架多晶片封裝的截面 示意圖。 第15圖為根據本發明另一個實施例的E_pad LQFp多晶片封沪的 截面示意圖。 第16圖為根據本發明另一個實施例的qfn多晶片封裝的戴面八 意圖。 7 ' =Π _根縣發明另—個實施_具有疊層塊 片封裝的戴面示意圖。 舟W夕日日 第圖為根據本發明另一個實施例的 LQ卯多晶片封裝的截面示意圖。 才裝、、。構的E-pad 第19圖為根據本發明另_ 多晶片職賴的雜實_的具有4層·結構的q™ 27 201112387 【主要元件符號說明】 1，la，lb〜擴散型WLP ; 1 c〜晶片封裝， 10〜半導體裸晶； 10a~主動晶面， 10b〜背面； 10c〜裸晶側面； 12，12a〜輸入/輸出墊； 16〜支援結構； 16a〜頂面； 20〜重接線疊層結構； 21〜重新佈線金屬層； 22，22a〜重新分配接合墊； 24〜電介質層； 40〜晶片載體； 40a〜依附面； 42〜接合墊； 50〜接合線； 60〜膠體； 60a〜空腔； 100，100a，100b，100c〜線接合晶片封裝； 140〜導線架； 28 201112387 140a〜裸晶墊； 140b〜底面； • 142〜内側引腳； 152〜枯結層； 200，200a -200h〜多晶片封裝； 222，322〜凸塊； 240〜導線架； 240a〜裸晶塾， # 240c〜凹腔； 242〜互連墊； 51-55〜步驟。FIG. 4 is a cross-sectional view of an exemplary wire bonding wafer package contact according to still another embodiment of the present invention, as shown in FIG. 5, a semiconductor die 1G' having a bare crystal face and a bare crystal side center is disposed on the wafer. The carrier (the bare crystal phase (10) of the earrie phase is also surface) 40a on which the wafer carrier 4 can be, for example, a package substrate or a printed circuit board, wherein a plurality of input/output ports 12 are located on the semiconductor die or within. The support structure 〖6 can (10) semiconductor bare crystal 1G. The auxiliary structure 16 has a top surface (6), and the top surface 16a is substantially flush with the active bare surface i0a. 'Rewiring laminated structure 20 package semiconductor die 10 is provided with a re-wiring laminated structure 2〇201112387 comprising a plurality of redistribution bonding pads 22, and a plurality of redistribution bonding pads 22 may be projected outside the bare side 10c, or It may not be projected outside the bare side 1〇c. The redistribution bond pads 22 are interconnected with corresponding bond pads 42 on the wafer carrier 4 using a plurality of bond wires 50. A colloid (m〇Mcap) is provided to encapsulate at least the semiconductor die 10, the re-wiring laminate structure 2, the support structure 16, and the bonding wires 5〇. According to this example, the colloid 60 and the support structure π can be made of different gum cakes. According to this embodiment, the bond wires 50 may comprise gold, copper, or a combination of the two, or other suitable materials. According to the present invention, the face distribution bonding pad 22_ is formed of copper, and the bonding wire 50 is a copper wire. Since the input/output 塾12 having a close 塾 spacing on the semiconductor die 10 is redistributed at the periphery, it is projected on the outer region outside the bare side (the 重新 匪 因此 因此 因此 重新 重新 重新 重新 重新 重新 重新The loose inter-pitch spacing of the joints. However, as previously mentioned, the redistribution bond pads 22 may be projected outside the bare side 10c or not projected beyond the bare side 1c according to design requirements. 6 is a cross-sectional view showing a wire bonding wafer package according to still another embodiment of the present invention. As shown in FIG. 6, 'via a dry layer (adhesivelaye 152, a diffusion type WLP la is disposed on a wafer carrier (in this embodiment) For example, the lead frame of the lead frame i or the bare pad 14〇a, wherein the diffusion type WLp u includes the semiconductor bare die 1 with the active bare crystal shirt and the bare side 10c, and multiple input/output ports塾12 is located in or on the semiconductor die ίο. The diffusion type WLP la may include a support structure 16 which surrounds the semiconductor die 1 (). The support structure 16 has a top surface (6), and the top surface is 12 1212 Moving bare face 10a is substantially flush. 'The diffusion type WLpla further comprises a re-wiring laminate structure 20, and the re-wiring laminate structure 20 is on the semiconductor die 1 and the top surface 1 of the support structure 16 as above. The rewiline stack structure 20 can Manufactured in an assembly house. The rewiline stack structure 20 includes a plurality of redistribution bond pads 22' and a plurality of redistribution bond pads 22 can be projected out of the bare side 10c, and the redistribution bond pads 22 can have A loose pad spacing for wire bonding applications. In another embodiment, depending on design requirements, the redistribution bond pad 22 may not be projected outside the bare side 1Ge, or only its towel - partially projected on the bare side In still another embodiment, at least a portion of the redistribution bond pad 22 is not projected beyond the bare side surface l〇c. The bond pads 22 and the lead frame are redistributed using a plurality of bond wires 50 (leadframe) 14 〇 corresponding inner leads 142 are interconnected. The colloid 60 is packaged with at least a semiconductor die 1 , a re-wiring layer structure 20 , a support structure 16 , a bare pad 14 〇 a , and an inside lead L 2 And bonding wires 50. According to this embodiment, the bonding wires 5A may comprise gold, copper, or a combination of the two or other suitable materials. Figure 7 is a wire bonding wafer package in accordance with still another embodiment of the present invention. 1〇〇1) The wearing surface map. As shown in Fig. 7, through the drilled layer 152, the expanded WLP la containing the semiconductor bare crystal is disposed on the bare pad i4〇a of the lead frame 140, and The semiconductor die has an active bare face 10a and a die side i〇c, wherein a plurality of input/output pads I] are located within or on the semiconductor die 10. The diffusion type WLP la may include a support structure 16 surrounding the semiconductor die 10, wherein the support structure 16 has a top surface 16a, and the top surface 16a is substantially flush with the 13201112387 active die plane l〇a. The diffusion type <13> 13 further includes a re-wiring laminated structure 20 on the semiconductor die 10 and the top surface 16a of the support structure 16. Similarly, the patch cord laminate structure 20 includes a plurality of redistribution bond pads 22, and the plurality of redistribution bond pads 22 can be projected outside of the bare side faces i〇c or not projected beyond the bare side faces i〇c A plurality of bond wires 50 are used to interconnect the redistribution bond pads 22 with the inner leads 142 of the leadframe 14A. The bonding wires 5〇 may comprise gold, copper, or a combination of the two, or other suitable materials. The colloid 60 encapsulates at least a semiconductor die 1 , a re-wiring stack structure 20 , a support structure 16 , an inner pin 142 , and a bond wire 50 . According to this embodiment, the bottom surface 14〇b of the bare pad 140a is not surrounded by the colloid 60 and, therefore, can be exposed to the air. Such a package structure may be referred to as an exposed pad (Jppad (j_pad, E_pad) Low-Profile Quad Hat Package (LQFP). Figure 8 is a wire bond according to still another embodiment of the present invention. A schematic cross-sectional view of the chip package 1 〇〇 c. As shown in Fig. 8, a diffusion type WLpia including a semiconductor die 1 , is disposed on the bare pad 24 (9) of the lead frame 240, and the semiconductor die 1 〇 has active die The surface l〇a and the bare side i〇c, wherein the plurality of input/output pads 12 are located in or on the semiconductor die 1b. The die pad 240a may further comprise a recess 24〇c, and The semiconductor die ί can be disposed in the cavity 240. The diffusion type WLPla can include the support structure 16, and the support structure 16 surrounds the semiconductor die 1. The support structure 16 can have the top surface 16a' and the top surface 16a and the active bare The crystal plane i〇a is substantially flush. The diffusion type WLp la further includes a re-wiring laminated structure 2 on the semiconductor die 10. Similarly, the reconnection 201112387 line laminate structure 2G includes a plurality of redistribution joints 22 And multiple redistribution joints The crucible 22 may be projected outside the bare side l〇c or not projected on the bare side. A plurality of bonding wires 5〇 are used to re-distribute the bonding pads 22 with the corresponding interconnects 242 of the leadframe. The bonding wires 50 may comprise gold, copper, or both of the above or other suitable. The colloidal 6G package includes at least the rotating die 1 (), the re-wiring laminated structure 20, the supporting structure 16, the bare crystal The upper portion of the pad 24A, the upper portion of the interconnect 242, and the bonding wire 50. The package configuration as shown in Fig. 8 can be referred to as a quad flat no-lead (QFN) package or advanced. The quad flat no-leaded (aQFN) package structure. In other embodiments, the support structure 16 as shown in the second @, 4th to 1Gth drawings may be omitted. The wiper may have another semiconducting crystal on the semiconductor die 1(). Another semiconductor die may be connected to the semiconductor die 10 via at least a bonding wire. In other embodiments, another semiconductor is bare. The crystal can be surface-connected to the semiconductor bare matte 10 without projecting to the bare side l〇c A new distribution joint 22 is shown in Fig. 11. Fig. 11 is a perspective view showing a multi-chip package of a stacked package (POP) structure according to still another embodiment of the present invention, wherein the same reference numerals denote the same A region, layer or element. As shown in FIG. N, the multi-chip package 200 includes a diffusion type WLP lb' in which the diffusion type WLP lb includes a semiconductor die 1 having a bare face 1 〇 & and a bare side 10 c. The diffusion type WLPlbK is disposed on the die attaching surface 40a of the wafer carrier 40, and the wafer carrier 40 can be, for example, a package substrate, a printed circuit board 15 201112387 2 lead frame 'wherein a plurality of input/output ports 12 and 仏 are located in the semiconductor die 〇 The face 1〇a is located in the semiconductor die 10. Support structural adhesive cake) = semiconductor bare crystal K). The support structure 16 has a top surface 16a and the top surface 10a is substantially flush. Gong 俅 , + conductor bare crystal 1G provides Na _ structure Μ, re-wiring laminated package t 个 a redistribution joint 塾 22 and melon for input / output 塾 12 and 12a. The weight = mating bond pads 22 and 22a may be projected outside of the bare side (10) or may not be outside the seed side W. At least one of the re-distribution 〇 22 and 22a is interconnected with a corresponding bond pad 42 on the wafer carrier 40 using at least one bond wire. A colloid 60 is provided to encapsulate at least a portion of the bond line %, and to further encapsulate at least a portion of the semiconductor 重0 re-wiring laminate structure 2 and the support structure 16. According to this embodiment, the colloid (4) and the support structure 16 may be made of gold, copper or a combination of the two, or other suitable materials, according to another embodiment. According to the present invention, the redistribution joint is formed of copper and the bond wire 50 is a copper wire. The input/output port 12a is located on the active bare crystal shirt of the semiconductor die 1 or in the rotating die 10. The input/output pads 12a are redistributed to the respective redistribution junctions via the rewiring layer Layer' RDL) 21a. The colloidal item has a cavity 60a to expose the redistribution joint 22a. The chip package is disposed on the cavity/internal diffusion type WLP lb. In the present embodiment, the wafer encapsulation is electrically connected to the diffusion type WLpib by bumps (bumP) 222, wherein the bump milk is bonded to the redistribution 201112387 bond pad 22a. In another embodiment, the die package ic can be electrically connected to the diffusion type WLP lb via copper, wherein the copper posts are bonded to the redistribution bond pads 22a. The redistribution bond pads 22 and 22a may be projected outside the bare side 1c, or may not be projected outside the bare side 10c. In one embodiment, the redistribution bond pads 22 and 2 are projected out of the bare side 10c. In another embodiment, only a portion of the redistribution pads 22 and 22a are projected out of the bare sides l〇c. In another embodiment, at least a portion of the redistribution bond pads 22 and 22a are not projected beyond the bare side 1c. And in a further embodiment, no redistribution of bond pads 22 and 22a is projected onto the bare side i〇c. The redistribution joints 22 and 22a can be redistributed to best meet packaging and performance requirements. > Fig. 12 is a perspective view of a multi-chip package 200a of a stacked package structure according to another embodiment of the present invention. The same reference numerals denote the same regions, layers or elements. The main difference between the multi-chip package 2A shown in Fig. 12 and the multi-chip package shown in Fig. 5 is that the multi-chip package is packaged in a package of colloidal On the bump 322. Bumps 322 electrically connect the bumps of the wafer package from the redistribution bond pads of the diffusion type WLP lb. In another embodiment, the bumps 222, bumps 322, or both can be replaced by copper posts, so that the wafer package can be electrically connected to the redistribution bond 22a via the copper posts. According to this embodiment, the colloid is empty. Further, Fig. 13 is a schematic view of a multi-wafer package 200b according to another embodiment of the present invention, wherein the same reference numerals denote the same regions, layers or elements. As shown in FIG. 13, the multi-chip package 200b includes a diffusion type WLP lb, wherein the moon-type WLP lb includes a semiconductor die having a bare face 1〇a and a bare side face 1〇c (1) a diffusion type WLP lb is disposed on the wafer The die attach surface of the carrier 4 can be, for example, a package substrate, a circuit board or a lead frame, wherein the plurality of input/output pads 12 and 12a are located above the semiconductor die 1 or at the semiconductor die 1 。. = Aid structure 16 (such as rubber cake) (4) Semiconductor bare crystal 1 〇. The support structure 16 has a top surface and the top surface 16a is substantially flush with the active bare surface 1A. A rewiring stack structure 2 is provided on the semiconductor die 10, and the rewiring stack structure 2 〇 # includes a plurality of redistribution bond pads 22 and 22a for input/output 塾 and 仏. The redistribution bond pads 22 and 22a may be projected outside the bare side 1c, or may not be projected outside the bare side 10c. The at least one redistribution bond pad 22 is interconnected with the corresponding bond $42 on the wafer bond 4G using at least one bond wire 5A. The output port 12a is located on the active bare face 1〇a of the semiconductor die 1〇 or at the semiconductor Inside the bare crystal. The input/output 塾i2a is reallocated to the respective redistribution joints 22a through the rewiring layer 21a. In the present embodiment, the wafer package is electrically connected to the diffusion type lb by bumps 222, wherein the bumps 222 are bonded to the redistribution joints 22 & In another embodiment, the wafer sealing 1c can be coupled to the redistribution joint 22a by a copper post and a diffusion type WLp. Warfare, the middle copper column provides the colloid 60 (four) less-partial joint line%, and the frequency-loading of the crystal, the re-wiring laminated structure 2〇, the support structure 16 at least _ part, and the - ang angry chip package lc -section. According to one embodiment, the colloid 6〇 and the support structure 201112387 can be made in the same way. According to another embodiment, the bonding wire is comprised of gold, copper or a combination of the two or other suitable materials. According to another embodiment of the present invention, the redistribution joint 22 is formed of copper, and the bonding wires 5 are copper wires. Figure 14 is a schematic cross-sectional view showing a dirty portion of a lead frame multi-chip package in accordance with another embodiment of the present invention. As shown in Fig. 14, the diffusion type body 1b includes a semiconductor die 1 having a bare crystal face 10a and a bare crystal side face H)C. And through the dry layer 152, the diffusion type wLp lb is disposed on the bare die attaching surface or the bare crystal smoothing of the lead frame 140, wherein the plurality of lu input/output turns 12 and 12a are located on the bare crystal face of the semiconductor bare die 1 . 1〇a or semiconductor bare germanium) semiconductor bare crystal 10. The support structure 16 has a top surface 16a that is substantially flush with the active die face 10a. The diffusion type WLP lb-in step comprises a re-wiring stack structure 2, and the re-wiring stack structure 20 is on the semiconductor die 10 and on the top surface 16& of the support structure 16. Heavy-duty laminates Call structure 2〇 can be made in package Wei. The rewiring stack structure contains multiple reassignment connections. Pads 22 and 22a, a plurality of redistribution tabs 22 and 22a may be projected outside the bare side 10c' or may not be projected outside the bare side 1c, and the redistribution pad 22 may have a wire bond Should be (four) loose distance. A plurality of input/output 塾仏 are located on the bare crystal face 1〇a of the semiconductor bare crystal 1或者 or within the semiconductor bare crystal 1〇. The input/output pad 12a is re-distributed to the respective redistribution bond pads 22a by a re-distribution layer (2U. In the present embodiment, the chip package lc is disposed on the diffusion type WLP lb' and passes through the bump 222 Electrically connected to the diffusion type WLp 'where the convex 201112387 ==:=::::: The at least one redistribution junction 互连 is interconnected with the corresponding _ pin 142 of the conduction 140 using the J - bonding wires 5G. The colloid (9) package is at least partially bonded: 50' and further encapsulates the semiconductor die (1), the re-wiring stack structure, for example, supports the immersion 16, the die pad, the inner pin 142, and the step Sealing 曰: Packing a portion of 1C. According to this embodiment, the bonding wire 5〇 may comprise a combination of gold, copper, or other suitable material. Figure 15 is a diagram of another embodiment in accordance with the present invention. A cross-sectional view of the Epad LQFp more than 2_. As shown in Fig. 15, the diffusion type wLp ib includes a semiconductor die 1 having a bare f face 10a and a bare side 10c, and via the dry layer 152, the variable lb is set at The die of the lead frame 140 is applied, wherein a plurality of wheels = pad i2 and The support structure 16 may be included on the semiconductor die 1 or the semiconductor die 1/4, and the support structure 16 surrounds the turn naked day and day ω. The support 16 has a top surface 16a' and the top surface 16a and the active The bare crystal face is substantially flush. The diffusion type WLP lb advance step comprises a rewiring stack structure 2, and the rewiline stack structure 20 is on the semiconductor die 1 and the top surface of the support structure 16. The rewiring structure 20 includes a plurality of redistribution joints 22 and melons. The plurality of redistribution joints and 22a may be projected outside the bare side 10c or may not be projected outside the bare side. Multiple inputs/outputs The semiconductor substrate is placed on the bare semiconductor surface of the semiconductor die 1. The input/output pad 12a is redistributed to the respective redistribution bonding pads 22a through the rewiring layer 21a. In this embodiment, The chip package lc is disposed on the diffusion type WLP lb and electrically connected to the diffusion type WLP lb through the bump 222, wherein the bump 222 is bonded to the redistribution bonding pad 22a. In another embodiment, the wafer package can pass through the copper pillar Electrically connected to the diffused WLP lb Wherein the copper posts are bonded to the redistribution bond pads 22a. At least one redistribution bond pad 22 is interconnected with the corresponding inner pins 142 of the leadframe 140 using at least one bond wire 50. The bond wires 5〇 may comprise gold 'copper Or a combination of the two, or other suitable materials. The colloid 60 encapsulates the bonding wire 5 卩. The boring tool, and further encapsulates the semiconductor die 10, the re-wiring laminated structure 20, the support structure 16, the bare pad 140a, a portion of the inner leads 142, and further encapsulating a portion of the wafer package lc. According to this embodiment, the colloid 6 〇 does not enclose the bottom surface 140b of the bare pad 14 and the bottom surface 140b is exposed to the air. Figure 16 is a cross-sectional view of a QFN multi-chip package 2A according to another embodiment of the present invention. As shown in Fig. 16, the diffusion type WLP lb includes a semiconductor bare crystal 1G having a bare crystal face 1a and a bare crystal side IGe. And the diffusion type emulsion lb lb is disposed on the bare pad 240a of the lead frame, wherein the plurality of input/output pads 12 and 12a are located above the semiconductor die 10 or within the semiconductor die 1Q. The bare day/day step may include a cavity (reCeSS) 240c' and the semiconductor die 1 may be disposed in the cavity 240c. The diffusion type WLP lb may include the support structure 16, and the support structure 16 surrounds the semiconductor bare 35ω. The support structure 16 can have a top surface 16a which is substantially flush with the active bare surface i〇a. 21 201112387 Diffusion type WLP lb advances a rewired laminate structure 20 on a semiconductor die 1 . The rewiring stack structure 20 includes a plurality of redistribution bond pads 22 and 22a, and the plurality of redistribution bond pads 22 and 22a can be projected out of the bare side 1c or not projected outside the twin side 10c. The input/output port 12a is located above the active bare b-plane 10a of the semiconductor die (1) or within the semiconductor die 1〇. The input/output pads are newly assigned to the respective redistribution bond pads by the redistribution layer 21a f. In the present embodiment, the wafer package lc is disposed on the diffusion type WLP lb and electrically connected to the diffusion type lb by the bumps 222, wherein the bumps 222 are bonded to the redistribution bonding. In another embodiment, the wafer package lc can be electrically connected to the diffusion type WLp lb through a copper post, wherein the steel post is bonded to the redistribution bond pad 22a. At least one redistribution bond is interconnected with a corresponding interconnect pin 242 of leadframe 240 using at least one bond wire 5''. The bonding wire % may comprise gold, copper, or a combination of the two, or other suitable materials. _(9) packaging at least a portion of the bonding, ''recovering and progressively encapsulating the semiconductor die 10, the rewiring stack structure Μ, the support structure 16, the upper portion of the die 240a, a portion of the upper portion of the interconnect pin 242, And further packaging at least a portion of the wafer package lc. The figure is a schematic cross-sectional view of a package package 200f having a laminated package I according to another embodiment of the present invention. As shown in Fig. 17, the diffusion type hunger includes a semiconductor bare crystal having a bare crystal surface and a bare crystal side 1 〇c, and a bare crystal disposed on the lead frame (10) via a dry sound ❿ = bulk WLP lb Depending on the surface or bare (four) ^, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Expanding the drawing - and the ancient fresh heart can contain the supporting structure l - while the top surface is naked = the second f can have (4), =WUMb into the tender line on the W(6) of the tender structure i The layer structure is 2〇. The rewiring laminate structure 2〇 can be manufactured in the package. The rewiring stack structure 2 includes (4) the recording joint 22 and the melon, and the plurality of redistribution joints 22a may be projected outside the bare side (10) or not projected outside the bare side 10c. And the redistribution splice 22 can have a loose interpupillary spacing for the wire: application. The input/output 塾 12a is located above the active bare face l〇a of the half-baked die (1) or within 1 turn of the rotating die. The input/output ports are redistributed to the respective redistribution joints by the redistribution layer 21a. The colloid (6) has a cavity 6〇a to expose the redistribution joint 22a. The wafer seals c are disposed on the cavity_internal = diffusion type WLP lb. In the present embodiment, the wafer package lc is electrically connected from the diffusion type WLP lb by bumps, wherein the bumps 222 are bonded to the redistribution bonding pads 22a. In another embodiment, the chip package 1C can be electrically connected to the diffusion type WLp lb through a copper post, wherein the copper post is bonded to the redistribution bond pad 22a. At least one redistribution bond pad 22 is interconnected with a corresponding inner pin 142 of the leadframe 140 using at least one bond wire 50. The gel 60 encloses at least a portion of the bond wires. According to this embodiment, the bond wires 50 may comprise gold, copper, or a combination of the two, or other suitable materials. Figure 18 is a perspective view of a surface of an E_pad 23 201112387 LQFP multi-chip package 200g having a stacked package structure in accordance with another embodiment of the present invention. As shown in FIG. 18, the diffusion type muscle p ib includes a semiconductor bare crystal ITO having a bare crystal from 10 & and a bare crystal side 1 〇 c, and a diffusion type WLP lb is disposed on the lead frame 14 via the dry junction layer 152 The germanium die is hidden therein, and the plurality of input/output pads 12 and 12a are located above the bare crystal face of the semiconductor die 1 or within the semiconductor die. The diffusion type WLP lb can support the ray 16, while the support structure 16 surrounds the semiconductor die 10. The support structure 16 can have a top-faced shirt with the top surface 16a being substantially flush with the active bare face i〇a. The diffusion type WLP lb advances the re-wiring stack, structure 2 on the semiconductor die 1 and the top surface 16a of the support structure 16. The rewiring stack structure includes a plurality of redistribution bond pads 22 and 22a' and the plurality of redistribution bond pads 22 and 22a can be projected out of the bare side © 10c or not projected outside the die. The input/output 塾仏 is located above the active bare face 1〇a of the semiconductor die 1 or within the semiconductor die. The input/output ports 12a are redistributed to the respective redistribution pads 22a by the rewiring layer 21a. The colloid 60 has a cavity 60a therein to expose the redistribution bond pad 22a. The wafer package lc is disposed on the diffusion type WLp lb inside the cavity 60a. In the present embodiment, the wafer package lc is electrically connected to the diffusion type WLP lb through bumps 222, wherein the bumps 222 are bonded to the redistribution joint 22a. In another embodiment, the wafer package lc can be electrically connected to the diffusion type WLP lb through a steel column where the copper posts are bonded to the redistribution bonded squash. At least one redistribution bond pad 22 is interconnected with a corresponding inner pin 142 of the leadframe 140 using at least one bond wire 50. The bonding wires 5〇 may comprise gold, copper, or a combination of the two, or other suitable materials. The colloidal 6〇 package bond wire 5〇 to 24 201112387 a small part. According to this embodiment, the colloid 6〇 does not encapsulate the bottom side of the bare crystal metaphor, and the bottom surface 140b is exposed to the air. Figure 19 is a schematic cross-sectional view of a multi-chip package 200h having a stacked package structure in accordance with another embodiment of the present invention. As shown in Fig. 19, the diffusion type body includes a semiconductor bare metal layer having a bare crystal face H)a and a bare crystal side surface 1〇c. And the diffusion type WLp 1 b is disposed on the bare pad of the lead frame 24 , wherein a plurality of input/output ports 2 and 12a are located in the semiconductor!! Above the bare crystal 1 or within the semiconductor bare crystal. The bare 塾 &> step may comprise a recess woven, and the semiconductor bare 曰曰曰 1 〇 may be disposed within the cavity 240c. The diffusion type WLP lb may include the support structure 16, and the support structure π surrounds the semiconductor bare cell 10. The support structure 16 can have a top surface 16a with the top surface (10) being substantially flush with the active bare surface 10a. The diffusion type WLP lb advances the rewired laminate structure 20 on the semiconductor die 1 . The rewiring stack structure 2 includes a plurality of redistribution bond pads 22 and 22a, and the plurality of redistribution bond pads 22 and 22a may be projected outside the bare side 10c or may not be projected outside the bare side 10c. The input/output pad 12a is located over the active bare face 10a of the semiconductor die 1 or within the semiconductor die 1〇. The input/output pads 12& are redistributed to the respective redistribution bond pads 22a by the redistribution layer 21a. The colloid 6 has a cavity 60a which redistributes the joint 22a with a violent path. The chip package ic is disposed on the diffusion type WLP lb inside the cavity 6〇a. In the present embodiment, the wafer package lc is electrically connected to the diffusion type WLP lb through the bumps 222, wherein the bumps 222 are bonded to the redistribution bonding pads 22a. In another embodiment, the die package lc can be electrically connected to the diffusion type WLp lb through a copper post, the copper pillar of which is bonded to the redistribution bond pad 22a in 25 201112387. At least one redistribution bond pad 22 is interconnected with corresponding interconnect pins 242 of leadframe 240 using at least one bond wire 50. The bond wires may comprise gold, copper, or a combination of the above, or other suitable materials. The colloid 6〇 encapsulates at least a portion of the bond wire 5〇. Anyone skilled in the art will be able to make changes and refinements in the afternoon without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a principle according to the present invention. The diffused wafer level package of the example of the embodiment is a schematic cross-sectional view of the diffusion type WLP along the line W in Fig. 1. 3 is a schematic view showing a step of manufacturing a diffusion type WLP as shown in FIG. 2. · Γ5 It眺 Another embodiment of the present invention, a schematic view of a diffused wlp wear surface. A cross-sectional view of a bonded wafer package according to still another embodiment of the present invention. "The figure is a cross-sectional view of a wire bonded wafer package according to still another embodiment of the present invention. FIG. 7 is a re-__ of this (4) Cross-sectional view of the exposed device 26 201112387 Figure 8 is a schematic cross-sectional view of a wire bonded wafer package in accordance with still another embodiment of the present invention. - Figure 9 and Figure are some schematic variations of the redistribution joint 塾 according to the cross-sectional view of the present invention. Figure 11 is a schematic illustration of a multi-chip package of a stacked package structure in accordance with still another embodiment of the present invention. Figure 12 is a schematic cross-sectional view showing a multi-wafer package of a stacked package structure in accordance with another embodiment of the present invention. • Figure U is a cross-sectional view of a multi-wafer package of a stacked package structure in accordance with another embodiment of the present invention. Figure 14 is a cross-sectional view showing a lead frame multi-chip package in accordance with another embodiment of the present invention. Figure 15 is a cross-sectional view showing the E_pad LQFp multi-chip package in accordance with another embodiment of the present invention. Figure 16 is a perspective view of a qfn multi-chip package in accordance with another embodiment of the present invention. 7 ' = Π _ Root County invents another implementation _ a schematic diagram of the wearing surface with a laminated block package. The following is a schematic cross-sectional view of an LQ(R) multi-chip package in accordance with another embodiment of the present invention. Only installed, and. Figure 19 is a diagram showing the structure of the E-pad according to the present invention. The QTM 27 201112387 has a 4-layer structure. [Main component symbol description] 1, la, lb~ diffusion type WLP; c ~ chip package, 10 ~ semiconductor bare crystal; 10a ~ active crystal face, 10b ~ back; 10c ~ bare side; 12, 12a ~ input / output pad; 16 ~ support structure; 16a ~ top surface; 20 ~ rewiring Laminated structure; 21~ rewiring metal layer; 22, 22a~ redistribution bonding pad; 24~ dielectric layer; 40~ wafer carrier; 40a~ bonding surface; 42~ bonding pad; 50~ bonding wire; 60~ colloid; ~ cavity; 100, 100a, 100b, 100c ~ wire bonded wafer package; 140 ~ lead frame; 28 201112387 140a ~ bare pad; 140b ~ bottom surface; • 142 ~ inner pin; 152 ~ dry layer; 200, 200a -200h~ multi-chip package; 222, 322~ bumps; 240~ lead frame; 240a~ bare die, #240c~ cavity; 242~ interconnect pad; 51-55~ step.
2929