CN102403281A - A high-performance chip packaging structure - Google Patents

Abstract

The invention discloses a high-performance chip packaging structure which comprises a metal pin frame, a substrate, a chip, a radiating fin and a packaging body and is characterized in that the packaging end of the metal pin frame adopts a Y-shaped structure, a chip accommodating cavity can be formed by the metal pin frame and the substrate welded inside the metal pin frame when the metal pin frame is used in pairs, the chip is positioned in the chip accommodating cavity and is bonded on the substrate, one end of the radiating fin penetrates through a gap between the metal pin frames to be connected with the substrate, and the other end of the radiating fin extends out of the packaging body. The invention discloses a high-performance chip packaging structure, which has high packaging space utilization rate and can implement a multi-chip packaging process; meanwhile, the good heat dissipation structure enables heat generated by the chip to be easily released, and efficient operation of the chip is ensured.

Description

A high-performance chip packaging structure

technical field

The invention relates to a chip packaging structure, in particular to a high-performance chip packaging structure with excellent heat dissipation performance and capable of realizing multiple chip packaging processes, belonging to the technical field of chip packaging.

Background technique

In the manufacture of integrated circuits, chips are obtained through the steps of wafer fabrication, forming integrated circuits, and cutting wafers. After the integrated circuit of the wafer is fabricated, the chip formed by dicing the wafer can be electrically connected to the carrier outwardly; wherein, the carrier can be a lead frame or a substrate, and the chip can be wire bonded or covered. The method of crystal bonding is electrically connected to the carrier. If the chip and the carrier are electrically connected by wire bonding, then enter into the manufacturing step of filling the encapsulant to form the chip package. Chip packaging technology is a process technology that wraps the chip to avoid contact between the chip and the outside world and prevent damage to the chip from the outside world. Impurities and bad gases in the air, and even water vapor will corrode the precision circuits on the chip, resulting in a decrease in electrical performance. Different packaging technologies differ greatly in terms of manufacturing procedures and processes, and packaging also plays a vital role in the performance of the memory chip itself. With the rapid development of optoelectronic and microelectronic manufacturing technology, electronic products are always developing in the direction of smaller, lighter and cheaper, so the packaging form of chip components is also continuously improved.

In the current chip packaging process, people are most concerned about the heat dissipation performance of the chip and the packaging capacity of the packaging structure. Especially when packaging some high-power, multi-chip integrated circuits, the heat dissipation problem is definitely the primary problem to be dealt with. normal operation of the chip.

Contents of the invention

In view of the above requirements, the present invention provides a high-performance chip packaging structure, which can realize multi-chip packaging, and at the same time, can ensure good heat dissipation performance of the packaging structure. the

The present invention is a high-performance chip packaging structure, which includes a metal lead frame, a substrate, a chip, a heat sink and a package body, and is characterized in that the package end of the metal lead frame adopts "Y "type structure, when used in pairs, it can form a chip accommodating cavity with the substrate welded inside. The chip is in the chip accommodating cavity and bonded to the substrate. One end of the heat sink passes through the The gap between the lead frames is connected to the substrate, and the other end protrudes from the package body.

In a preferred embodiment of the present invention, the chip and the substrate are generally fixedly connected by thermosetting adhesive, and then electrically connected by gold wires.

In a preferred embodiment of the present invention, the upper and lower parts of the chip accommodating cavity are packaged with a substrate and a chip, and a certain distance is maintained between the upper and lower chips.

In a preferred embodiment of the present invention, the size of the chip accommodating cavity is determined by the specifications of the substrate and the chip, and the distance between the chips can avoid the contact of the gold wire during packaging and reduce the performance.

In a preferred embodiment of the present invention, heat-conducting glue is used to connect the heat sink and the substrate, and at the same time, a sealant is provided in the gap between the heat sink and the end of the contacting metal lead frame.

In a preferred embodiment of the present invention, the heat sink is generally made of copper or aluminum alloy.

The invention discloses a high-performance chip packaging structure. The high-performance chip packaging structure has a high utilization rate of the packaging space and can implement a multi-chip packaging process; at the same time, the good heat dissipation structure makes the heat generated by the chip easy to release, ensuring the high efficiency of the chip. run.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

Fig. 1 is a structural schematic diagram of a high-performance chip packaging structure according to an embodiment of the present invention;

The marks of the components in the drawings are as follows: 1. Metal lead frame, 2. Substrate, 3. Chip, 4. Heat sink, 5. Package body, 6. Chip accommodation cavity, 7. Gold wire, 8. Sealant .

Detailed ways

The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

Fig. 1 is the structure schematic diagram of the high-performance chip package structure of the embodiment of the present invention; This high-performance chip package structure comprises metal lead frame 1, substrate 2, chip 3, heat sink 4 and package body 5, it is characterized in that, described The packaging end of the metal lead frame 1 adopts a "Y" structure, and when used in pairs, it can form a chip accommodating cavity 6 with the substrate 2 welded inside it, and the chip 3 is in the chip accommodating cavity 6, and Bonded on the substrate 2 , one end of the heat sink 4 is connected to the substrate 2 through the gap between the metal lead frames 1 , and the other end extends out of the package body 5 .

In the high-performance chip packaging structure mentioned in the present invention, the metal lead frame 1, the substrate 2 and the chip 3 are all packaged in the package body 5, and one end of the heat sink 4 is connected to the substrate 2 inside the package body 5, and the other end extends out. The package body 5 is exposed to the outside to improve heat dissipation performance; wherein, the package body 5 is made of silica gel material.

The chip 3 and the substrate 2 are generally fixedly connected by a thermosetting adhesive, and then electrically connected by a gold wire 7; Chip 3, maintain a certain distance between the upper and lower chips; the size of the chip accommodating cavity 6 is determined by the specifications of the substrate 2 and the chip 3, and the distance between the chips 3 can avoid the contact of the gold wire during packaging and reduce the performance. The distance generally accounts for 20%-40% of the total thickness of the chip 3 and the substrate 2 .

The heat sink 4 and the base plate 2 are connected by heat-conducting glue. At the same time, a sealant 8 is provided in the gap between the heat sink 4 and the end of the metal lead frame 1 that it contacts. This structure can be used to ensure the sealing performance of the package and The installation stability of the heat sink 4 ; the heat sink 4 is generally made of copper or aluminum alloy, and its size and specification are determined by the specification of the packaged chip 3 .

The invention discloses a high-performance chip packaging structure, which is characterized in that: the high-performance chip packaging structure has a high utilization rate of the packaging space and can implement a multi-chip packaging process; at the same time, the good heat dissipation structure makes the heat generated by the chip easy to release, To ensure the efficient operation of the chip.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto, and any person skilled in the art may make changes or modifications without creative work within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope defined in the claims.

Claims (6)

1. high performance chips encapsulating structure; This high performance chips encapsulating structure comprises metal pins frame, substrate, chip, fin and packaging body; It is characterized in that the potted ends of described metal pins frame adopts " Y " type structure, when using in pairs can be welded on its inner substrate and form a chip containing cavity; Described chip is in the chip containing cavity; And be bonded on the substrate, the gap that described fin one end passes between the metal pins frame links to each other with substrate, and packaging body is stretched out in the other end.

2. high performance chips encapsulating structure according to claim 1 is characterized in that, the general heat curing-type viscose glue that adopts is fixedly connected between described chip and the substrate, electrically connects through gold thread then.

3. high performance chips encapsulating structure according to claim 1 is characterized in that the upper and lower part of described chip containing cavity all is packaged with substrate and chip, keeps certain distance between the upper and lower chip.

4. high performance chips encapsulating structure according to claim 3 is characterized in that, the size of described chip containing cavity confirmed by the specification of substrate and chip, and gold thread came in contact and reduces serviceability when the distance between the chip can be avoided encapsulating.

5. high performance chips encapsulating structure according to claim 1 is characterized in that, adopts heat-conducting glue to be connected between described fin and the substrate, simultaneously, is provided with fluid sealant in the gap of fin and the metal pins frame end portion that is contacted.

6. high performance chips encapsulating structure according to claim 5 is characterized in that, described fin generally adopts copper or aluminum alloy materials to process.

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