CN105870115A - Multi-chip 3D packaging structure - Google Patents

Abstract

The invention discloses a multi-chip 3D packaging structure, which comprises a plastic package (40), a frame base island (41) is packaged in the plastic package (40), and at least one control panel is mounted on the front side of the frame base island (41). chip (43), and an insulating glue (47) is provided between the control chip (43) and the frame base island (41); at least one power chip (42) is mounted on the back of the frame base island (41) , and a plurality of copper pillars (46) are evenly arranged between the power chip (42) and the frame base island (41); the other side of the power chip (42) is mounted together with a heat sink by solder; wherein , the functional pins on the control chip (42) are connected to the frame pins on the frame base island (41). The present invention uses Flip-chip technology to mount power chips, avoids the use of welding wires for connection, effectively reduces the internal resistance of large current loops, and improves electrical efficiency.

Description

A multi-chip 3D packaging structure

technical field

The invention relates to a multi-chip 3D packaging structure.

Background technique

At present, the common multi-chip packages are mainly as follows:

1. Mount multiple chips on the same base island, and use wires to connect the chips to the pins. As shown in FIG. 1a to FIG. 1d : in this packaging structure, multiple chips are mounted on the same base island with die-mount adhesive, and usually the two chips are a power chip 12 and a control chip 13 . The substrate of the control chip 13 is at a low potential, and the substrate of the power chip 12 is at a high potential, and there is a voltage difference between the two substrates. The high potential on the substrate of the power chip 12 generally needs to be adhered to the base island of the frame with conductive glue, and the high potential is drawn out through the base island. In this case, the control chip 13 needs to be electrically isolated from the base island with insulating glue. Since the thickness of the insulating glue is difficult to control, and the coating on the surface of the frame is prone to have pointed and convex conductive particles, the substrate of the control chip 13 and the base island of the frame will leak electricity, affecting product performance and reliability. In addition, the surface of the power chip 12 is connected to the pins by wires, and there is a wire connection in the large current circuit, and the internal resistance is relatively large, which affects the electrical efficiency.

Its main disadvantages are: high-potential area and low-potential area are separated by insulating glue, and there is a risk of leakage; there is a welding wire connection in the high-current circuit, and the internal resistance is relatively large.

2. Multiple chips are stacked and packaged, and wires are used to connect the chips to the pins. As shown in Figures 2a to 2c:

The packaging structure is multi-chip stacking. The power chip 22 is mounted on the frame base island 21 with a mounting glue, and then the control chip 23 is mounted on the top of the power chip 22 with insulating glue. Chips are electrically connected to form a stacked chip structure. This packaging structure must require that the area of the power chip 22 is large enough to meet the size requirements of the mounting control chip 23, and it is required that no wire bonding can be performed on these areas. Since the power chip 22 is connected by a bonding wire, there is a large internal resistance of the bonding wire, so that there is a bonding wire connection in the large current circuit, and the internal resistance is relatively large, which affects the electrical efficiency.

Its main disadvantages are: there are wire connections in the large current loop, and the internal resistance is large; the area of the power chip must be larger than the area of the control chip.

3. Multi-chip multi-base island package, using wires to connect chips to pins. As shown in Figures 3a to 3c:

In this packaging structure, the power chip 32 and the control chip 33 are respectively mounted on a separate frame base island 31, and then connected by bonding wires. The chip and frame of this multi-base island structure are usually encapsulated inside the plastic package, so that the thermal resistance of the chip is high and the heat dissipation effect is not good. Wherein the power chip 32 is connected by bonding wires, there is a relatively large internal resistance of the bonding wires, which affects electrical efficiency.

Its main disadvantages are: there is no heat sink, and the heat dissipation effect is not good; there are welding wire connections in the high-current circuit, and the internal resistance is large.

Contents of the invention

The purpose of the present invention is to provide a multi-chip 3D packaging structure for the defects existing in the prior art.

In order to achieve the above object, the present invention adopts the following technical scheme: a multi-chip 3D packaging structure, including: a plastic package 40, a frame base island 41 is packaged in the plastic package 40, and at least the front side of the frame base island 41 is mounted with A control chip 43, and an insulating glue 47 is arranged between the control chip 43 and the frame base island 41; at least one power chip 42 is mounted on the back side of the frame base island 41, and the power chip 42 and the frame base A plurality of copper pillars 46 are evenly arranged between the islands 41 ; the other side of the power chip 42 is mounted together with a heat sink 45 through solder 44 .

Beneficial effects of the present invention:

1. The present invention will use the Flip-chip process to mount the power chip, avoiding the use of wire bonding, effectively reducing the internal resistance of the large current loop, and improving the electrical efficiency.

2. The present invention adopts the technology of loading films on both sides of the base island of the frame, fully utilizes the space of the base island, effectively saves the area of the base island of the frame, and saves material costs.

3. The present invention distributes and mounts control chips and power chips on the front and back of the frame base island, effectively separates low-potential chips and high-potential chips, and solves the problem of high-voltage insulation.

4. The present invention adopts the method of attaching the heat sink and exposes the heat sink on the surface of the plastic package, which effectively improves the heat dissipation performance of the package.

Description of drawings

Fig. 1a is a schematic plan view of a traditional multi-chip same-base island package structure.

Fig. 1b is a schematic cross-sectional view of a traditional multi-chip same-base island package structure.

Figure 1c is a schematic diagram of the high and low potential regions of the traditional multi-chip same-base island package structure.

Figure 1d is a schematic diagram of the high current region of the traditional multi-chip same-base island package structure.

FIG. 2a is a schematic plan view of a traditional multi-chip stack package structure.

Fig. 2b is a schematic cross-sectional view of a conventional multi-chip stack package structure.

Fig. 2c is a schematic diagram of a large current region of a traditional multi-chip stacked package structure.

Fig. 3a is a schematic plan view of a traditional multi-chip multi-base island package structure.

Fig. 3b is a schematic cross-sectional view of a traditional multi-chip multi-base island package structure.

Fig. 3c is a schematic diagram of a large current region of a traditional multi-chip multi-base island package structure.

Fig. 4a is a schematic plan view of the 3D packaging structure of the present invention.

Fig. 4b is a schematic cross-sectional view of the 3D packaging structure of the present invention.

FIG. 4c is a schematic diagram of the high and low potential regions of the 3D packaging structure of the present invention.

Fig. 4d is a schematic diagram of the high current region of the 3D packaging structure of the present invention.

FIG. 4e is a schematic diagram of the package when the heat sink is not exposed on the surface of the plastic package in the 3D package structure of the present invention.

FIG. 4f is a schematic diagram of packaging multiple power chips in the 3D packaging structure of the present invention.

FIG. 4g is a schematic diagram of packaging multiple control chips in the 3D packaging structure of the present invention.

detailed description

As shown in Figure 4a and Figure 4b, a multi-chip 3D packaging structure is disclosed. Installed on both sides of the frame base island, a new 3D packaging structure is finally obtained.

The 3D packaging structure obtained by the above process specifically includes: a plastic package 40, a frame base island 41 is packaged in the plastic package 40, at least one control chip 43 is mounted on the front side of the frame base island 41, and the control chip 43 and An insulating glue 47 is provided between the frame base islands 41; at least one power chip 42 is mounted on the back of the frame base island 41, and a plurality of copper pillars 46 are uniformly arranged between the power chip 42 and the frame base island 41 ; The other side of the power chip 42 is mounted together with the heat sink 45 through the solder 44 . Wherein, in order to make the packaging structure more compact, the functional pins on the control chip 42 are preferably connected to the frame pins on the frame base island 41 .

The process specifically includes the following steps:

a) Using the Bumping process to grow multiple copper pillars on the front side of the power chip;

b) Use the Flip-chip process to mount the power chip on the back of the frame base island;

c) Mount the heat sink on the back of the power chip with the Clip process;

d) Mount and paste the control chip on the front of the frame base island by using the mounting glue process;

e) Use bonding wires to connect the functional pins on the control chip with the frame pins;

f) Put the frame with welded wires into the processed mold, make the heat sink close to the mold for plastic sealing;

g) Electroplating the plastic-encapsulated product and then cutting the ribs to form it.

In the present invention, high-potential chips and low-potential chips are distributed and mounted on both sides of the frame base island, so that high-potential and low-potential chips are effectively isolated; as shown in FIG. 4c.

The present invention uses the Flip-chip process to mount the power chip, avoids the use of wire bonding, effectively reduces the internal resistance of the large current loop, and improves the electrical efficiency, as shown in Figure 4d.

In addition, in the above-mentioned packaging process of the present invention, the order of step b) and step c) can be interchanged, and the 3D packaging structure can also be realized. The packaging process after interchange is as follows:

a) Using the Bumping process to grow multiple copper pillars on the front of the power chip;

b) Mount the power chip on the heat sink using a soldering process;

c) Use the Flip-chip process to attach the power chip with the heat sink attached to the back of the frame base island;

d) Mount and paste the control chip on the front of the frame base island by using the mounting glue process;

e) Use bonding wires to connect the functional pins on the control chip with the frame pins;

f) Put the welded wire frame into the processed mold so that the heat sink is close to the mold for plastic sealing;

g) Electroplating the plastic-encapsulated product and then cutting the ribs to form it.

Wherein, when the power chip does not require heat dissipation, the heat sink may not be attached to the surface of the plastic package in step f), as shown in FIG. 4e.

Among them, the number of control chips and power chips on both sides of the frame base island is not limited to one, but can be multiple. At this time, the relevant processes in the process flow can be repeated many times, as shown in Figure 4f and Figure 4g. In addition, the package type can be different according to requirements, such as SOP, DFN, QFN, etc.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (1)

1. A multi-chip 3D packaging structure, characterized in that it comprises a plastic package (40), the plastic package (40) is packaged with a frame base island (41), and the front of the frame base island (41) is at least mounted with A control chip (43), and an insulating glue (47) is arranged between the control chip (43) and the frame base island (41); at least one power chip ( 42), and a plurality of copper pillars (46) are evenly arranged between the power chip (42) and the frame base island (41); the other side of the power chip (42) is connected with the heat sink ( 45) Mount together.