CN105845633A - Multi-chip 3D packaging technology - Google Patents

Multi-chip 3D packaging technology Download PDF

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Publication number
CN105845633A
CN105845633A CN201610204787.2A CN201610204787A CN105845633A CN 105845633 A CN105845633 A CN 105845633A CN 201610204787 A CN201610204787 A CN 201610204787A CN 105845633 A CN105845633 A CN 105845633A
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Prior art keywords
chip
framework
technology
technique
packaging
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CN201610204787.2A
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Inventor
刘桂芝
马丙乾
马小保
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WUXI LINLI TECHNOLOGY Co Ltd
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WUXI LINLI TECHNOLOGY Co Ltd
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Priority to CN201610204787.2A priority Critical patent/CN105845633A/en
Publication of CN105845633A publication Critical patent/CN105845633A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a multi-chip 3D packaging technology, comprising the steps of: a) growing a plurality of copper columns on the front surface of a power chip by using the Bumping technology; b) packaging the power chip on the back side of a framework base island by using the Flip-chip technology; c) packaging a cooling fin on the back side of the power chip by utilizing the Clip technology; d) using the loading adhesive technology to mount a control chip on the front side of the framework base island; e) employing bonding wires to connect functional pins on the control chip with framework pins; f) putting a framework after wire bonding in a processed mould, allowing the cooling fin to cling to the module for plastic package; and g) electroplating a product after plastic package, and then performing tendon-cutting forming. The invention combines the Bumping technology, the Flip-chip technology, the Clip technology, the loading adhesive technology and the wire bonding technology, and realizes the new 3D packaging technology.

Description

A kind of multi-chip 3 D packaging technology
Technical field
The present invention relates to a kind of multi-chip 3 D packaging technology.
Background technology
At present, common multi-chip package is main the most several again:
1, multi-chip is mounted on same Ji Dao, uses wire to be connected with pin by chip.Such as Fig. 1 a To shown in Fig. 1 d: this packaging technology is to be contained on same Ji Dao by multiple chips use load sticker, usual two Individual chip is respectively power chip 12 and control chip 13.Control chip 13 substrate is electronegative potential, power core Sheet 12 substrate is high potential, and both exist voltage difference by substrate electric potential.High potential one on power chip 12 substrate As be required for using conducting resinl and the island adhesion of framework base, draw high potential by Ji Dao.Now control chip 13 It is accomplished by using insulating cement and Ji Dao to carry out electrical isolation.Owing to the thickness of insulating cement is difficult to control to, and framework Easily there is sharp convex conductive particle in overlay coating, so that control chip 13 substrate leakage occurs with framework Ji Dao The phenomenon of electricity, affects properties of product and reliability.It addition, power chip 12 surface uses wire and pin phase Connecting, there is bonding wire and connect in big current loop, internal resistance is relatively big, affects electrical efficiency.
Its major defect is: uses insulating cement isolation between areas of high potential and electronegative potential region, there is electric leakage wind Danger；There is bonding wire in big current loop to connect, internal resistance is bigger.
2, multiple chips carry out stacked package, use wire to be connected with pin by chip.Such as Fig. 2 a to 2c Shown in:
This packaging technology is that multi-chip carries out stacking load, and power chip 22 uses load sticker to be contained in framework base On island 21, re-use insulating cement and control chip 23 is mounted on above power chip 22, then incited somebody to action by bonding wire Two chips are electrically connected, and form the structure of stacking load.This encapsulating structure necessarily requires power chip 22 areas are sufficiently large, it is possible to meet the requirement of attachment control chip 23 size, and require on these areas not Bonding wire can be carried out.Owing to power chip 22 uses bonding wire to connect, there is bigger bonding wire internal resistance so that big There is bonding wire in current loop to connect, internal resistance is relatively big, affects electrical efficiency.
Its major defect is: there is bonding wire in big current loop and connect, internal resistance is bigger；Power chip area is necessary Bigger than control chip area.
3, multi-chip Duo Ji island encapsulation, uses wire to be connected with pin by chip.As shown in Fig. 3 a to 3c:
This packaging technology is that power chip 32 and control chip 33 are mounted on single framework Ji Dao respectively On 31, re-use bonding wire and connect.The chip of this many bases island structure and framework are typically to be encapsulated in plastic packaging Internal portion, so that the thermal resistance of chip is higher, radiating effect is the best.Power chip 32 therein uses Bonding wire connects, and there is bigger bonding wire internal resistance, affects electrical efficiency.
Its major defect is: do not have fin, and radiating effect is the best；There is bonding wire in big current loop to connect, Internal resistance is bigger.
Summary of the invention
The present invention seeks to provide a kind of multi-chip 3 D packaging technology for the defect that prior art exists.
For achieving the above object, the first technical scheme of employing is as follows for the present invention:
A kind of multi-chip 3 D packaging technology, comprises the steps:
A) Bumping technique is used to grow multiple copper posts in the front of power chip；
B) use Flip-chip technique that power chip dress is attached to the back side of framework Ji Dao；
C) use Clip technique that fin is mounted on the back side of power chip；
D) use load adhesive process that control chip dress is attached to the front of framework Ji Dao；
E) bonding wire is used to be connected with framework foot position the function foot position on control chip；
F) framework welding line is put in treated mould, makes fin be close to mould and carry out plastic packaging；
G) Trim Molding after the product after plastic packaging being electroplated.
The second technical scheme used is as follows:
A kind of multi-chip 3 D packaging technology, comprises the steps:
A) Bumping technique is used to grow multiple copper posts in power chip front；
B) Clip technique is used to be mounted on a heat sink by power chip；
C) use Flip-chip technique that the power chip posting fin fills the back side being attached to framework Ji Dao；
D) use load adhesive process that control chip dress is attached to the front of framework Ji Dao；
E) bonding wire is used to be connected with framework foot position the function foot position on control chip；
F) framework welding line is put in treated mould, makes fin be close to mould and carry out plastic packaging；
G) Trim Molding after the product after plastic packaging being electroplated.
Beneficial effects of the present invention:
1, this invention is by Bumping technique, Flip-chip technique, Clip technique, load adhesive process and weldering Wiring technology combines, it is achieved a kind of new 3D packaging technology.
2, the present invention uses the technique at the two-sided load in framework base island, takes full advantage of Ji Dao space, effectively saves Save the area of framework Ji Dao, save material cost.
3, the present invention uses attachment fin mode and by exposed for fin on plastic-sealed body surface, is effectively increased The heat dispersion of packaging body.
4, the present invention is at framework base island two EDS maps attachment high potential chip and electronegative potential chip, make high potential with Electronegative potential is effectively isolated.
5, the present invention will use Flip-chip technique to mount power chip, it is to avoid uses bonding wire to connect, effectively Reduce the internal resistance of big current loop, improve electrical efficiency.
Accompanying drawing explanation
Fig. 1 a is that tradition multi-chip is with base island encapsulating structure floor map.
Fig. 1 b is that tradition multi-chip is with base island encapsulating structure schematic cross-section.
Fig. 1 c is the tradition multi-chip height potential areas schematic diagram with base island encapsulating structure.
Fig. 1 d is the tradition multi-chip big galvanic areas schematic diagram with base island encapsulating structure.
Fig. 2 a is tradition Multichip stacking encapsulation structural plan schematic diagram.
Fig. 2 b is tradition Multichip stacking encapsulation structural section schematic diagram.
Fig. 2 c is the big galvanic areas schematic diagram of tradition Multichip stacking encapsulation structure.
Fig. 3 a is tradition multi-chip Duo Ji island encapsulating structure floor map.
Fig. 3 b is tradition multi-chip Duo Ji island encapsulating structure schematic cross-section.
Fig. 3 c is the big galvanic areas schematic diagram of tradition multi-chip Duo Ji island encapsulating structure.
Fig. 4 a is 3D encapsulating structure floor map of the present invention.
Fig. 4 b is 3D encapsulating structure schematic cross-section of the present invention.
Fig. 4 c is the height potential areas schematic diagram of 3D encapsulating structure of the present invention.
Fig. 4 d is the big galvanic areas schematic diagram of 3D encapsulating structure of the present invention.
Fig. 4 e is the most exposed encapsulation schematic diagram when plastic-sealed body surface of fin in 3D encapsulating structure of the present invention.
Fig. 4 f is that 3D encapsulating structure of the present invention uses multiple power chips encapsulation schematic diagram.
Fig. 4 g is that 3D encapsulating structure of the present invention uses multiple control chips encapsulation schematic diagram.
Detailed description of the invention
Shown in Fig. 4 a, Fig. 4 b, disclosing a kind of multi-chip 3 D packaging technology, this technique is by Bumping work Skill, Flip-chip technique, Clip technique, load adhesive process and bonding wire craft combine, and multi-chip are mounted In the both sides of framework Ji Dao, finally give a kind of new 3D encapsulating structure.
The 3D encapsulating structure that above-mentioned technique obtains, specifically includes: plastic-sealed body 40, encapsulation in this plastic-sealed body 40 Having framework base island 41, the front on this framework base island 41 is at least pasted with a control chip 43, and described control It is provided with insulating cement 47 between chip 43 and framework base island 41；The back side on described framework base island 41 at least mounts Have between a power chip 42, and described power chip 42 and framework base island 41 and be evenly arranged with multiple copper Post 46；Together with the another side of described power chip 42 is mounted on fin by solder；Wherein, described control Function foot position on coremaking sheet 42 is connected with the framework foot position on described framework base island 41.
This technique specifically includes following steps:
A) Bumping technique is used to grow multiple copper posts in the front of power chip；
B) use Flip-chip technique that power chip dress is attached to the back side of framework Ji Dao；
C) by Clip technique, fin is mounted on the back side of power chip；
D) use load adhesive process that control chip dress is attached to the front of framework Ji Dao；
E) bonding wire is used to be connected with framework foot position the function foot position on control chip；
F) framework welding line is put in treated mould, makes fin be close to mould and carry out plastic packaging；
G) Trim Molding after the product after plastic packaging being electroplated.
The present invention, at framework base island two EDS maps attachment high potential chip and electronegative potential chip, makes high potential and low electricity The effective isolation in position；As illustrated in fig. 4 c.
The present invention will use Flip-chip technique to mount power chip, it is to avoid uses bonding wire to connect, effectively reduces The internal resistance of big current loop, improves electrical efficiency, as shown in figure 4d.
It addition, in the above-mentioned packaging technology of the present invention, operation b) and operation c) can exchange order, with Sample can realize this 3D encapsulating structure.Packaging technology flow process after exchange is as follows:
A) Bumping technique is used to grow multiple copper posts in power chip front；
B) solder process is used to be mounted on a heat sink by power chip；
C) use Flip-chip technique that the power chip posting fin fills the back side being attached to framework Ji Dao；
D) use load adhesive process that control chip dress is attached to the front of framework Ji Dao；
E) bonding wire is used to be connected with framework foot position the function foot position on control chip；
F) framework welding line is put in treated mould makes fin be close to mould to carry out plastic packaging；
G) Trim Molding after the product after plastic packaging being electroplated.
Wherein, when power chip does not has cooling requirements, in operation f), fin can not be attached to plastic packaging Surface, as shown in fig 4e.
Wherein, the control chip of framework Ji Dao both sides and the quantity of power chip are not limited only to one, Ke Yiduo Individual, at this moment the concerned process steps in technological process can be repeated several times and carry out, as shown in Fig. 4 f and Fig. 4 g.
It addition, packaging body type can be different, such as SOP, DFN, QFN etc. according to demand.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all in the present invention Spirit and principle within, any modification, equivalent substitution and improvement etc. made, should be included in this Within bright protection domain.

Claims (2)

1. a multi-chip 3 D packaging technology, it is characterised in that comprise the steps:
A) Bumping technique is used to grow multiple copper posts in the front of power chip；
B) use Flip-chip technique that power chip dress is attached to the back side of framework Ji Dao；
C) use Clip technique that fin is mounted on the back side of power chip；
D) use load adhesive process that control chip dress is attached to the front of framework Ji Dao；
E) bonding wire is used to be connected with framework foot position the function foot position on control chip；
F) framework welding line is put in treated mould, makes fin be close to mould and carry out plastic packaging；
G) Trim Molding after the product after plastic packaging being electroplated.
2. a multi-chip 3 D packaging technology, it is characterised in that comprise the steps:
A) Bumping technique is used to grow multiple copper posts in power chip front；
B) Clip technique is used to be mounted on a heat sink by power chip；
C) use Flip-chip technique that the power chip posting fin fills the back side being attached to framework Ji Dao；
D) use load adhesive process that control chip dress is attached to the front of framework Ji Dao；
E) bonding wire is used to be connected with framework foot position the function foot position on control chip；
F) framework welding line is put in treated mould makes fin be close to mould to carry out plastic packaging；
G) Trim Molding after the product after plastic packaging being electroplated.
CN201610204787.2A 2016-04-01 2016-04-01 Multi-chip 3D packaging technology Pending CN105845633A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018113573A1 (en) * 2016-12-21 2018-06-28 江苏长电科技股份有限公司 Three-dimensional packaging structure having low resistance loss and process method therefor
CN109659241A (en) * 2018-12-11 2019-04-19 沈阳中光电子有限公司 A method of connecting two types chip on the lead frames

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06181286A (en) * 1992-12-14 1994-06-28 Toshiba Corp Semiconductor device
US20050206010A1 (en) * 2004-03-18 2005-09-22 Noquil Jonathan A Multi-flip chip on lead frame on over molded IC package and method of assembly
US20090189266A1 (en) * 2008-01-28 2009-07-30 Yong Liu Semiconductor package with stacked dice for a buck converter
CN104600061A (en) * 2014-12-30 2015-05-06 杰群电子科技（东莞）有限公司 Stack-based 3D packaging structure of semiconductor chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06181286A (en) * 1992-12-14 1994-06-28 Toshiba Corp Semiconductor device
US20050206010A1 (en) * 2004-03-18 2005-09-22 Noquil Jonathan A Multi-flip chip on lead frame on over molded IC package and method of assembly
US20090189266A1 (en) * 2008-01-28 2009-07-30 Yong Liu Semiconductor package with stacked dice for a buck converter
CN104600061A (en) * 2014-12-30 2015-05-06 杰群电子科技（东莞）有限公司 Stack-based 3D packaging structure of semiconductor chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018113573A1 (en) * 2016-12-21 2018-06-28 江苏长电科技股份有限公司 Three-dimensional packaging structure having low resistance loss and process method therefor
CN109659241A (en) * 2018-12-11 2019-04-19 沈阳中光电子有限公司 A method of connecting two types chip on the lead frames
CN109659241B (en) * 2018-12-11 2021-05-11 沈阳中光电子有限公司 Method for connecting two types of chips on lead frame

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Application publication date: 20160810