CN110323199A - A kind of QFN encapsulating structure of more base island lead frame framves and power conversion module - Google Patents
A kind of QFN encapsulating structure of more base island lead frame framves and power conversion module Download PDFInfo
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- CN110323199A CN110323199A CN201910699362.7A CN201910699362A CN110323199A CN 110323199 A CN110323199 A CN 110323199A CN 201910699362 A CN201910699362 A CN 201910699362A CN 110323199 A CN110323199 A CN 110323199A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/411—Chip-supporting parts, e.g. die pads
- H10W70/415—Leadframe inner leads serving as die pads
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
- H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/461—Leadframes specially adapted for cooling
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/464—Additional interconnections in combination with leadframes
- H10W70/465—Bumps or wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/811—Multiple chips on leadframes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
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Abstract
Description
技术领域technical field
本发明涉及半导体封装技术领域,尤其涉及一种多基岛引线框架及电源转换模块的QFN封装结构。The invention relates to the technical field of semiconductor packaging, in particular to a QFN packaging structure of a multi-base island lead frame and a power conversion module.
背景技术Background technique
随着集成电路IC设计、制造行业得到飞速发展,封装技术也得到了大幅提升。封装是整个集成电路制造过程中重要一环,它具有散热和保护功能。封装工艺能够将芯片密封,隔绝外界污染及外力对芯片的破坏。With the rapid development of integrated circuit IC design and manufacturing industry, packaging technology has also been greatly improved. Packaging is an important part of the entire integrated circuit manufacturing process, which has the functions of heat dissipation and protection. The packaging process can seal the chip and isolate the damage from external pollution and external force.
随着技术的进步,在一个封装体中封装两颗芯片已经不能满足需求。在一个封装体中封装多颗芯片,成为了技术发展的方向。现有的在每一个基岛上放置一个芯片的多基岛框架在实际应用时,各引脚因为高低电压差异比较大,非常容易相互之间击穿,进而无法满足封装或可靠性的要求。With the advancement of technology, it is no longer sufficient to package two chips in one package. Encapsulating multiple chips in one package has become the direction of technological development. In practical application of the existing multi-base island frame with one chip placed on each base island, each pin is very easy to break down due to the large difference in high and low voltage, and thus cannot meet the requirements of packaging or reliability.
低成本、超薄型、高散热贴片封装一直是半导体封装的开发方向,随着国家大力倡导环保节能,电机行业也迎来了春天,电机驱动技术发展突飞猛进。芯片面积越来越小,功率越来越大,使用环境越来越极限,散热要求越来越高,市场竞争日益激烈,成本竞争尤为突出。传统的DIP/SOP IPM封装结构,存在散热性欠佳、成本高、封装兼容性欠佳,可选供应商较少等缺点。Low-cost, ultra-thin, high heat dissipation chip packaging has always been the development direction of semiconductor packaging. With the country's vigorous advocacy of environmental protection and energy conservation, the motor industry has also ushered in the spring, and motor drive technology has developed by leaps and bounds. The chip area is getting smaller and smaller, the power is getting bigger and bigger, the usage environment is getting more and more extreme, the heat dissipation requirement is getting higher and higher, the market competition is getting more and more intense, and the cost competition is particularly prominent. The traditional DIP/SOP IPM package structure has disadvantages such as poor heat dissipation, high cost, poor package compatibility, and few optional suppliers.
目前市场上也出现了QFN封装形式,传统的QFN封装通常是用来封装存储类的芯片。电源转换类的芯片由于功耗大,散热要求高,管脚之间安全间距等一系列的问题,不太适用于QFN封装针对存储类芯片的封装工艺。因此,如何解决DIP/SOP IPM现有封装结构体积大、成本高、兼容性差、散热欠佳等问题,成为多基岛引线框架及半导体封装发展亟待解决的技术问题。At present, the QFN package has also appeared on the market. The traditional QFN package is usually used to package memory chips. Due to a series of problems such as high power consumption, high heat dissipation requirements, and safe spacing between pins, power conversion chips are not suitable for the packaging process of QFN packaging for memory chips. Therefore, how to solve the problems of large volume, high cost, poor compatibility, and poor heat dissipation of the existing DIP/SOP IPM packaging structure has become an urgent technical problem to be solved in the development of multi-base island lead frames and semiconductor packaging.
发明内容SUMMARY OF THE INVENTION
本发明的目的在于,针对现有技术中存在的技术问题,提供一种多基岛引线框架及电源转换模块的QFN封装结构,可以实现封装结构的封装体积小、成本低、散热高、集成度高、兼容性好等优点。The purpose of the present invention is to provide a QFN package structure of a multi-base island lead frame and a power conversion module in view of the technical problems existing in the prior art, which can realize the package structure with small package volume, low cost, high heat dissipation and integration. High, good compatibility and so on.
为实现上述目的,本发明提供了一种应用于电源转换模块QFN封装的多基岛引线框架,至少包括:相互之间电气隔离的一第一基岛以及一第二基岛;所述第一基岛具有用于承载功率器件的一第一承载面,以及与所述第一承载面相对的一第一散热面,所述第一基岛具有设置于所述多基岛引线框架至少一边、并与所述第一基岛本体直接连接的多个第一引脚;所述第二基岛具有用于承载控制所述功率器件的主控芯片的一第二承载面,以及与所述第二承载面相对的一第二散热面,所述第二基岛具有设置于所述多基岛引线框架两相邻边、并与所述第二基岛本体分离的多个第二引脚;其中,在所述多基岛引线框架应用于QFN封装被塑封体进行塑封后,相应散热面部分或全部暴露于所述塑封体,并且所有引脚的端部以及与相应散热面共面的底面部分暴露于所述塑封体。In order to achieve the above object, the present invention provides a multi-base island lead frame applied to a QFN package of a power conversion module, which at least includes: a first base island and a second base island that are electrically isolated from each other; the first base island; The base island has a first carrying surface for carrying power devices, and a first heat dissipation surface opposite to the first carrying surface, and the first base island has at least one side disposed on the multi-base island lead frame, A plurality of first pins directly connected to the first base island body; the second base island has a second bearing surface for carrying the main control chip for controlling the power device, and is connected to the first base island. A second heat dissipation surface opposite the two bearing surfaces, the second base island has a plurality of second pins disposed on two adjacent sides of the multi-base island lead frame and separated from the second base island body; Wherein, after the multi-base island lead frame is applied to the QFN package and is plastic-sealed by the plastic-sealed body, a part or all of the corresponding heat dissipation surface is exposed to the plastic-sealed body, and the ends of all the pins and the bottom surface coplanar with the corresponding heat-dissipating surface Parts are exposed to the molding.
为实现上述目的,本发明还提供了一种电源转换模块的QFN封装结构,包括:一多基岛引线框架,所述多基岛引线框架至少包括相互之间电气隔离的一第一基岛以及一第二基岛;所述第一基岛具有一第一承载面,以及与所述第一承载面相对的一第一散热面,所述第一基岛具有设置于所述多基岛引线框架至少一边、并与所述第一基岛本体直接连接的多个第一引脚;所述第二基岛具有一第二承载面,以及与所述第二承载面相对的一第二散热面,所述第二基岛具有设置于所述多基岛引线框架两相邻边、并与所述第二基岛本体分离的多个第二引脚;一第一功率器件,设置于所述第一承载面上,并与所述第一引脚直接连接;一控制所述第一功率器件的主控芯片,设置于所述第二承载面上,所述主控芯片通过金属引线分别与所述第二引脚以及所述第一功率器件电性连接;以及一塑封体,塑封承载所述第一功率器件和所述主控芯片的所述多基岛引线框架;其中,相应散热面部分或全部暴露于所述塑封体,并且所有引脚的端部以及与相应散热面共面的底面部分暴露于所述塑封体;所述第一引脚的工作电压与所述第二引脚的工作电压不相同。In order to achieve the above object, the present invention also provides a QFN package structure of a power conversion module, comprising: a multi-base island lead frame, the multi-base island lead frame at least includes a first base island that is electrically isolated from each other; a second base island; the first base island has a first bearing surface and a first heat dissipation surface opposite to the first bearing surface, the first base island has leads disposed on the multi-base island at least one side of the frame and a plurality of first pins directly connected to the first base island body; the second base island has a second bearing surface, and a second heat dissipation surface opposite to the second bearing surface surface, the second base island has a plurality of second pins disposed on two adjacent sides of the multi-base island lead frame and separated from the second base island body; a first power device disposed on the the first carrying surface, and is directly connected to the first pin; a main control chip for controlling the first power device is disposed on the second carrying surface, and the main control chip is respectively connected by metal leads is electrically connected with the second pin and the first power device; and a plastic packaging body, which plastically encapsulates the multi-base island lead frame carrying the first power device and the main control chip; wherein the corresponding heat dissipation Part or all of the surface is exposed to the plastic package, and the ends of all pins and the bottom surface part coplanar with the corresponding heat dissipation surface are exposed to the plastic package; the working voltage of the first pin is the same as that of the second pin. The working voltage of the pins is not the same.
本发明的优点在于:实现了多芯片/器件集成平面封装,提高了集成度,缩小了封装体体积、降低了封装成本;通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的;封装结构内部各基岛之间电气隔离,且基岛与基岛之间设置了安全隔离间距,封装结构外漏散热面之间、引脚与引脚之间、分离式引脚与散热面之间均进行安全间距设计,可以有效防止高压击穿,进而满足封装或可靠性的要求。The advantages of the present invention are that: multi-chip/device integrated plane packaging is realized, the integration degree is improved, the volume of the package body is reduced, and the packaging cost is reduced; The PCB is fully contacted to achieve the purpose of high heat dissipation; the base islands inside the package structure are electrically isolated, and a safety isolation distance is set between the base islands and the base islands, and the package structure leaks between the heat dissipation surfaces and between the pins and the pins. , A safe spacing is designed between the separated pins and the heat dissipation surface, which can effectively prevent high-voltage breakdown, thereby meeting the requirements of packaging or reliability.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图。In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.
图1,本发明引线框架的一实施例的平面结构示意图;FIG. 1 is a schematic plan view of an embodiment of the lead frame of the present invention;
图2A,本发明电源转换模块的QFN封装结构第一实施例的打线结构示意图;FIG. 2A is a schematic diagram of the wire bonding structure of the first embodiment of the QFN packaging structure of the power conversion module of the present invention;
图2B为图2A所示QFN封装结构的仰视图;2B is a bottom view of the QFN package structure shown in FIG. 2A;
图2C为图2A所示QFN封装结构的侧视图;FIG. 2C is a side view of the QFN package structure shown in FIG. 2A;
图3,本发明电源转换模块的QFN封装结构第二实施例的打线结构示意图。FIG. 3 is a schematic diagram of the wire bonding structure of the second embodiment of the QFN packaging structure of the power conversion module of the present invention.
具体实施方式Detailed ways
下面将结合附图,对本发明实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。本发明的说明书和权利要求书以及附图中的术语“第一”、“第二”、“第三”等(如果存在)是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。应当理解,这样描述的对象在适当情况下可以互换。此外,术语“包括”和“具有”以及它们的任何变形,意图在于覆盖不排它的包含。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention. The terms "first", "second", "third", etc. (if present) in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion.
请参阅图1,本发明多基岛引线框架一实施例的平面结构示意图。本发明多基岛引线框架10应用于电源转换模块QFN封装,所述多基岛引线框架10在与电子组件通过QFN封装塑封后,能够形成一个独立的QFN封装结构20(标示于图2A中),其中所述多基岛引线框架10的封装线采用虚线框示意性标示出。所述多基岛引线框架10包括相互之间电气隔离的多个基岛。在本实施例中,示意性地绘示出四个相互之间电气隔离的基岛,分别为第一基岛11、第二基岛12、第三基岛13以及第四基岛14。其中,所述第一基岛11的面积大于所述第二基岛12的面积。在其它实施例中,所述多基岛引线框架10也可以包括三个相互之间电气隔离的基岛,例如包括第一基岛11、第二基岛12以及第三基岛13,或包括第一基岛11、第二基岛12以及第四基岛14。Please refer to FIG. 1 , which is a schematic plan view of a multi-base island lead frame according to an embodiment of the present invention. The multi-base island lead frame 10 of the present invention is applied to the QFN package of a power conversion module. The multi-base island lead frame 10 can form an independent QFN package structure 20 (marked in FIG. 2A ) after being plastic-sealed with the electronic components through the QFN package. , wherein the packaging lines of the multi-base-island lead frame 10 are schematically indicated by a dotted frame. The multi-base island lead frame 10 includes a plurality of base islands that are electrically isolated from each other. In this embodiment, four base islands that are electrically isolated from each other are schematically depicted, namely, a first base island 11 , a second base island 12 , a third base island 13 and a fourth base island 14 . Wherein, the area of the first base island 11 is larger than the area of the second base island 12 . In other embodiments, the multi-base-island lead frame 10 may also include three base islands that are electrically isolated from each other, such as a first base island 11 , a second base island 12 and a third base island 13 , or include The first base island 11 , the second base island 12 and the fourth base island 14 .
在本实施例中,所述第一基岛11具有用于承载第一功率器件21(标示于图2A中)的一第一承载面111,以及与所述第一承载面111相对的一第一散热面112(标示于图2B中),所述第一基岛11具有设置于所述多基岛引线框架10两相邻边上、并与所述第一基岛本体110直接连接的多个第一引脚113。其中,在所述多基岛引线框架10应用于QFN封装被塑封体进行塑封后,所述第一散热面112部分或全部暴露于所述塑封体,并且所有第一引脚113的端部以及与所述第一散热面112共面的底面部分暴露于所述塑封体。通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的。在本实施例中,示意性地绘示出九个第一引脚113,在其它实施例中,所述第一引脚113数目不限,设置位置也可以仅位于所述多基岛引线框架10的一侧边上,只要满足本发明的目的即可。所述第一功率器件21包括但不限于三极管,MOS管,晶闸管,绝缘栅双极型晶体管(IGBT)和快恢复二极管(FRD)的组合等。In this embodiment, the first base island 11 has a first carrying surface 111 for carrying the first power device 21 (marked in FIG. 2A ), and a first carrying surface 111 opposite to the first carrying surface 111 . A heat dissipation surface 112 (shown in FIG. 2B ), the first base island 11 has multiple base islands disposed on two adjacent sides of the multiple base island lead frame 10 and directly connected to the first base island body 110 a first pin 113 . Wherein, after the multi-base-island lead frame 10 is applied to the QFN package and is plastic-sealed by the plastic-sealed body, the first heat dissipation surface 112 is partially or completely exposed to the plastic-sealed body, and the ends of all the first pins 113 and A portion of the bottom surface coplanar with the first heat dissipation surface 112 is exposed to the molding body. By encapsulating the base island to maximize external leakage, the external leakage heat dissipation surface can be fully contacted with the PCB in the follow-up to achieve the purpose of high heat dissipation. In this embodiment, nine first pins 113 are schematically drawn. In other embodiments, the number of the first pins 113 is not limited, and the setting positions may only be located in the multi-base island lead frame On one side of 10, as long as the purpose of the present invention is satisfied. The first power device 21 includes, but is not limited to, a triode, a MOS transistor, a thyristor, a combination of an insulated gate bipolar transistor (IGBT) and a fast recovery diode (FRD).
具体的,每一所述第一引脚113均与所述第一基岛本体110直接连接,其作为所述第一基岛11的主散热引脚和功能性引脚与外界电连接。由于所述第一引脚113与所述第一基岛本体110直接连接,在后续使用中,该引脚既可以耦接至地,也可以接高压引脚;或者该引脚可以仅作为高压引脚使用。同时,所有所述第一引脚113还在所述多基岛引线框架10应用于QFN封装进行塑封时,对面积较大的所述第一基岛11起到支撑的作用。Specifically, each of the first pins 113 is directly connected to the first base island body 110 , and is electrically connected to the outside world as a main heat dissipation pin and a functional pin of the first base island 11 . Since the first pin 113 is directly connected to the first base island body 110, in subsequent use, the pin can be coupled to the ground or a high-voltage pin; or the pin can only be used as a high-voltage pin pin usage. At the same time, all the first pins 113 also play a supporting role for the first base island 11 with a larger area when the multi-base island lead frame 10 is applied to the QFN package for plastic packaging.
进一步的实施例中,所述多基岛引线框架10一侧边上的所有所述第一引脚113可以由一个宽度较宽(大于一第一预设宽度,例如小于或等于所述第一基岛本体110的宽度)的直连式引脚分割而成。由于宽度较宽的直连式引脚的应力较大,在切割制程中不易切断,给切筋成型带来难题,且有塑封体暗裂的风险;而宽度太窄,影响塑封后的封装体通过引脚向外散热的性能。在本发明通过将该直连式引脚分割成多个宽度较窄(小于一第二预设宽度)的第一引脚113,使得所述第一引脚113的切筋成型的应力减小,而多个所述第一引脚113的总宽度较宽,提高了塑封后的封装体通过引脚向外散热的性能,可以在保证散热性能基本不变的前提下,解决了不易切筋成型的难题,同时也避免了塑封体暗裂的风险。进一步,在本发明中,所述多基岛引线框架10的两相邻边上与所述第一基岛本体110直接连接的直连式引脚均分割成多个所述第一引脚113;或者一侧边上的直连式引脚分割成多个所述第一引脚113,另一侧边上的直连式引脚不进行分割。In a further embodiment, all the first pins 113 on one side of the multi-base-island lead frame 10 may have a wider width (greater than a first predetermined width, for example, less than or equal to the first The width of the base island body 110 ) is divided into directly connected pins. Due to the large stress of the direct-connected pins with a wide width, it is not easy to cut off during the cutting process, which brings difficulties to the forming of the cutting ribs, and there is a risk of dark cracking of the plastic package; and the width is too narrow, which affects the package body after plastic sealing. The ability to dissipate heat out through the pins. In the present invention, by dividing the direct-connected lead into a plurality of first leads 113 with narrower widths (less than a second predetermined width), the stress of the rib forming of the first leads 113 is reduced. , and the total width of the plurality of first pins 113 is relatively wide, which improves the performance of the plastic-encapsulated package body to dissipate heat outward through the pins, and can solve the problem of difficulty in cutting ribs on the premise of ensuring that the heat dissipation performance is basically unchanged. The problem of molding is also avoided, and the risk of cracking of the plastic body is avoided. Further, in the present invention, the direct connection pins directly connected to the first base island body 110 on the two adjacent sides of the multi-base island lead frame 10 are divided into a plurality of the first pins 113 ; or the direct-connected pins on one side are divided into a plurality of the first pins 113, and the direct-connected pins on the other side are not divided.
进一步的实施例中,所述第一承载面111上用于承载所述第一功率器件21的区域之外设有至少一糙面区119。所述糙面区119可以通过在所述第一承载面111上相应区域采用半蚀刻工艺实现,通过半蚀刻工艺,增加所述糙面区119的表面粗糙度,其作用在于增强所述多基岛引线框架10与后续封装工艺的塑封体的结合力。由于本发明对应的产品与现有的封装体相比而言,封装体积更小,包封强度更弱,产品容易分层,而通过增加所述糙面区119的设计,增加了所述多基岛引线框架10与塑封体的结合力,避免产品分层,提升了产品的可靠性。在本实施例中,所述第一承载面111上设有两个所述糙面区119,分别位于在所述框架本体两相邻边缘的夹角处,和靠近所述第三基岛13的一侧,进一步提高了所述多基岛引线框架10与塑封体的结合力。在其它实施例中,所述糙面区119可以仅设置在所述框架本体两相邻边缘的夹角处,或仅设置在靠近所述第三基岛13的一侧。本发明对所述糙面区119的形状、数量及设置位置不进行限定,其形状可根据设置位置进行设计,其数量可以根据需要进行调整。In a further embodiment, at least one rough surface area 119 is provided on the first bearing surface 111 outside the area for bearing the first power device 21 . The rough surface area 119 can be realized by adopting a half-etching process in the corresponding area on the first bearing surface 111. Through the half-etching process, the surface roughness of the rough surface area 119 is increased, and its function is to enhance the multi-base surface roughness. The bonding force between the island lead frame 10 and the plastic encapsulation body of the subsequent encapsulation process. Compared with the existing package body, the product corresponding to the present invention has smaller package volume, weaker package strength, and the product is easy to be delaminated. The bonding force between the base island lead frame 10 and the plastic packaging body avoids product delamination and improves product reliability. In this embodiment, the first bearing surface 111 is provided with two rough surface areas 119 , which are respectively located at the included angle between two adjacent edges of the frame body and close to the third base island 13 . side, which further improves the bonding force between the multi-base island lead frame 10 and the plastic package. In other embodiments, the roughened surface area 119 may be provided only at the included angle between two adjacent edges of the frame body, or only at the side close to the third base island 13 . The present invention does not limit the shape, quantity and setting position of the rough surface area 119 , the shape can be designed according to the setting position, and the quantity can be adjusted as required.
进一步的实施例中,所述第一承载面111上用于承载所述第一功率器件21的区域之外设有至少一打线区118,用于通过金属引线25(标示于图2A中)实现所述第一基岛11与其它基岛上承载的芯片或器件的电性连接。例如,在本实施例中,所述第一承载面111上设有两个所述打线区118,其中一个采用金属引线25与设置在所述第三基岛13上的第二功率器件23(标示于图2A中)连接,另一个采用金属引线25与设置在所述第二基岛12上的主控芯片22(标示于图2A中)连接。所述打线区118可以通过在所述第一承载面111上相应区域采用镀银、或镀锡等工艺实现。In a further embodiment, at least one wire bonding area 118 is provided on the first carrying surface 111 outside the area for carrying the first power device 21 for passing through the metal leads 25 (marked in FIG. 2A ) The electrical connection between the first base island 11 and the chips or devices carried on other base islands is realized. For example, in this embodiment, the first carrying surface 111 is provided with two of the wire bonding areas 118 , one of which uses the metal lead 25 and the second power device 23 disposed on the third base island 13 . (marked in FIG. 2A ) is connected, and the other is connected with the main control chip 22 (marked in FIG. 2A ) disposed on the second base island 12 by using metal leads 25 . The wire bonding area 118 may be implemented by silver plating or tin plating or other processes on the corresponding area on the first bearing surface 111 .
在本实施例中,所述第二基岛12具有用于承载控制所述第一功率器件21的主控芯片22的一第二承载面121,以及与所述第二承载面121相对的一第二散热面122(标示于图2B中),所述第二基岛12具有设置于所述多基岛引线框架10两相邻边、并与所述第二基岛本体120分离的多个第二引脚123。其中,在所述多基岛引线框架10应用于QFN封装被塑封体进行塑封后,所述第二散热面122部分或全部暴露于所述塑封体,并且所有第二引脚123的端部以及与所述第二散热面122共面的底面部分暴露于所述塑封体。通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的。在本实施例中,示意性地绘示出十个第二引脚123,其中可包括一备用引脚(可用于连接热敏电阻)。在其它实施例中,所述第一引脚113数目不限,设置位置也可以仅位于所述多基岛引线框架10的一侧边上,只要满足本发明的目的即可。所述主控芯片22即为集成电路芯片(IC),用于控制所述第一功率器件21。In this embodiment, the second base island 12 has a second carrying surface 121 for carrying the main control chip 22 for controlling the first power device 21 , and a second carrying surface 121 opposite to the second carrying surface 121 . The second heat dissipation surface 122 (shown in FIG. 2B ) has a plurality of second base islands 12 disposed on two adjacent sides of the multi-base island lead frame 10 and separated from the second base island body 120 The second pin 123 . Wherein, after the multi-base-island lead frame 10 is applied to the QFN package to be molded by the molded body, the second heat dissipation surface 122 is partially or completely exposed to the molded body, and the ends of all the second pins 123 and A portion of the bottom surface coplanar with the second heat dissipation surface 122 is exposed to the molding body. By encapsulating the base island to maximize external leakage, the external leakage heat dissipation surface can be fully contacted with the PCB in the follow-up to achieve the purpose of high heat dissipation. In this embodiment, ten second pins 123 are schematically shown, which may include a spare pin (which may be used to connect the thermistor). In other embodiments, the number of the first pins 113 is not limited, and the arrangement position may only be located on one side of the multi-base island lead frame 10, as long as the purpose of the present invention is satisfied. The main control chip 22 is an integrated circuit chip (IC) for controlling the first power device 21 .
进一步的实施例中,所述第二引脚123上设置有打线区1231,用于通过金属引线25实现所述第二引脚123与所述第二承载面121上承载的主控芯片22,或与所述第一承载面111上承载的第一功率器件21的电性连接。其中,在后续使用时,所述第二引脚123的工作电压与所述第一引脚113的工作电压不相同,两基岛通过电气隔离,避免引脚之间由于高低电压差异比较大,而引起的相互之间击穿的情况发生,进而满足封装或可靠性的要求。所述第二引脚123不与所述第二基岛本体120直接连接,其上设置有打线区,通过镀银或镀锡后,能够与设置在所述第二基岛12上的主控芯片22或与设置在所述第一基岛11上的第一功率器件21采用金属引线25连接,并作为后续形成的QFN封装结构20的功能性引脚与外界电连接。例如,在本实施例中,五个第二引脚123采用金属引线25与设置在所述第二基岛12上的主控芯片22连接,另外三个第二引脚123采用金属引线25与设置在所述第一基岛11上的第一功率器件21连接。位于同一侧的第二引脚123和第一引脚113之间至少间隔预设安全间距,以降低两引脚之间工作电压差带来的击穿风险。In a further embodiment, the second pin 123 is provided with a wire bonding area 1231 for realizing the second pin 123 and the main control chip 22 carried on the second bearing surface 121 through the metal lead 25 . , or the electrical connection with the first power device 21 carried on the first carrying surface 111 . Wherein, in subsequent use, the working voltage of the second pin 123 is different from the working voltage of the first pin 113, and the two base islands are electrically isolated to avoid the large difference between the pins due to the high and low voltage. The resulting breakdown occurs between each other, thereby meeting the requirements of packaging or reliability. The second pin 123 is not directly connected to the second base island body 120, and is provided with a wire bonding area. After silver plating or tin plating, it can be connected with the main body disposed on the second base island 12. The control chip 22 or the first power device 21 disposed on the first base island 11 is connected with metal leads 25, and is electrically connected to the outside as a functional pin of the subsequently formed QFN package structure 20. For example, in this embodiment, five second pins 123 are connected to the main control chip 22 disposed on the second base island 12 by using metal leads 25 , and the other three second pins 123 are connected to the main control chip 22 provided on the second base island 12 by using metal leads 25 . The first power device 21 disposed on the first base island 11 is connected. There is at least a predetermined safety distance between the second pin 123 and the first pin 113 on the same side, so as to reduce the risk of breakdown caused by the difference in operating voltage between the two pins.
进一步的实施例中,所述第二基岛12还具有至少一支撑结构124,用于在所述多基岛引线框架10应用于QFN封装进行塑封时,支撑所述第二基岛12。具体的,所述支撑结构124与所述第二基岛本体120直接连接,并延伸至所述多基岛引线框架10两相邻边。例如,靠近所述第四基岛14的一第二引脚123侧的边框结构直接与所述第二基岛本体120连接,形成支撑结构;靠近所述第一基岛11的一第二引脚123侧的边框结构也直接与所述第二基岛本体120连接,形成支撑结构。优选的,除两侧的第二引脚123延伸有支撑结构外,还可以包括至少一第二引脚123侧的边框结构也直接与所述第二基岛本体120连接,形成支撑结构(如图中虚线圆圈框出的部分所示)。In a further embodiment, the second base island 12 further has at least one support structure 124 for supporting the second base island 12 when the multi-base island lead frame 10 is applied to the QFN package for plastic packaging. Specifically, the support structure 124 is directly connected to the second base island body 120 and extends to two adjacent sides of the multi-base island lead frame 10 . For example, a frame structure close to a second lead 123 of the fourth base island 14 is directly connected to the second base island body 120 to form a support structure; a second lead close to the first base island 11 The frame structure on the side of the feet 123 is also directly connected with the second base island body 120 to form a support structure. Preferably, in addition to the supporting structures extending from the second pins 123 on both sides, at least one frame structure on the side of the second pin 123 may also be directly connected to the second base island body 120 to form a supporting structure (eg The part enclosed by the dashed circle in the figure).
在本实施例中,所述第三基岛13与所述第一基岛11结构相同且对称设置于所述多基岛引线框架10上。In this embodiment, the third base island 13 has the same structure as the first base island 11 and is symmetrically disposed on the multi-base island lead frame 10 .
具体的,所述第三基岛13具有用于承载第二功率器件23的一第三承载面131,以及与所述第三承载面131相对的一第三散热面132(标示于图2B中),所述第三基岛13具有设置于所述多基岛引线框架10两相邻边上、并与所述第三基岛本体130直接连接的多个第三引脚133。其中,在所述多基岛引线框架10应用于QFN封装被塑封体进行塑封后,所述第三散热面132部分或全部暴露于所述塑封体,并且所有第三引脚133的端部以及与所述第三散热面132共面的底面部分暴露于所述塑封体。通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的。在本实施例中,示意性地绘示出九个第三引脚133,在其它实施例中,所述第三引脚133数目不限,设置位置也可以仅位于所述多基岛引线框架10的一侧边上,只要满足本发明的目的即可。所述第二功率器件23包括但不限于三极管,MOS管,晶闸管,绝缘栅双极型晶体管(IGBT)和快恢复二极管(FRD)的组合等。Specifically, the third base island 13 has a third carrying surface 131 for carrying the second power device 23 , and a third heat dissipation surface 132 (marked in FIG. 2B ) opposite to the third carrying surface 131 ), the third base island 13 has a plurality of third pins 133 disposed on two adjacent sides of the multi-base island lead frame 10 and directly connected to the third base island body 130 . Wherein, after the multi-base-island lead frame 10 is applied to the QFN package and is molded by the molded body, the third heat dissipation surface 132 is partially or completely exposed to the molded body, and the ends of all the third pins 133 and A portion of the bottom surface coplanar with the third heat dissipation surface 132 is exposed to the molding body. By encapsulating the base island to maximize external leakage, the external leakage heat dissipation surface can be fully contacted with the PCB in the follow-up to achieve the purpose of high heat dissipation. In this embodiment, nine third pins 133 are schematically drawn. In other embodiments, the number of the third pins 133 is not limited, and the setting positions may only be located in the multi-base island lead frame On one side of 10, as long as the purpose of the present invention is satisfied. The second power device 23 includes, but is not limited to, a triode, a MOS transistor, a thyristor, a combination of an insulated gate bipolar transistor (IGBT) and a fast recovery diode (FRD).
具体的,每一所述第三引脚133均与所述第三基岛本体130直接连接,其作为所述第三基岛13的主散热引脚和功能性引脚与外界电连接。由于所述第三引脚133与所述第三基岛本体130直接连接,在后续使用时,可作为低压引脚使用(例如作接地功能使用),或者也可作为高压引脚使用。其中,在后续使用时,所述第三引脚133的工作电压与所述第一引脚113的工作电压不相同;例如,所述第一引脚113可以为低压(电压小于或等于一预设电压,例如0V)引脚,相应的所述第三引脚133为高压(电压大于或等于一预设电压,例如500V)引脚;或者第一引脚113可以为高压引脚,相应的所述第三引脚133为低压引脚。在此例举的实施例中,由于第一基岛11和第三基岛13上的两款功率芯片是交替工作在高低压状态下,因此,第一基岛11和第三基岛之间需要保持预设的安全间距,预防第一基岛11和第三基岛13上功率器件交替工作在高低压状态下时发生击穿。所有所述第三引脚133还在所述多基岛引线框架10应用于QFN封装进行塑封时,起到支撑所述第三基岛13的作用。所述第三引脚133的设置方式与功能可参考所述第一引脚113的记载,此处不再赘述。Specifically, each of the third pins 133 is directly connected to the third base island body 130 , which is used as a main heat dissipation pin and a functional pin of the third base island 13 to be electrically connected to the outside world. Since the third pin 133 is directly connected to the third base island body 130 , it can be used as a low-voltage pin (for example, a grounding function) or a high-voltage pin in subsequent use. Wherein, in subsequent use, the working voltage of the third pin 133 is different from the working voltage of the first pin 113; for example, the first pin 113 may be a low voltage (voltage less than or equal to a predetermined Set a voltage, such as 0V) pin, the corresponding third pin 133 is a high-voltage (voltage greater than or equal to a preset voltage, such as 500V) pin; or the first pin 113 can be a high-voltage pin, the corresponding The third pin 133 is a low voltage pin. In this exemplary embodiment, since the two power chips on the first base island 11 and the third base island 13 work alternately in the high and low voltage states, therefore, between the first base island 11 and the third base island 13 A preset safe distance needs to be maintained to prevent breakdown from occurring when the power devices on the first base island 11 and the third base island 13 work alternately under high and low voltage states. All the third pins 133 also play a role of supporting the third base island 13 when the multi-base island lead frame 10 is applied to the QFN package for plastic packaging. For the setting method and function of the third pin 133, reference may be made to the description of the first pin 113, which will not be repeated here.
相应的,所述第三承载面131上用于承载所述第二功率器件23的区域之外也设有至少一糙面区139,以及至少一打线区138,可参考所述第一基岛11对应的记载,此处不再赘述。Correspondingly, at least one rough surface area 139 and at least one wire bonding area 138 are also provided on the third carrying surface 131 outside the area used to carry the second power device 23 , please refer to the first base The records corresponding to the island 11 will not be repeated here.
在本实施例中,所述第四基岛14具有用于承载分立器件24(标示于图2A中)的一第四承载面141,以及与所述第四承载面141相对的一第四散热面142(标示于图2B中),所述第四基岛14具有设置于所述多基岛引线框架10两相邻边的多个第四引脚143。第四引脚143可以与所述第四基岛本体140直接连接,或并与所述第四基岛本体140分离,并通过金属引线25与其它基岛上的引脚、芯片或器件电性连接。在一些实施例中,若该分立器件为功率型的器件,例如二极管,对散热要求较高,建议第四引脚143与第四基岛本体140直连,以提高第四基岛14的散热效率。其中,在所述多基岛引线框架10应用于QFN封装被塑封体进行塑封后,所述第四散热面142部分或全部暴露于所述塑封体,并且所有第四引脚143的端部以及与所述第四散热面142共面的底面部分暴露于所述塑封体。通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的。所述第四承载面141上还设有打线区148,打线区148的设置方式及功能可参考所述第一基岛11上打线区118对应的记载,此处不再赘述。所述分立器件24可以为二极管芯片,例如续流二极管。In this embodiment, the fourth base island 14 has a fourth carrying surface 141 for carrying the discrete devices 24 (marked in FIG. 2A ), and a fourth heat dissipation surface opposite to the fourth carrying surface 141 On the surface 142 (marked in FIG. 2B ), the fourth base island 14 has a plurality of fourth pins 143 disposed on two adjacent sides of the multi-base island lead frame 10 . The fourth pin 143 can be directly connected to the fourth base island body 140 , or be separated from the fourth base island body 140 , and electrically connected to pins, chips or devices on other base islands through the metal leads 25 . connect. In some embodiments, if the discrete device is a power-type device, such as a diode, which has high requirements for heat dissipation, it is recommended that the fourth pin 143 be directly connected to the fourth base island body 140 to improve the heat dissipation of the fourth base island 14 efficiency. Wherein, after the multi-base-island lead frame 10 is applied to the QFN package and is molded by the molded body, part or all of the fourth heat dissipation surface 142 is exposed to the molded body, and the ends of all the fourth pins 143 and A portion of the bottom surface coplanar with the fourth heat dissipation surface 142 is exposed to the molding body. By encapsulating the base island to maximize external leakage, the external leakage heat dissipation surface can be fully contacted with the PCB in the follow-up to achieve the purpose of high heat dissipation. The fourth bearing surface 141 is further provided with a wire bonding area 148 . For the arrangement and function of the wire bonding area 148 , reference may be made to the description corresponding to the wire bonding area 118 on the first base island 11 , which will not be repeated here. The discrete device 24 may be a diode chip, such as a freewheeling diode.
在本实施例中,所述第一基岛11的面积大于所述第二基岛12及所述第四基岛14的面积,从而利于放置功率型器件。若该封装结构内需要同时封装两个功率型器件,那么还可以设置与所述第一基岛11对称的第三基岛13。所述第一基岛11及所述第三基岛13设置在所述多基岛引线框架10的同一侧,所述第二基岛12及所述第四基岛14设置在所述多基岛引线框架10的同一侧,实现多芯片/器件集成平面封装,提高了集成度,进而缩小封装体体积。其它实施例中,可能衍生与本实施例不同尺寸、不同基岛位置的四基岛设计,或三基岛设计。In this embodiment, the area of the first base island 11 is larger than the areas of the second base island 12 and the fourth base island 14 , so as to facilitate placement of power devices. If the package structure needs to package two power devices at the same time, a third base island 13 that is symmetrical with the first base island 11 may also be provided. The first base island 11 and the third base island 13 are disposed on the same side of the multi-base lead frame 10 , and the second base island 12 and the fourth base island 14 are disposed on the multi-base lead frame 10 . On the same side of the island lead frame 10 , a multi-chip/device integrated plane package is realized, the integration degree is improved, and the package volume is reduced. In other embodiments, a four-base island design or a three-base island design with different sizes and different base island positions from the present embodiment may be derived.
在本实施例中,所述第一基岛11和所述第三基岛13上的功率器件为交替工作在高低压状态,为了防止高压击穿,各基岛之间电气隔离,且基岛与基岛之间设置了安全隔离间距,如图所示所述第一基岛11与所述第二基岛12之间的安全隔离间距a,所述第一基岛11与所述第三基岛13之间的安全隔离间距b,所述第二基岛12与所述第四基岛14之间的安全隔离间距c,以及所述第三基岛13与所述第四基岛14之间的安全隔离间距d;当所述第三基岛13上的引脚作为高压输出引脚时,b、d的值大于a、c的值。安全隔离间距需同时考虑封装时塑封料的流动性以及基岛间的高压安全。In this embodiment, the power devices on the first base island 11 and the third base island 13 work alternately in high and low voltage states. In order to prevent high voltage breakdown, the base islands are electrically isolated, and the base islands are A safety isolation distance is set between the base island and the base island, as shown in the figure, the safety isolation distance a between the first base island 11 and the second base island 12, the first base island 11 and the third base island 12 The safety isolation distance b between the base islands 13 , the safety isolation distance c between the second base island 12 and the fourth base island 14 , and the third base island 13 and the fourth base island 14 The safety isolation distance d between them; when the pins on the third base island 13 are used as high-voltage output pins, the values of b and d are greater than the values of a and c. The safety isolation distance needs to consider both the fluidity of the molding compound during packaging and the safety of high voltage between the base islands.
本发明实现了多芯片/器件集成平面封装,提高了集成度,进而缩小封装体体积;通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的;各基岛之间电气隔离,且基岛与基岛之间设置了安全隔离间距,可以有效防止高压击穿,进而满足封装或可靠性的要求。另外,放置功率器件的基岛可设置若干与基岛直连的引脚,以提高散热。The invention realizes the multi-chip/device integrated plane package, improves the integration degree, and reduces the volume of the package body; by encapsulating the base island to maximize the external leakage, the external leakage heat dissipation surface can be fully contacted with the PCB in the follow-up, so as to achieve the purpose of high heat dissipation; The base islands are electrically isolated, and a safety isolation distance is set between the base islands, which can effectively prevent high-voltage breakdown, thereby meeting the requirements of packaging or reliability. In addition, the base island where the power device is placed can be provided with a number of pins directly connected to the base island to improve heat dissipation.
基于同一发明构思,本发明还提供了一种电源转换模块的QFN封装结构,其采用本发明上述的多基岛引线框架10。Based on the same inventive concept, the present invention also provides a QFN package structure of a power conversion module, which adopts the above-mentioned multi-base island lead frame 10 of the present invention.
请一并参阅图2A-图2C,其中,图2A为本发明电源转换模块的QFN封装结构第一实施例的打线结构示意图,图2B为图2A所示QFN封装结构的仰视图,图2C为图2A所示QFN封装结构的侧视图。其中,为了清楚描述本发明QFN封装结构20的结构,在图2A中,塑封体内部的多基岛引线框架的结构被绘示出。Please refer to FIGS. 2A-2C together, wherein FIG. 2A is a schematic diagram of a wire bonding structure of the first embodiment of the QFN package structure of the power conversion module of the present invention, FIG. 2B is a bottom view of the QFN package structure shown in FIG. 2A , and FIG. 2C It is a side view of the QFN package structure shown in FIG. 2A . Among them, in order to clearly describe the structure of the QFN package structure 20 of the present invention, in FIG. 2A , the structure of the multi-base island lead frame inside the plastic package is shown.
QFN(Quad Flat No-lead Package,方形扁平无引脚封装),是一种无引脚封装,呈正方形或矩形,具有封装体积小、成本低、高散热、高集成、兼容性好等优点,弥补了传统DIP/SOPIPM模块体积大、高成本、兼容性差、散热欠佳等缺点。QFN封装结构贴装占有面积比QFP小,高度比QFP低。由于QFN封装结构内部引脚与焊盘之间的导电路径短,自感系数以及内布线电阻很低,所以它能提供卓越的电性能。此外,它还通过外露的引线框架焊盘(散热面)提供了出色的散热性能,该焊盘具有直接散热通道,用于释放封装内的热量。通常将散热焊盘直接焊接在电路板上,并且PCB中的散热过孔有助于将多余的功耗扩散到铜接地板中,从而吸收多余的热量。本发明QFN封装结构20采用超薄型低成本设计,4基岛框架结构的单颗QFN封装结构20面积(S=9mm*9mm)只有传统DIP23/SOP23面积的23%,封装成本只有传统DIP23/SOP23的60%。QFN (Quad Flat No-lead Package) is a leadless package, which is square or rectangular, and has the advantages of small package size, low cost, high heat dissipation, high integration, and good compatibility. It makes up for the shortcomings of traditional DIP/SOPIPM modules such as large size, high cost, poor compatibility, and poor heat dissipation. The mounting area of the QFN package structure is smaller than that of the QFP, and the height is lower than that of the QFP. Due to the short conductive path between the internal pins and the pads of the QFN package structure, the self-inductance coefficient and the internal wiring resistance are very low, so it can provide excellent electrical performance. In addition, it provides excellent thermal dissipation through exposed leadframe pads (thermal planes) with direct thermal paths for dissipating heat within the package. Thermal pads are usually soldered directly on the board, and thermal vias in the PCB help to spread excess power dissipation into the copper ground plane, which absorbs excess heat. The QFN package structure 20 of the present invention adopts an ultra-thin low-cost design. The area (S=9mm*9mm) of the single QFN package structure 20 of the 4-base island frame structure is only 23% of the area of the traditional DIP23/SOP23, and the packaging cost is only the traditional DIP23/ 60% of SOP23.
在本实施例中,所述电源转换模块为半桥整流或逆变电源转换模块。所述QFN封装结构20包括一多基岛引线框架10、一第一功率器件21、一主控芯片22、一第二功率器件23、一二极管芯片24以及一塑封体(附图中未绘示)。所述多基岛引线框架10的结构、功能以及实现的效果与上述多基岛引线框架10的相同,此处不再赘述。其中,相应散热面部分或全部暴露于所述塑封体,并且所有引脚的端部以及与相应散热面共面的底面部分暴露于所述塑封体。通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的。在其它实施例中,所述电源转换模块也可以为DC-DC电源转换模块,所述QFN封装结构20包括一多基岛引线框架10、一第一功率器件21、一控制所述第一功率器件21的主控芯片22、一二极管芯片24以及一塑封体。相应的,多基岛引线框架10包括所述第一基岛11、所述第二基岛12以及所述第四基岛14。In this embodiment, the power conversion module is a half-bridge rectifier or inverter power conversion module. The QFN package structure 20 includes a multi-base island lead frame 10, a first power device 21, a main control chip 22, a second power device 23, a diode chip 24 and a plastic package (not shown in the drawings). ). The structure, function and effect of the multi-base island lead frame 10 are the same as those of the above-mentioned multi-base island lead frame 10 , which will not be repeated here. Wherein, part or all of the corresponding heat dissipation surface is exposed to the plastic packaging body, and the ends of all the pins and the bottom surface part coplanar with the corresponding heat dissipation surface are exposed to the plastic packaging body. By encapsulating the base island to maximize external leakage, the external leakage heat dissipation surface can be fully contacted with the PCB in the follow-up to achieve the purpose of high heat dissipation. In other embodiments, the power conversion module may also be a DC-DC power conversion module, and the QFN package structure 20 includes a multi-base island lead frame 10 , a first power device 21 , a control device for the first power The device 21 has a main control chip 22 , a diode chip 24 and a plastic package. Correspondingly, the multi-base island lead frame 10 includes the first base island 11 , the second base island 12 and the fourth base island 14 .
在本实施例中,所述第一功率器件21采用导电胶等粘结剂粘贴于所述第一承载面111上,并与所述第一引脚113直接连接,同时通过金属引线25与多个所述第二引脚123中的部分引脚、以及所述第二功率器件23电性连接。所述第一功率器件21为MOS管。所述主控芯片22采用导电胶等粘结剂粘贴于所述第二承载面121上,所述主控芯片22通过金属引线25分别与多个所述第二引脚123中的部分引脚、所述第一功率器件21、所述第二功率器件23以及所述二极管芯片24电性连接。所述主控芯片22即为集成电路芯片(IC),用于控制其它器件,例如控制所述第一功率器件21、所述第二功率器件23以及所述二极管芯片24。所述第二功率器件23采用导电胶等粘结剂粘贴于所述第三承载面131上,并与所述第三引脚133直接连接,同时通过金属引线25与所述第四引脚143电性连接。所述第二功率器件23为MOS管。所述二极管芯片24采用导电胶等粘结剂粘贴于所述第四承载面141上,并与所述第四引脚143直接连接,同时通过金属引线25与多个所述第二引脚123中的一个引脚电性连接;所述第四承载面141上还设有打线区,其通过金属引线25与所述主控芯片22电性连接。In this embodiment, the first power device 21 is pasted on the first bearing surface 111 by an adhesive such as conductive glue, and is directly connected to the first pin 113 , and is connected to multiple Some of the second pins 123 are electrically connected to the second power device 23 . The first power device 21 is a MOS transistor. The main control chip 22 is pasted on the second carrying surface 121 by adhesives such as conductive glue, and the main control chip 22 is connected to some of the plurality of second pins 123 through metal leads 25 respectively. , the first power device 21 , the second power device 23 and the diode chip 24 are electrically connected. The main control chip 22 is an integrated circuit chip (IC) for controlling other devices, such as controlling the first power device 21 , the second power device 23 and the diode chip 24 . The second power device 23 is pasted on the third bearing surface 131 with an adhesive such as conductive glue, and is directly connected to the third pin 133, and is connected to the fourth pin 143 through the metal lead 25 at the same time. Electrical connection. The second power device 23 is a MOS transistor. The diode chip 24 is pasted on the fourth bearing surface 141 by using an adhesive such as conductive glue, and is directly connected to the fourth pins 143 , and is connected to a plurality of the second pins 123 through the metal leads 25 at the same time. One of the pins is electrically connected; the fourth bearing surface 141 is also provided with a wire bonding area, which is electrically connected to the main control chip 22 through the metal leads 25 .
在后续使用的一种状态中,所述第一引脚113的工作电压低于所述第二引脚123的工作电压,所述第二引脚123的工作电压低于所述第三引脚133的工作电压。所述第四引脚143的工作电压范围基本与所述第二引脚123的工作电压范围相同。即,所述第一引脚113作为低压(电压小于或等于一预设电压,例如0V)引脚,所述第二引脚123接工作电压或高/低压输入信号(一般为几十伏),相应的所述第三引脚133为高压(电压大于或等于一预设电压,例如500V)引脚。低压引脚及高压引脚分别设置在基岛的两侧,并电气隔离,避免引脚之间由于高低电压差异比较大,而引起的相互之间击穿的情况发生,进而满足封装或可靠性的要求。In a state of subsequent use, the working voltage of the first pin 113 is lower than the working voltage of the second pin 123 , and the working voltage of the second pin 123 is lower than that of the third pin 133 working voltage. The working voltage range of the fourth pin 143 is basically the same as that of the second pin 123 . That is, the first pin 113 is used as a low voltage (voltage less than or equal to a preset voltage, such as 0V) pin, and the second pin 123 is connected to a working voltage or a high/low voltage input signal (usually several tens of volts) , the corresponding third pin 133 is a high-voltage (voltage greater than or equal to a predetermined voltage, such as 500V) pin. The low-voltage pins and the high-voltage pins are arranged on both sides of the base island respectively, and are electrically isolated to avoid the breakdown between the pins due to the large difference between the high and low voltages, so as to meet the packaging or reliability requirements. requirements.
在本实施例中,为了满足高散热性要求,同时防止高压击穿,除封装结构内部基岛与基岛之间设置了安全隔离间距外,封装外漏散热面之间、引脚与引脚之间、分离式引脚与散热面之间均进行安全间距设计。如图2B中,第一散热面112与第二散热面122之间具有预设隔离间距k1,不同边上的第二引脚123与第二散热面122之间具有预设隔离间距k以及k2,作为高压引脚的第三引脚133与第二散热面122之间具有预设隔离间距k3,第一散热面112与第三散热面132之间具有预设隔离间距k4。由于高压引脚与控制芯片所在散热面之间的压差较大,一般可达到几百伏压差,因此k3的值可以设置的最大。In this embodiment, in order to meet the requirements of high heat dissipation and prevent high-voltage breakdown at the same time, in addition to setting a safety isolation distance between the base island and the base island inside the package structure, the outer leakage and heat dissipation surfaces of the package, pins and pins Safety spacing design is carried out between the separated pins and the heat dissipation surface. As shown in FIG. 2B , there is a preset isolation distance k1 between the first heat dissipation surface 112 and the second heat dissipation surface 122 , and preset isolation distances k and k2 between the second pins 123 on different sides and the second heat dissipation surface 122 , there is a preset isolation distance k3 between the third pin 133 serving as the high voltage pin and the second heat dissipation surface 122 , and a preset isolation distance k4 between the first heat dissipation surface 112 and the third heat dissipation surface 132 . Because the voltage difference between the high-voltage pin and the heat dissipation surface where the control chip is located is large, which can generally reach several hundred volts, the value of k3 can be set to the maximum.
本发明QFN封装结构,实现了多芯片/器件集成平面封装,提高了集成度,缩小了封装体体积、降低了封装成本;通过将基岛进行封装最大外漏,外漏散热面可以在后续与PCB充分接触,达到高散热目的;封装结构内部各基岛之间电气隔离,且基岛与基岛之间设置了安全隔离间距,封装结构外漏散热面之间、引脚与引脚之间、分离式引脚与散热面之间均进行安全间距设计,可以有效防止高压击穿,进而满足封装或可靠性的要求。The QFN packaging structure of the present invention realizes multi-chip/device integrated plane packaging, improves the integration degree, reduces the volume of the package body, and reduces the packaging cost; by encapsulating the base island to maximize the external leakage, the external leakage heat dissipation surface can be used in the follow-up with The PCB is fully contacted to achieve the purpose of high heat dissipation; the base islands inside the package structure are electrically isolated, and a safety isolation distance is set between the base islands and the base islands, and the package structure leaks between the heat dissipation surfaces and between the pins and the pins. , A safe spacing is designed between the separated pins and the heat dissipation surface, which can effectively prevent high-voltage breakdown, thereby meeting the requirements of packaging or reliability.
请参阅图3,本发明电源转换模块的QFN封装结构第二实施例的打线结构示意图。与图2A所示实施例的不同之处在于,在本实施例中,所述第一功率器件21包括采用金属引线25电性连接的第一绝缘栅双极型晶体管(IGBT)311以及第一快恢复二极管(FRD)312;所述第二功率器件23包括采用金属引线25电性连接的第二绝缘栅双极型晶体管(IGBT)331以及第二快恢复二极管(FRD)332。所述QFN封装结构的其它结构、功能可参考上述QFN封装结构,此处不再赘述。Please refer to FIG. 3 , which is a schematic diagram of the wire bonding structure of the second embodiment of the QFN package structure of the power conversion module of the present invention. The difference from the embodiment shown in FIG. 2A is that in this embodiment, the first power device 21 includes a first insulated gate bipolar transistor (IGBT) 311 electrically connected by a metal wire 25 and a first Fast recovery diode (FRD) 312 ; the second power device 23 includes a second insulated gate bipolar transistor (IGBT) 331 and a second fast recovery diode (FRD) 332 electrically connected by metal leads 25 . For other structures and functions of the QFN package structure, reference may be made to the above-mentioned QFN package structure, which will not be repeated here.
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as It is the protection scope of the present invention.
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| CN114284230A (en) * | 2021-12-24 | 2022-04-05 | 天水华天科技股份有限公司 | Packaging piece for sealing base island isolation frame and substrate chip and preparation method |
| CN114420664A (en) * | 2022-01-18 | 2022-04-29 | 广东气派科技有限公司 | Packaging structure of multi-base-island high-power module QFN |
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