CN104124205A - RDL preparation method - Google Patents
RDL preparation method Download PDFInfo
- Publication number
- CN104124205A CN104124205A CN201410345835.0A CN201410345835A CN104124205A CN 104124205 A CN104124205 A CN 104124205A CN 201410345835 A CN201410345835 A CN 201410345835A CN 104124205 A CN104124205 A CN 104124205A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon
- preparation
- keyset
- rdl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses an RDL preparation method. The RDL preparation method comprises the steps of adopting a photo-etching technology to perform exposure on a photo-etching adhesive layer on a substrate so as to form a residual photo-etching adhesive layer graph, wherein undercut is produced at the bottom of the residual photo-etching adhesive layer graph; performing etching modification on the residual photo-etching adhesive layer graph to remove the undercut on the residual photo-etching adhesive layer graph so as to form a redistribution layer graph and a photoresist substrate graph; plating metal to form redistribution layer lines and removing the photoresist substrate graph. In the RDL preparation method, the undercut is removed through the etching modification on the photo-etching adhesive layer graph, and the metal is plated to form an RDL. The RDL preparation method has the advantages that the process cot is reduced, the device performance is improved, and good narrow-line-distance wide-line-distance RDL are prepared.
Description
Technical field
The present invention relates to TSV keyset manufacture craft, relate in particular to a kind of preparation method of RDL wiring layer.
Background technology
Along with popularizing fast of the mobile intelligent terminals such as smart mobile phone and panel computer, following global Mobile data flow estimates the 0.6EB from 2011 (Exabyte) to increase sharply to the 10.8EB of 2016,17 times more than of data volume popularizations.In order to meet more and more higher Mobile data flow and the demand of transmission speed to device, further improving performance when reducing chip volume, the complexity of IC encapsulation is also in continuous upgrading, silicon through hole (TSV) technology of take is arisen at the historic moment as the various chip stack package techniques on basis, comprises 3D IC, 3D WLCSP, 2.5D keyset technique etc.Semi-additive process and Damascus technics are exactly two kinds of conventional at present methods of preparing 2.5D keyset RDL layer.
Conventional semi-additive process is to complete TSV etching when TSV keyset, after the making technologies such as TSV filling, by sputtering sedimentation Ti or Ti/W barrier layer and Cu Seed Layer.Then be coated with photoresist, by exposure imaging, form the figure needing.Then electroplating deposition metal Cu, forms RDL layer.Adopt the defect of semi-additive process manufacture RDL layer to be, when live width line-spacing diminishes, undercutting is easily caused in photoresist bottom, thereby it is poor to make to electroplate figure, even may cause component failure.Conventional copper RDL layer manufacturing method thereof is a kind of manufacturing process of standard on encapsulation circle.And copper Damascus (damascene) technique is to be widely used in ICChang Qian road technique.Damascus technique is the figure film that first etching metal wire is used on dielectric layer, and then fills metal.Its topmost feature is the etching that does not need to carry out metal level.When the material of plain conductor converts the lower copper of resistivity to by aluminium, due to the dry ecthing of copper difficulty comparatively, so Damascus technique is just very important concerning copper wiring.The defect of this technique is, for Advanced Packaging, the preparation pitch layer process cost that reroutes is higher.
Summary of the invention
The invention provides a kind of preparation method of RDL wiring layer, by photoetching and etching, modify the undercutting of removing remaining photoresist layer figure bottom, to form the layer pattern that reroutes, re-plating copper, reach the object that reduces process costs, and reach the effect of preparing the wide line-spacing RDL of good fine rule wiring layer and improving device performance.
The preparation method of a kind of RDL wiring layer provided by the invention, comprising:
Adopt photoetching technique, the photoresist layer on substrate is exposed, to form remaining photoresist layer figure, wherein, there is undercutting in the bottom of described remaining photoresist layer figure;
Described remaining photoresist layer figure is carried out to etching modification, remove the undercutting on described remaining photoresist layer figure, to form reroute layer pattern and photoresist substrate figure;
Plated metal to be to form the layer line bar that reroutes, and removes described photoresist substrate figure.
Preferably, described substrate is comprised of through-silicon-via keyset and the Seed Layer that deposits on described through-silicon-via keyset.
Preferably, described Seed Layer consists of the Ti and the Cu that are deposited on successively on described through-silicon-via keyset.
Preferably, the preparation process of described through-silicon-via keyset, comprising:
A plurality of silicon through holes of etching on keyset, to form silicon through hole keyset;
At the inwall of described a plurality of silicon through holes and the surface of described silicon through hole keyset, form passivation layer;
In having a plurality of silicon through holes of passivation layer, this fills metal, to form through-silicon-via keyset.
Preferably, at this, having the metal of filling in a plurality of silicon through holes of passivation layer is copper.
Preferably, described photoresist layer is negative photoresist layer.
Preferably, the thickness of the described photoresist layer thickness of layer line bar that reroutes described in being more than or equal to.
Preferably, adopt electrochemistry galvanoplastic plated metal.
Preferably, adopt wet processing to remove described photoresist substrate figure.
Preferably, described plated metal is copper.
The preparation method of a kind of RDL wiring layer provided by the invention, adopt photoetching technique to expose to the negative photoresist layer on substrate, on substrate, after exposure, formed remaining photoresist layer figure, there is undercutting in the bottom of this remaining photoresist layer figure, by etching modification process, remaining photoresist layer figure is carried out to etching modification again, removed undercutting, reroute layer pattern and the photoresist substrate figure that meet the requirement of RDL wiring layer have been obtained, adopt again electrochemistry galvanoplastic plated metal and wet processing to remove photoresist substrate figure, thereby obtained RDL wiring layer.The present invention compares with prior art Damascus technics, has the advantage that process costs is low, and the present invention compares with prior art semi-additive process, has the excellent performance and the advantage that produces the wide line-spacing RDL of fine rule wiring layer of device.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, by the accompanying drawing of required use in embodiment or description of the Prior Art being done to one, introduce simply below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the preparation method's of a kind of RDL wiring layer of providing of the embodiment of the present invention schematic flow sheet;
Fig. 2 is the schematic diagram of the TSV keyset that provides of the embodiment of the present invention;
Fig. 3 is the schematic diagram of the substrate that provides of the embodiment of the present invention;
Fig. 4 is the schematic diagram of the formation photoresist layer 14 that provides of the embodiment of the present invention;
Fig. 5 is the schematic diagram of the photoetching RDL wiring layer that provides of the embodiment of the present invention;
Fig. 6 is the schematic diagram of the RDL wiring layer that provides of the embodiment of the present invention;
Fig. 7 is the schematic diagram of the undercutting on the removal remaining photoresist layer figure 16 that provides of the embodiment of the present invention;
Fig. 8 is the schematic diagram of the electro-coppering RDL wiring layer 18 that provides of the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to the accompanying drawing in the embodiment of the present invention, by execution mode, technical scheme of the present invention is described clearly and completely, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
With reference to figure 1, the preparation method's of a kind of RDL wiring layer providing for the embodiment of the present invention schematic flow sheet, the technical scheme of the present embodiment is applicable to the semiconductor chip fabrication process situation that integrated level is high.Chip can be three dimensional integrated circuits chip.Before preparation, can first prepare the keyset with through-silicon-via, and form successively one deck Seed Layer and photoresist layer thereon, the layer pattern so that photoetching-formation is rerouted.The method comprises the steps:
Step 110, employing photoetching technique, expose to the photoresist layer on substrate, and to form remaining photoresist layer figure, wherein, undercutting appears in the bottom of described remaining photoresist layer figure;
Step 120, described remaining photoresist layer figure is carried out to etching modification, remove the undercutting on described remaining photoresist layer figure, to form reroute layer pattern and photoresist substrate figure;
Step 130, plated metal to be to form the layer line bar that reroutes, and remove described photoresist substrate figure.
With reference to figure 2, the schematic diagram of the TSV keyset providing for the embodiment of the present invention.Preparation process at this preferred described through-silicon-via (Through Silicon Via, TSV) keyset, comprising:
First, a plurality of silicon through holes 12 of etching on keyset 11, to form silicon through hole keyset;
In the present embodiment, on keyset 11, the reason of a plurality of silicon through holes 12 of etching is: silicon through hole technology is a kind of technical scheme that in three dimensional integrated circuits, stacked chips is realized interconnection, not only can effectively realize the heap superimposition interconnection of semiconductor chip chips, also make that chip is maximum in the stacking density of three-dimensional, the interconnection line between chip is the shortest, overall dimension is minimum.
A plurality of silicon through holes 12 of this step etching on keyset 11, can effectively realize chip laminate, and can produce that structure is more complicated, performance is more powerful, have more cost-efficient chip, also reduced chip package size simultaneously, reduced transmission delay, accelerated the data stream transmitting speed of chip chamber and reduce chip power-consumption.
Secondly, at the inwall of described a plurality of silicon through holes 12 and the surface of described silicon through hole keyset, form passivation layer;
Passivation layer in semiconductor device is usually used as protective layer, insulating barrier and separator.In the present embodiment, at the inwall of described a plurality of silicon through holes 12 and the surface of described silicon through hole keyset, form passivation layer, said passivation layer can be silicon dioxide layer, the effect of passivation layer is: when metal material being filled in silicon through hole 12 and/or being deposited on silicon through hole keyset surface, metal material is used as connecting line and layer (the Redistribution Layer that reroute of a plurality of chip chambers of semiconductor device, RDL), to conduct electricity, yet, when if metal material directly contacts the inwall of silicon through hole 12 or silicon through hole keyset surperficial, metal material is easy to be diffused in the silicon base of keyset, thereby have a strong impact on the semiconducting behavior of silicon base, cause device performance degeneration, therefore the object that forms one deck passivation layer between the inwall of silicon through hole 12 and metal material is to prevent the diffusion of metal material, thereby guarantee the performance of device.On the surface of silicon through hole keyset also for this purpose.
Finally, in having a plurality of silicon through holes 12 of passivation layer, this fills metal, to form through-silicon-via keyset;
In the present embodiment, preferably, at this, having the metal of filling in a plurality of silicon through holes 12 of passivation layer is copper, its reason is: on the one hand, and in integrated circuit (Integrated Circuit, IC) industry, traditional RDL wiring layer is generally aluminium, along with reducing of semiconductor chip process, the high resistance shortcoming of aluminium embodies gradually, makes the electric conductivity variation of device; On the other hand, if adopt silver as RDL wiring layer, the low-resistivity advantage of silver can make device have excellent electric conductivity, yet defect is high cost.In sum, at this, adopt copper as RDL wiring layer, it is advantageous that, cost lower than silver, resistivity is well below aluminium and be slightly higher than silver, electric conductivity is good, therefore can substitution of Al or silver as the RDL wiring layer of high-integrated semiconductor chip.According to after above-mentioned three steps, just formed TSV keyset.
With reference to figure 3, the schematic diagram of the substrate providing for the embodiment of the present invention.
At this preferred described substrate, by through-silicon-via keyset and the Seed Layer 13 that deposits on described through-silicon-via keyset, formed.
Preferably, described Seed Layer 13 consists of the Ti and the Cu that are deposited on successively on described through-silicon-via keyset.
The reason that deposits one deck Seed Layer 13 on above-mentioned TSV keyset is: in the present invention, adopt the RDL wiring layer of electrochemistry galvanoplastic fabricate devices, electroplating the key forming is to make metal deposit by surperficial metal level generation current.And passivation layer is nonconducting, so can not carry out the plating of RDL wiring layer, therefore need to form again layer of metal layer in nonconducting passivation layer surface, using as Seed Layer 13, be convenient to prepare RDL wiring layer.
Described Seed Layer 13 is by being deposited on successively the reason that Ti on described through-silicon-via keyset and Cu form: after in the present invention, extended meeting adopts copper as RDL wiring layer, the effect of preparation barrier layer Ti is that Ti layer can be used as diffusion impervious layer and stops copper to the silicon base diffusion of TSV keyset, and the adhesion that increases Cu layer, Cu is plating seed layer, is convenient to electrochemistry electro-coppering RDL wiring layer.Therefore Seed Layer 13 is the lamination of Ti and Cu.
With reference to figure 4, the schematic diagram of the formation photoresist layer 14 providing for the embodiment of the present invention.
At this preferably, described photoresist layer 14 is negative photoresist layer, the thickness of the layer line bar that reroutes described in the thickness of described photoresist layer 14 is more than or equal to.
Photoresist is before and after a kind of sensitization, the solubility meeting organic compound that great changes will take place in specific developer solution.Photoresist comprises positive photoresist and negative photoresist.At this, preferably form negative photoresist layer, the unexposed portion of negative photoresist is dissolved in developer solution, and exposed portion solidifies, and is insoluble to developer solution, and the pattern that after developing, negative photoresist layer retains is contrary with mask plate light-shielding pattern.
When the thickness of photoresist layer 14 is more than or equal to the thickness of the layer line bar that reroutes, be convenient to counterweight wiring layer figure and electroplate the RDL wiring layer thickness that reaches required, wherein, described in the layer line bar that reroutes be RDL wiring layer.
Operation for step 110, adopt photoetching technique, photoresist layer 14 on substrate is exposed, developed, to form remaining photoresist layer figure 16, wherein, there is undercutting in the bottom of described remaining photoresist layer figure 16, with reference to figure 5, the schematic diagram of the photoetching RDL wiring layer providing for the embodiment of the present invention, with reference to figure 6, the schematic diagram of the RDL wiring layer providing for the embodiment of the present invention.
As shown in Figure 5, because the photoresist layer 14 in the present invention is negative photoresist, it is identical with preformed copper RDL wiring layer figure on substrate that the mask plate 15 shading graph regions that provide in this figure should be designed to, and the mask plate 15 shading graph regions that adopt in the present invention are of a size of the integral multiple of copper RDL wiring layer size, in when exposure, dwindle mask graph accurately to form copper RDL wiring layer on substrate, and mask plate 15 not shading graph be exposure area.
According to the copper RDL wiring layer of device, mask plate 15 and photoresist layer 14 are accurately located and retain space, to photoresist layer 14 selectivity exposures.The contactless exposure of mask plate 15 and photoresist layer 14, not only can stop the pollution of photoresist to mask plate 15, and the mask plate 15 that can also effectively avoid mask plate 15 and photoresist layer 14 directly to contact causing damages, and has protected the complete of RDL wiring layer.
As shown in Figure 6, well known photolithography glue-line 14 is negative photoresist layer, mask plate 15 shading graph are copper RDL wiring layer figure, by photoetching technique exposure imaging, on substrate, formed remaining photoresist layer figure 16, wherein, there is undercutting (Undercut) with the position of substrate contact in the remaining photoresist layer figure after photoetching 16.
Operation for step 120, described remaining photoresist layer figure 16 is carried out to etching modification, remove the undercutting on described remaining photoresist layer figure 16, to form reroute layer pattern and photoresist substrate figure 17, with reference to figure 7, the schematic diagram of the undercutting of removal remaining photoresist layer figure 16 bottoms that provide for the embodiment of the present invention.
Known according to Fig. 5 and Fig. 6, after photoresist layer 14 is exposed, developed, there is undercutting in residue photoetching offset plate figure 16.Undercutting structure may cause the copper RDL wiring layer of subsequent deposition poor, also may cause reliability of technology to reduce, to such an extent as to cause component failure.Therefore in the present invention, by etching technics, modify the sidewall of the remaining photoresist layer figure 16 after photoetching, remove undercutting structure, make it to form the photoresist substrate figure 17 that meets the requirement of deposit RDL wiring layer, avoided the inefficacy of device and reliability to reduce.Etching is modified the sidewall of (Etch trim) remaining photoresist layer figure 16, spacing between photoresist substrate figure 17 after modifying is broadened, and the width of photoresist substrate figure 17 self reduces, so should fully take into account this point during mask design, to obtain the wide line-spacing RDL of satisfactory fine rule wiring layer.
For the operation of step 130, plated metal to be to form the layer line bar that reroutes, and removes described photoresist substrate figure 17, with reference to figure 8, and the schematic diagram of the electro-coppering RDL wiring layer 18 providing for the embodiment of the present invention.
At this preferably, adopt electrochemistry galvanoplastic plated metal.Preferably, adopt wet processing to remove described photoresist substrate figure 17.Preferably, described plated metal is copper.
Shown in Fig. 1-Fig. 7, on substrate, formed the layer pattern that reroutes.Photoresist substrate figure 17 according to the Ti/Cu Seed Layer 13 of deposition and after modifying, adopt electrochemistry galvanoplastic to electroplate the layer line bar that reroutes, copper RDL wiring layer 18 namely, detailed process is: power supply is added between Ti/Cu Seed Layer 13 and the silicon base of TSV keyset, Ti/Cu Seed Layer 13 is as anode, the silicon base of TSV keyset is as negative electrode, apply after voltage, as the copper in the Ti/Cu Seed Layer 13 of anode, react and change into copper ion and electronics, silicon base as negative electrode also reacts simultaneously, near the copper ion on Seed Layer 13 surfaces silicon base is combined formation and is plated in the copper on Seed Layer 13 surfaces with electronics.Finally, complete the plating of copper RDL wiring layer 18, adopt subsequently photoetching technique to remove photoresist substrate figure 17, can form the wide line-spacing RDL of good fine rule wiring layer 18.
From the above mentioned, according to electrochemical process, by electroplating technology, formed copper RDL wiring layer 18, by wet processing, remove photoresist substrate figure 17, thereby on substrate, prepare complete copper RDL wiring layer 18, completed the reroute process of layer pattern of fabricate devices.
The preparation method of a kind of RDL wiring layer 18 that the embodiment of the present invention provides, the copper layer pattern that reroutes is designed to the not lightproof area of mask plate 15, adopt again photoetching technique to expose to the negative photoresist layer on substrate, develop, on substrate, formed remaining photoresist layer figure 16, there is undercutting in the bottom of this remaining photoresist layer figure 16, by etching modification process, remaining photoresist layer figure 16 is carried out to etching modification again, removed undercutting, obtained and met the photoresist substrate figure 17 that RDL wiring layer 18 requires, adopt again electrochemistry electro-coppering and remove photoresist substrate figure 17, thereby obtained the wide line-spacing copper of good fine rule RDL wiring layer 18.The present invention compares with prior art Damascus technics, has the advantage that process costs is low, and the present invention compares with prior art semi-additive process, has the excellent performance and the advantage of manufacturing the good wide line-spacing copper of fine rule RDL wiring layer 18 of device.
Above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious variations, readjust and substitute and can not depart from protection scope of the present invention.Therefore, although the present invention is described in further detail by above embodiment, the present invention is not limited only to above embodiment, in the situation that not departing from the present invention's design, can also comprise more other equivalent embodiment, and scope of the present invention is determined by appended claim scope.
Claims (10)
1. a preparation method for RDL wiring layer, is characterized in that, comprising:
Adopt photoetching technique, the photoresist layer on substrate is exposed, to form remaining photoresist layer figure, wherein, there is undercutting in the bottom of described remaining photoresist layer figure;
Described remaining photoresist layer figure is carried out to etching modification, remove the undercutting on described remaining photoresist layer figure, to form reroute layer pattern and photoresist substrate figure;
Plated metal to be to form the layer line bar that reroutes, and removes described photoresist substrate figure.
2. preparation method according to claim 1, is characterized in that, described substrate is comprised of through-silicon-via keyset and the Seed Layer that deposits on described through-silicon-via keyset.
3. preparation method according to claim 2, is characterized in that, described Seed Layer consists of the Ti and the Cu that are deposited on successively on described through-silicon-via keyset.
4. preparation method according to claim 2, is characterized in that, the preparation process of described through-silicon-via keyset, comprising:
A plurality of silicon through holes of etching on keyset, to form silicon through hole keyset;
At the inwall of described a plurality of silicon through holes and the surface of described silicon through hole keyset, form passivation layer;
In having a plurality of silicon through holes of passivation layer, this fills metal, to form through-silicon-via keyset.
5. preparation method according to claim 4, is characterized in that, at this, having the metal of filling in a plurality of silicon through holes of passivation layer is copper.
6. preparation method according to claim 1, is characterized in that, described photoresist layer is negative photoresist layer.
7. preparation method according to claim 6, is characterized in that, the thickness of the layer line bar that reroutes described in the thickness of described photoresist layer is more than or equal to.
8. preparation method according to claim 1, is characterized in that, adopts electrochemistry galvanoplastic plated metal.
9. preparation method according to claim 1, is characterized in that, adopts wet processing to remove described photoresist substrate figure.
10. preparation method according to claim 1, is characterized in that, described plated metal is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410345835.0A CN104124205B (en) | 2014-07-18 | 2014-07-18 | A kind of preparation method of RDL wiring layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410345835.0A CN104124205B (en) | 2014-07-18 | 2014-07-18 | A kind of preparation method of RDL wiring layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104124205A true CN104124205A (en) | 2014-10-29 |
| CN104124205B CN104124205B (en) | 2018-03-16 |
Family
ID=51769571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410345835.0A Active CN104124205B (en) | 2014-07-18 | 2014-07-18 | A kind of preparation method of RDL wiring layers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124205B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105550432A (en) * | 2015-12-11 | 2016-05-04 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power network layout method thereof |
| CN110007210A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of method for rapidly testing of system in package modular structure |
| CN112289688A (en) * | 2019-07-22 | 2021-01-29 | 中芯长电半导体（江阴）有限公司 | Preparation method of rewiring layer |
| CN117116888A (en) * | 2023-01-16 | 2023-11-24 | 荣耀终端有限公司 | Semiconductor packaging structure, preparation method thereof and electronic equipment |
| CN117613001A (en) * | 2023-11-30 | 2024-02-27 | 上海玻芯成微电子科技有限公司 | Chip manufacturing method and chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1147147A (en) * | 1995-06-26 | 1997-04-09 | 现代电子产业株式会社 | Method for forming fine patterns of semiconductor device |
| CN1797198A (en) * | 2004-12-22 | 2006-07-05 | 联华电子股份有限公司 | Method for forming pattern of photoresist and finishing technique |
| CN1885524A (en) * | 2005-06-24 | 2006-12-27 | 米辑电子股份有限公司 | Circuitry component and method for forming the same |
| CN101110377A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | Method for forming soldering projection |
| CN101937175A (en) * | 2009-07-03 | 2011-01-05 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| CN103454856A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Photosenstive material and method of lithography |
| CN103456685A (en) * | 2013-09-13 | 2013-12-18 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for TSV and first layer re-wiring layer needless of using CMP |
-
2014
- 2014-07-18 CN CN201410345835.0A patent/CN104124205B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1147147A (en) * | 1995-06-26 | 1997-04-09 | 现代电子产业株式会社 | Method for forming fine patterns of semiconductor device |
| CN1797198A (en) * | 2004-12-22 | 2006-07-05 | 联华电子股份有限公司 | Method for forming pattern of photoresist and finishing technique |
| CN1885524A (en) * | 2005-06-24 | 2006-12-27 | 米辑电子股份有限公司 | Circuitry component and method for forming the same |
| CN101110377A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | Method for forming soldering projection |
| CN101937175A (en) * | 2009-07-03 | 2011-01-05 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| CN103454856A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Photosenstive material and method of lithography |
| CN103456685A (en) * | 2013-09-13 | 2013-12-18 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for TSV and first layer re-wiring layer needless of using CMP |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105550432A (en) * | 2015-12-11 | 2016-05-04 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power network layout method thereof |
| CN110007210A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of method for rapidly testing of system in package modular structure |
| CN112289688A (en) * | 2019-07-22 | 2021-01-29 | 中芯长电半导体（江阴）有限公司 | Preparation method of rewiring layer |
| CN112289688B (en) * | 2019-07-22 | 2024-05-07 | 盛合晶微半导体(江阴)有限公司 | Preparation method of rewiring layer |
| CN117116888A (en) * | 2023-01-16 | 2023-11-24 | 荣耀终端有限公司 | Semiconductor packaging structure, preparation method thereof and electronic equipment |
| CN117613001A (en) * | 2023-11-30 | 2024-02-27 | 上海玻芯成微电子科技有限公司 | Chip manufacturing method and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104124205B (en) | 2018-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110121766B (en) | Method for forming lead in hybrid bonding semiconductor device | |
| CN102332435B (en) | Electronic component and manufacturing method of same | |
| CN104124205A (en) | RDL preparation method | |
| US9257336B2 (en) | Bottom-up plating of through-substrate vias | |
| CN108074911B (en) | Jumping hole structure | |
| US9240373B2 (en) | Semiconductor devices with close-packed via structures having in-plane routing and method of making same | |
| CN102254871A (en) | Semiconductor eevice and manufacturing method thereof | |
| CN104037162A (en) | Wafer-level package mitigated undercut | |
| CN102034741B (en) | Method of manufacturing a semiconductor component and structure | |
| EP2713389A2 (en) | System and method of novel MX to MX-2 | |
| US7553743B2 (en) | Wafer bonding method of system in package | |
| CN104167353A (en) | Method for processing surface of bonding substrate | |
| US11069620B2 (en) | Die interconnect substrate, an electrical device and a method for forming a die interconnect substrate | |
| TWI543263B (en) | Semiconductor device and manufacturing method thereof | |
| CN102903673A (en) | Method for manufacturing wafer-level through silicon via (TSV) | |
| US20140084481A1 (en) | System and method of novel encapsulated multi metal branch foot structures for advanced back end of line | |
| JP5942867B2 (en) | Manufacturing method of semiconductor device | |
| US10497610B2 (en) | Dual photoresist approach to lithographic patterning for pitch reduction | |
| CN103295915B (en) | The manufacture method of TSV keyset and TSV keyset | |
| CN102800621B (en) | Method for forming embolism structure and semiconductor device | |
| KR100884987B1 (en) | Method for forming cu metal line of semiconductor device | |
| KR100866121B1 (en) | Method for forming metal line of semiconductor device | |
| KR100731082B1 (en) | Method for fabricating semiconductor device | |
| CN113363202A (en) | Semiconductor structure and forming method thereof | |
| CN114121779A (en) | Method for preparing dual damascene structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |