CN107622953B - Method for manufacturing package-on-package structure - Google Patents
Method for manufacturing package-on-package structure Download PDFInfo
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- CN107622953B CN107622953B CN201610603368.6A CN201610603368A CN107622953B CN 107622953 B CN107622953 B CN 107622953B CN 201610603368 A CN201610603368 A CN 201610603368A CN 107622953 B CN107622953 B CN 107622953B
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- package substrate
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 110
- 238000004806 packaging method and process Methods 0.000 claims abstract description 35
- 238000005538 encapsulation Methods 0.000 claims description 7
- 239000005022 packaging material Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 141
- 229910000679 solder Inorganic materials 0.000 description 23
- 239000004065 semiconductor Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 13
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 7
- 239000012792 core layer Substances 0.000 description 7
- 239000008393 encapsulating agent Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000004693 Polybenzimidazole Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000003973 paint Substances 0.000 description 4
- 229920002480 polybenzimidazole Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920002312 polyamide-imide Polymers 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A method for fabricating a package-on-package structure includes providing a first coreless package substrate, wherein one side of the first coreless package substrate has a plurality of first conductive elements and the other side of the first coreless package substrate is coupled to a carrier; then, the first coreless layer type packaging substrate is combined to a second coreless layer type packaging substrate through a first conductive element of the first coreless layer type packaging substrate, and at least one electronic element is arranged on the second coreless layer type packaging substrate; then, a package layer is formed between the first coreless package substrate and the second coreless package substrate, and the carrier is removed. By stacking two coreless packaging substrates, the thickness of the packaging stack structure is reduced.
Description
Technical Field
The present invention relates to a semiconductor packaging process, and more particularly, to a method for fabricating a package-on-package structure.
background
With the development of Semiconductor packaging technology, Semiconductor devices (Semiconductor devices) have been developed with different Package types, and in order to improve electrical performance and save Package space, Package types have been developed in which a plurality of Package structures are stacked to form a Package On Package (POP) structure, which can perform heterogeneous integration of System In Package (SiP) and can be used to integrate electronic devices with different functions, such as: the memory, the CPU, the graphic processor, the image application processor, etc. can achieve the integration of the system by the stacking design, and is suitable for various light, thin, short and small electronic products.
fig. 1 is a schematic cross-sectional view of a conventional package stack 1. As shown in fig. 1, the package stack structure 1 includes a first semiconductor device 10, a first package substrate 11, a second package substrate 12, a plurality of solder balls 13, a second semiconductor device 14, and an encapsulant 15. The first package substrate 11 has a core layer 110 and a plurality of circuit layers 111, and the second package substrate 12 has a core layer 120 and a plurality of circuit layers 121. The first semiconductor device 10 is disposed on the first package substrate 11 in a flip-chip manner, and the second semiconductor device 14 is also disposed on the second package substrate 12 in a flip-chip manner. The solder balls 13 are used to connect and electrically couple the first package substrate 11 and the second package substrate 12. The encapsulant 15 encapsulates the solder balls 13 and the first semiconductor device 10. Optionally, an underfill 16 is formed between the first semiconductor device 10 and the first package substrate 11.
however, in the conventional package stack structure 1, the first package substrate 11 and the second package substrate 12 both have the core layer 110,120, which results in high manufacturing cost, and the thickness H of the package stack structure 1 is about 620 μm, which is not suitable for the current demand of light, thin, and small products.
Therefore, how to overcome the problems in the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for fabricating a package stack structure, which reduces the thickness of the package stack structure by stacking two coreless package substrates.
The manufacturing method of the packaging stack structure comprises the following steps: providing a first coreless laminated packaging substrate and a second coreless laminated packaging substrate, wherein one side of the second coreless laminated packaging substrate is provided with at least one electronic element; bonding the first coreless laminated packaging substrate to one side of the second coreless laminated packaging substrate, which is provided with the electronic element, by a plurality of first conductive elements; and forming a packaging layer between the first coreless packaging substrate and the second coreless packaging substrate so that the packaging layer covers the first conductive elements and the electronic element.
In the above method for fabricating a package stack structure, the first coreless package substrate further includes a first dielectric layer and a first circuit layer embedded in the first dielectric layer and electrically connected to the first conductive elements. In addition, the first coreless packaging substrate also comprises a plurality of first conductive columns which are embedded in the first dielectric layer and formed on the first circuit layer, so that the first conductive elements are electrically connected with the first circuit layer through the first conductive columns.
In the above method for fabricating a package on package structure, a carrier is bonded to another side of the first coreless substrate, for example, the first coreless substrate is bonded to the carrier by a first insulating layer. The method also includes removing the carrier after forming the encapsulation layer. After the carrier plate is removed, a plurality of first openings are formed on the first insulating layer.
In the above method for fabricating the package stack structure, a primer is formed between the second coreless package substrate and the electronic device.
In the above method for fabricating the package stack structure, the second coreless package substrate includes a circuit build-up structure, such that the first conductive element and the electronic element are electrically connected to the circuit build-up structure. For example, the second coreless package substrate further includes a plurality of second conductive elements formed on the build-up structure and electrically connected to the build-up structure, such that the second conductive elements are combined with the first conductive elements and the electronic element, and the package layer further encapsulates the second conductive elements. Or, the second coreless laminated package substrate further comprises a second insulating layer formed on the line build-up structure, so that before the first and second coreless laminated package substrates are combined, the second coreless laminated package substrate is combined with another carrier plate by the second insulating layer, and after the package layer is formed, the other carrier plate is removed, so that a plurality of second openings can be formed on the second insulating layer after the other carrier plate is removed.
In the aforementioned method for fabricating a package on package structure, after forming the package layer, another electronic component is disposed on the first coreless package substrate. For example, an encapsulant is formed on the first coreless package substrate, such that the encapsulant encapsulates the other electronic component.
In addition, in the manufacturing method of the package stack structure, the first conductive elements are first disposed on one side of the first coreless package substrate, and then the first coreless package substrate is bonded to the second coreless package substrate. Alternatively, the first conductive elements are first disposed on one side of the second coreless package substrate, and then the first coreless package substrate is bonded to the second coreless package substrate.
As can be seen from the above, the method for manufacturing the package stack structure of the present invention stacks two coreless package substrates, so that compared with the conventional art, the method can not only omit the material and process of the core layer to reduce the manufacturing cost, but also greatly reduce the thickness of the package stack structure.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional package stack structure;
Fig. 2A to 2B are schematic cross-sectional views illustrating a method for fabricating a first coreless stacked package substrate according to the present invention;
FIG. 2B' is a schematic view of another embodiment of FIG. 2B;
Fig. 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a second coreless package substrate according to the present invention;
Fig. 4A to 4C are schematic cross-sectional views illustrating a method for fabricating a package stack structure according to the present invention;
FIGS. 4A 'to 4B' are schematic views of another embodiment of FIGS. 4A to 4B;
FIG. 4C' is a schematic view of another embodiment of FIG. 4C;
FIGS. 5A-5C are schematic cross-sectional views illustrating a method of fabricating a second coreless package substrate according to another embodiment of the present invention; and
Fig. 6A to 6C are schematic cross-sectional views illustrating a method for manufacturing a second coreless package substrate according to another embodiment of the present invention.
Description of the symbols
1,4, 4' package stack structure 10 first semiconductor device
11 first package substrate 110,120 core layer
111,121 wiring layer 12 second package substrate
13,42 solder ball 14 second semiconductor element
15 encapsulant 16 primer
2, 2' first coreless layer type packaging substrate
20,30 carrier plate 21, 21' first insulating layer
210 first opening 22, 22' first dielectric layer
23 first line layer 24 first conductive pillar
25 first conductive element
3, 3' second coreless package substrate
3a,5a,6a line build-up structure 31 second insulation layer
310 second opening 32,52,62 second dielectric layer
32 ', 52' solder mask layer 33,53,63 second circuit layer
34,54,64 second conductive post 35 second conductive element
40,44 active surface of electronic component 40a
40b non-active surface 400 electrode pad
41 packaging layer 41' primer
43 solder material 50,60 carrier
500 Release layers 501,601 Metal layers
H, T thickness 45 encapsulant.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the present disclosure, and are not used for limiting the conditions of the present disclosure, which will not be technically significant, and any structural modifications, ratio changes or size adjustments should be made within the scope of the present disclosure without affecting the function and the achievable purpose of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention unless otherwise specified.
Fig. 2A to 2B are schematic cross-sectional views illustrating a method for manufacturing a first coreless stacked package substrate 2 according to the present invention.
As shown in fig. 2A, a first insulating layer 21 is formed on a carrier 20.
In the present embodiment, the carrier 20 is a metal plate, a semiconductor wafer or a glass plate.
The first insulating layer 21 is made of a material selected from a solder mask layer of green paint, Polyimide (PI), polyamide-imide (PAI), or Polybenzimidazole (PBI).
As shown in fig. 2B, a first dielectric layer 22 is formed on the first insulating layer 21, a first circuit layer 23 and a plurality of first conductive pillars 24 formed on the first circuit layer 23 are embedded in the first dielectric layer 22, and the first conductive pillars 24 are exposed out of the first dielectric layer 22. Next, a plurality of first conductive elements 25 are formed on the first dielectric layer 22 (i.e., the first conductive pillars 24) and electrically connected to the first circuit layer 23 through the first conductive pillars 24.
In the present embodiment, the arrangement order of the first dielectric layer 22, the first circuit layer 23 and the first conductive pillar 24 is not particularly limited. For example, first, a first circuit layer 23 is formed on the first insulating layer 21, a first conductive pillar 24 is formed on a portion of the first circuit layer 23, and a dielectric material is formed on the first insulating layer 21, so that the first circuit layer 23 and the first conductive pillar 24 are embedded in the first dielectric layer 22.
In addition, there is no particular limitation on the material forming the first dielectric layer 22, such as a prepreg (prepreg), a molding compound (molding compound), or a photosensitive dielectric layer. In addition, the material for forming the first dielectric layer 22 may be the same as the material for forming the first insulating layer 21.
The first conductive element 25 is a copper pillar, a solder ball (solder ball), or a solder ball with a core copper ball (Cu core ball), and the shape thereof is not limited, and may be a cylinder, an elliptical cylinder, or a polygonal cylinder.
In addition, as shown in fig. 2B ', the first coreless package substrate 2 ' may omit the fabrication of the first conductive pillar 24, such that the first conductive element 25 is disposed on the first circuit layer 23 and is directly electrically connected to the first circuit layer 23, and the first dielectric layer 22 ' may be a solder mask layer such as a green paint. Specifically, a first insulating layer 21 'such as a dielectric material may be selectively formed on a carrier 20, for example, when the carrier 20 is made of copper, and the carrier 20 is subsequently removed, the first insulating layer 21' can prevent over-etching (over-etching) to avoid damaging the first circuit layer 23; if the carrier 20 and the first circuit layer 23 are made of different materials, the first insulating layer 21' can be omitted.
Fig. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing a second coreless package substrate 3 according to the present invention.
As shown in fig. 3A to 3C, a carrier 30 having a second insulating layer 31 is provided, and a circuit build-up structure 3A is formed on the second insulating layer 31. Next, a plurality of second conductive elements 35 are formed on the line build-up structure 3a and electrically connected to the line build-up structure 3 a.
In the present embodiment, the carrier 30 is a metal plate, a semiconductor wafer or a glass plate.
the second insulating layer 31 is made of a material selected from a solder mask layer of green paint, Polyimide (PI), polyamide-imide (PAI), or Polybenzimidazole (PBI).
The circuit build-up structure 3a further includes a plurality of second dielectric layers 32, a second circuit layer 33 disposed on the second dielectric layer 32, and a plurality of second conductive pillars 34 embedded in the second dielectric layer 32 to electrically connect the second circuit layer 33. Specifically, the second dielectric layer 32 is formed by a material such as a prepreg (prepreg), a molding compound (molding compound) or a photosensitive dielectric layer, but not limited thereto, and the arrangement order of the second dielectric layer 32, the second circuit layer 33 and the second conductive pillar 34 is not particularly limited. For example, first, the second conductive pillars 34 are formed on the second circuit layer 33, the second dielectric layer 32 is formed on the second insulating layer 31 to cover the second circuit layer 33 and the second conductive pillars 34, and a solder mask layer 32 'such as a green paint is further formed on the outermost second dielectric layer 32 and the second circuit layer 33, so that a portion of the surface of the outermost second circuit layer 33 is exposed from the solder mask layer 32'.
The second conductive element 35 is not particularly limited, and may be a copper pillar, a solder ball (solder ball), or a solder ball with a core copper ball (Cu core ball), and is disposed on the second circuit layer 33 and directly electrically connected to the second circuit layer 33.
Fig. 4A to 4C are schematic cross-sectional views illustrating a method for fabricating the package stack structure 4 according to the present invention.
As shown in fig. 4A, the structure shown in fig. 3C is provided, and an electronic component 40 is disposed on a portion of the second conductive element 35 of the second coreless package substrate 3.
in the present embodiment, the electronic component 40 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, and an inductor, or a combination thereof. In the present embodiment, the electronic component 40 is a semiconductor chip having an active surface 40a and an inactive surface 40b opposite to each other, the active surface 40a has a plurality of electrode pads 400, and the electrode pads 400 are electrically connected to the second circuit layer 33 through the second conductive elements 35 in a flip-chip manner. In another embodiment, the second conductive element 35 is formed on the electrode pad 400, and the electronic element 40 is bonded to the second circuit layer 33 through the second conductive element 35.
As shown in fig. 4B, the structure shown in fig. 2B is provided, and the first conductive element 25 of the first coreless package substrate 2 is combined with a portion of the second conductive element 35 of the second coreless package substrate 3, so that the first coreless package substrate 2 is stacked on the second coreless package substrate 3. Next, an encapsulation layer 41 is formed between the first coreless package substrate 2 and the second coreless package substrate 3, so that the electronic element 40, the first conductive elements 25 and the second conductive elements 35 are encapsulated by the encapsulation layer 41.
In the present embodiment, the package layer 41 is an insulating material, such as an encapsulant of epoxy resin.
In addition, before the first coreless package substrate 2 and the second coreless package substrate 3 are combined, an underfill (not shown) may be formed between the electronic component 40 and the second coreless package substrate 3.
It should be understood that the structure shown in fig. 2B' may be stacked instead of the structure shown in fig. 2B.
In another embodiment, as shown in fig. 4A 'and 4B', the first conductive elements 25 may be first disposed on one side of the second coreless package substrate 3, and a portion of the second conductive elements 35 is disposed on the first coreless package substrate 2, and then the first coreless package substrate 2 is bonded to the second coreless package substrate 3.
As shown in fig. 4C, the carrier boards 20 and 30 are removed, and then a plurality of first openings 210 and a plurality of second openings 310 are formed on the first insulating layer 21 and the second insulating layer 31, respectively, so that the first circuit layers 23 are exposed to the first openings 210, and the second circuit layers 33 are exposed to the second openings 310, thereby forming the package stacked structure 4.
In the present embodiment, the thickness T of the package stacked structure 4 is about 440 μm.
In addition, if stacking is performed with the structure shown in fig. 2B ', when the first insulating layer 21 ' is present, a plurality of first openings 210 may be formed on the first insulating layer 21 '; when the first insulating layer 21 'is absent, the first circuit layers 23 are exposed to the first dielectric layer 22'.
In another embodiment, as shown in fig. 4C ', the second circuit layer 33 in the second opening 310 may be bonded with solder balls 42 to be mounted on an electronic device (not shown) such as a circuit board, and the first circuit layer 23 in the first opening 210 may be bonded with solder material 43 to be bonded with another electronic component 44 such as a chip, and then a Package material 45 is formed to cover the electronic component 44, so that the Package-on-Package structure 4' becomes a Package-on-Package (POP).
It should be understood that a package or an electronic device such as a circuit board can also be bonded on the first circuit layer 23 in the first opening 210.
It should be understood that, as shown in fig. 4C ', an underfill 41 ' may be formed between the second coreless package substrate 3 and the electronic component 40 to cover a portion of the second conductive element 35, and the underfill 41 ' is covered by the package layer 41.
The manufacturing method of the invention reduces the thickness of the upper and lower packaging substrates by stacking the first coreless (core) packaging substrates 2,2 'and the second coreless (core) packaging substrates 3, so that compared with the prior art, the manufacturing method not only can save the material and the manufacturing process of the core layer to reduce the manufacturing cost, but also can greatly reduce the overall thickness of the packaging stacking structure 4, 4' to meet the trend of light, thin and short electronic products.
Fig. 5A to 5C are schematic cross-sectional views illustrating another embodiment of a method for manufacturing a second coreless package substrate 3' according to the present invention. The difference between this embodiment and the embodiment of fig. 3A to 3C lies in the process of the line build-up structure 5 a.
As shown in fig. 5A, a carrier 50 is provided, on which a releasing layer 500 and a metal layer 501 are formed. Next, a second circuit layer 53 is formed on the metal layer 501.
As shown in fig. 5B, a plurality of second dielectric layers 52, a second circuit layer 53 disposed on the second dielectric layer 52, and a plurality of second conductive pillars 54 (i.e., conductive blind vias) disposed in the second dielectric layer 52 and electrically connected to the second circuit layer 53 are formed on the metal layer 501.
In the present embodiment, the second dielectric layer 52 is formed first, then the second circuit layer 53 is formed on the second dielectric layer 52, and the second conductive pillar 54 is formed in the second dielectric layer 52.
As shown in fig. 5C, the carrier 50 is removed by the release layer 500, and the metal layer 501 is etched away. Then, solder masks 32 ', 52' are formed on the second dielectric layer 52 on two opposite sides, respectively, and the second circuit layer 53 is exposed from the solder masks 32 ', 52', so as to complete the circuit build-up structure 5 a. Then, a plurality of second conductive elements 35 are formed on at least one of the second circuit layers 53 and electrically connected to the second circuit layers 53.
Therefore, the second coreless package substrate 3' can replace the second coreless package substrate 3 shown in fig. 4C. For example, the second conductive elements 35 combine the electronic element 40 and the first conductive element 25.
Fig. 6A to 6C are schematic cross-sectional views illustrating another embodiment of a method for manufacturing a second coreless package substrate 3 ″ of the present invention. The difference between this embodiment and the embodiment of fig. 3A to 3C lies in the process of the line build-up structure 6 a.
As shown in fig. 6A, a carrier 60 is provided, and a metal layer 601 is formed on the upper and lower sides thereof, and a second dielectric layer 62, a second circuit layer 63 and a second conductive pillar 64 are formed on the metal layer 601 according to the processes shown in fig. 3A to 3B. Next, a carrier 30 and a second insulating layer 31 are formed (e.g., pressed) on the outermost second dielectric layer 62 and the second circuit layer 63.
As shown in fig. 6B, the carrier 60 and the metal layer 601 are removed to expose the second dielectric layer 62 and the second circuit layer 63.
As shown in fig. 6C, a solder mask layer 32 'is formed on the outermost second dielectric layer 62 and the second circuit layer 63, and a portion of the second circuit layer 63 is exposed from the solder mask layer 32'. Next, a plurality of second conductive elements 35 are formed on the exposed second circuit layer 63.
Therefore, in the structure shown in fig. 6C, the electronic component 40 is disposed on a portion of the second conductive element 35 of the second coreless package substrate 3 ″ during the manufacturing process shown in fig. 4A.
In summary, the method for fabricating the package stack structure 4,4 'of the present invention mainly stacks the first coreless package substrates 2, 2' and the second coreless package substrates 3,3 ', 3 ″ to omit the material and process of the core layer and reduce the thickness of the package stack structure 4, 4'.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (18)
1. A method of fabricating a package-on-package structure, the method comprising:
Providing a first coreless laminated packaging substrate and a second coreless laminated packaging substrate, wherein one side of the second coreless laminated packaging substrate is provided with at least one electronic element, and the first coreless laminated packaging substrate is combined to a bearing plate through a first insulating layer;
Bonding the first coreless laminated packaging substrate to one side of the second coreless laminated packaging substrate, which is provided with the electronic element, by a plurality of first conductive elements, wherein the bearing plate is bonded to the other side of the first coreless laminated packaging substrate, which is opposite to the side bonded with the second coreless laminated packaging substrate; and
Forming a packaging layer between the first coreless packaging substrate and the second coreless packaging substrate, so that the packaging layer covers the plurality of first conductive elements and the electronic element.
2. The method of claim 1, wherein the first coreless package substrate further comprises a first dielectric layer and a first circuit layer embedded in the first dielectric layer and electrically connected to the plurality of first conductive elements.
3. The method of claim 2, wherein the first coreless stacked package substrate further comprises a plurality of first conductive pillars embedded in the first dielectric layer and formed on the first circuit layer, such that the plurality of first conductive elements are electrically connected to the first circuit layer through the first conductive pillars.
4. The method of claim 1, further comprising removing the carrier after forming the encapsulation layer.
5. The method of claim 1, further comprising removing the carrier after forming the encapsulation layer.
6. The method of claim 5, further comprising forming a plurality of first openings in the first insulating layer after removing the carrier.
7. The method of claim 1, wherein an underfill is formed between the second coreless package substrate and the electronic component.
8. the method of claim 1, wherein the second coreless package substrate comprises a build-up circuitry structure, and the first conductive element and the electronic element are electrically connected to the build-up circuitry structure.
9. The method of claim 8, wherein the second coreless package substrate further comprises a plurality of second conductive elements formed on the build-up structure and electrically connected to the build-up structure, such that the plurality of second conductive elements combine the first conductive element and the electronic component.
10. The method of claim 9, wherein the encapsulation layer further encapsulates the second conductive elements.
11. The method of claim 8, wherein the second coreless package substrate further comprises a second insulating layer formed over the build-up structure.
12. The method of claim 11, further comprising bonding the second coreless package substrate to another carrier via the second insulating layer before bonding the first and second coreless package substrates.
13. The method of claim 12, further comprising removing the carrier after forming the encapsulation layer.
14. The method of claim 13, further comprising forming a plurality of second openings in the second insulating layer after removing the carrier.
15. The method of claim 1, further comprising disposing another electronic component on the first coreless stacked package substrate after forming the package layer.
16. the method of claim 15, further comprising forming a packaging material on the first coreless substrate such that the packaging material encapsulates the other electronic component.
17. The method of claim 1, wherein the first conductive elements are disposed on one side of the first coreless package substrate, and the first coreless package substrate is bonded to the second coreless package substrate.
18. The method of claim 1, wherein the first conductive elements are disposed on one side of the second coreless package substrate, and the first coreless package substrate is bonded to the second coreless package substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105122020A TWI591739B (en) | 2016-07-13 | 2016-07-13 | Method of manufacture a package stack-up structure |
| TW105122020 | 2016-07-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107622953A CN107622953A (en) | 2018-01-23 |
| CN107622953B true CN107622953B (en) | 2019-12-10 |
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Family Applications (1)
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| TWI701554B (en) * | 2018-12-13 | 2020-08-11 | 英屬維京群島商鯨鏈先進股份有限公司 | Circuit system adapted to hash algorithm |
| TWI740305B (en) * | 2019-12-13 | 2021-09-21 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
| CN118039493B (en) * | 2024-04-12 | 2024-08-06 | 芯爱科技(南京)有限公司 | Method for manufacturing package substrate |
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| CN105742256A (en) * | 2014-11-17 | 2016-07-06 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
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| TWI542263B (en) * | 2014-07-31 | 2016-07-11 | 恆勁科技股份有限公司 | Interposer substrate and a method for fabricating the same |
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| CN105742256A (en) * | 2014-11-17 | 2016-07-06 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
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| CN107622953A (en) | 2018-01-23 |
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