CN107579009A - A kind of multi-chip laminated packaging structure and preparation method thereof - Google Patents
A kind of multi-chip laminated packaging structure and preparation method thereof Download PDFInfo
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- CN107579009A CN107579009A CN201710781927.7A CN201710781927A CN107579009A CN 107579009 A CN107579009 A CN 107579009A CN 201710781927 A CN201710781927 A CN 201710781927A CN 107579009 A CN107579009 A CN 107579009A
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- chip
- lead
- bonding
- wiring layer
- plastic
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The invention discloses a kind of multi-chip laminated packaging structure and preparation method thereof, the encapsulating structure lamination includes at least two dual chip stacked package bodies stacked gradually from the bottom to top, dual chip stacked package body includes lead-bonding chip, upside-down mounting welding core, passivation layer, wiring layer again, bonding wire and orthogonal array lead, upside-down mounting welding core is adhered on lead-bonding chip and the two injection integrates to form plastic-sealed body, passivation layer is additionally provided with the upper and lower surface of plastic-sealed body, wiring layer is arranged between plastic-sealed body and passivation layer and the electrical interconnection of lead-bonding chip and upside-down mounting welding core is realized by bonding wire and orthogonal array lead again.The present invention reduces the cumulative volume of multi-chip package, reduces package thickness, and interconnection up and down is completed by orthogonal array lead, and manufacture work flow is simple, and cost is low.
Description
Technical field
The invention belongs to integrated antenna package technical field, and in particular to a kind of multi-chip laminated packaging structure and its making
Method.
Background technology
With the fast development of semiconductor integrated circuit, the functional requirement of integrated circuit is more and more, and multi-chip interconnection carries
The demand of high integration is more highlighted, while in order to meet miniaturization, light-weighted needs, 3-D stacks encapsulation has been complied with above-mentioned
Demand fast development is got up.
3-D stacks encapsulation can improve packaging density, reduce the interconnection length between chip, be to improve integrated circuit fortune
Row performance, functional diversities can be realized by the combination of multi-chip in addition.3-D stacks are encapsulated to complete Vertical Square at present
To interconnection, usually utilize silicon hole（TSV）Three-dimensional vertical interconnection to be realized, stacks density maximum, appearance and size is minimum, but
It is that process costs are of a relatively high.In addition, the vertical stacks of lead-bonding chip and upside-down mounting welding core how are completed in a three-dimensional structure
It is folded not solve method well.
The content of the invention
In order to solve the above-mentioned technical problem, the invention provides a kind of multi-chip laminated packaging structure and preparation method thereof.
In order to achieve the above object, technical scheme is as follows：
The present invention provides a kind of multi-chip laminated packaging structure, including at least two dual chip laminations stacked gradually from the bottom to top
Packaging body, dual chip stacked package body include lead-bonding chip, upside-down mounting welding core, passivation layer, again wiring layer, bonding wire and hang down
Straight array leads, upside-down mounting welding core is adhered on lead-bonding chip and the two injection integrates to form plastic-sealed body, plastic packaging
Passivation layer is additionally provided with the upper and lower surface of body, then wiring layer is arranged between plastic-sealed body and passivation layer and passes through bonding wire
The electrical interconnection of lead-bonding chip and upside-down mounting welding core is realized with orthogonal array lead.
Preferably, passivation layer includes the first passivation layer and the second passivation layer, and the first passivation layer is arranged at the following table of plastic-sealed body
Face, the second passivation layer are arranged at the upper surface of plastic-sealed body；Wiring layer includes the first wiring layer and the second wiring layer again again again, and first
Wiring layer is arranged between the lower surface of plastic-sealed body and the first passivation layer again, second again wiring layer be arranged at the upper surface of plastic-sealed body
And second between passivation layer, bonding wire is electrically connected to lead-bonding chip and first again between wiring layer, orthogonal array lead electricity
It is connected to the first wiring layer and second again between wiring layer again.
Preferably, first again wiring layer, second pad is additionally provided with wiring layer again, positioned at the second pad on wiring layer again
On be additionally provided with array salient point.
Preferably, pad is circular or square that array salient point is cylindricality or spherical.
Preferably, the size of lead-bonding chip is more than the size of upside-down mounting welding core.
Preferably, lead-bonding chip and upside-down mounting welding core are bonded together by insulating cement.
The present invention also provides a kind of preparation method of multi-chip laminated packaging structure, comprises the following steps：
S1, first vector disk is chosen, make or mount one layer of ephemeral key matched moulds in the upper surface of first vector disk；
S2, make passivation layer and again wiring layer；
S3, by the attachment of the back side of lead-bonding chip over the passivation layer, then the back side of upside-down mounting welding core is mounted with insulating cement
In the front of lead-bonding chip；
S4, the bonding for carrying out with bonding wire lead-bonding chip, then array position carries out vertical routing shape on wiring layer again
Into orthogonal array lead, lead is highly higher than the highest level height of upside-down mounting welding core；
S5, lead-bonding chip, the leaded fixation of upside-down mounting welding core and institute formed by plastic-sealed body using Shooting Technique；
S6, unnecessary soldered ball outside plastic-sealed body and orthogonal array lead polished flat, and make in the upper surface of plastic-sealed body and connect up again
Layer and passivation layer, the electrical interconnection of two chips is completed, array pad is then made by electroplating technology again, eventually forms dual chip
Stacked package body；
S7, using Flip Chip Bond Technique, multiple independent dual chip stacked package bodies are stacked gradually together from the bottom to top, completed
Multi-chip laminated packaging structure.
Preferably, the orthogonal array lead material in step S4 is copper cash.
Preferably, manufacture craft is connected up using wafer scale again in step S2, the Shooting Technique in step S5 is powder injection molding
Mode.
Preferably, array pad is made in step S6 playing skill art or electroplating technology is planted positioned at modeling using wafer scale afterwards
Spherical or cylindrical array salient point is made on the pad of envelope body upper surface, forms complete dual chip stacked package body；Then use
Solve bonding method to peel off dual chip stacked package body and interim bonding film, then formed by the cutting-up of disk multiple independent
Dual chip stacked package body.
The invention has the advantages that：
1st, the upper and lower surface of each dual chip stacked package body completes to interconnect by orthogonal array lead, and compare silicon hole
（TSV）Process costs are relatively low；
2nd, the size of lead-bonding chip is bigger than the size of upside-down mounting welding core in each dual chip stacked package body, can be achieved to fall more
Welding equipment chip and lead-bonding chip are integrated in a packaging body simultaneously；
3rd, the front of lead-bonding chip and the back side of upside-down mounting welding core bond together, and vertical direction saves bonding wire camber
Beyond the height space of chip；
4th, each dual chip stacked package body makes the wiring layer again of tow sides by wafer scale technique, and whole disk adds simultaneously
Work, production efficiency is high, effectively reduces packaging cost；
5th, the first pad made again on wiring layer, the second array salient point made again on wiring layer, it is possible to achieve multiple same
The packaging body of structure is three-dimensional stacked.
Brief description of the drawings
Fig. 1 is the interim structural representation made after bonding film on a kind of disk of multi-chip laminated packaging structure of the present invention
Figure.
Fig. 2 is that the first wiring layer and the again is made on a kind of interim bonding film of multi-chip laminated packaging structure of the present invention
Structural representation after one passivation layer.
Fig. 3 is that lead-bonding chip is mounted on a kind of first passivation layer of multi-chip laminated packaging structure of the present invention and is fallen
Structural representation after welding equipment chip.
Fig. 4 is to increase the structure after bonding wire and orthogonal array lead on a kind of multi-chip laminated packaging structure of the present invention
Schematic diagram.
Fig. 5 is the structural representation that injection forms plastic-sealed body on a kind of multi-chip laminated packaging structure of the present invention.
Fig. 6 is that the second wiring layer, the second passivation layer and pad again is made on a kind of multi-chip laminated packaging structure of the present invention
Structural representation afterwards.
Fig. 7 is that single dual chip lamination seals after the completion of array stud bump making on a kind of multi-chip laminated packaging structure of the present invention
Fill the structural representation of body.
Fig. 8 is a kind of dual chip stacked package body laminated construction schematic diagram of multi-chip laminated packaging structure of the present invention.
Wherein, the 1, first passivation layer 1,2, first wiring layer again, 3, lead-bonding chip, 4- upside-down mounting welding cores, 5, bonding
Silk, the 6, orthogonal array lead, 7, plastic-sealed body, 8, second wiring layer again, the 9, second passivation layer, 10, pad, 11, array salient point,
100th, the first dual chip stacked package body, the 200, second dual chip stacked package body, the 300, the 3rd dual chip stacked package body.
Embodiment
The preferred embodiment that the invention will now be described in detail with reference to the accompanying drawings.
In order to reach the purpose of the present invention, as shown in figure 8, being provided in the one of which embodiment of the present invention a kind of more
Stacked die package structure, including the 3rd dual chip stacked package body 300, the second dual chip lamination stacked gradually from the bottom to top
The dual chip stacked package body 100 of packaging body 200 and first, each dual chip stacked package body include lead-bonding chip 3, upside-down mounting
Core wire piece 4, passivation layer, wiring layer, bonding wire 5 and orthogonal array lead 6, upside-down mounting welding core 4 are adhered to lead-bonding chip 3 again
Upper and the two injection is integrated to form plastic-sealed body 7, and passivation layer, then cloth are additionally provided with the upper and lower surface of plastic-sealed body 7
Line layer is arranged between plastic-sealed body 7 and passivation layer and realizes the He of lead-bonding chip 3 by bonding wire 5 and orthogonal array lead 6
The electrical interconnection of upside-down mounting welding core 4.
Wherein, passivation layer includes the first passivation layer 1 and the second passivation layer 9, and the first passivation layer 1 is arranged under plastic-sealed body 7
Surface, the second passivation layer 9 are arranged at the upper surface of plastic-sealed body 7；Wiring layer includes the first wiring layer again of wiring layer 2 and second again again
8, first again wiring layer 2 be arranged between the lower surface of plastic-sealed body 7 and the first passivation layer 1, second again wiring layer 8 be arranged at plastic packaging
Between the upper surface of body 7 and the second passivation layer 9, bonding wire 5 is electrically connected to lead-bonding chip 3 and first again between wiring layer 2,
Orthogonal array lead 6 is electrically connected to the first wiring layer 2 and second again between wiring layer 8 again.First cloth again of wiring layer 2, second again
Pad 10 is additionally provided with line layer 8, is additionally provided with array salient point 11 on the pad 10 on wiring layer 8 again positioned at second, pad 10 is circle
Shape is square, and array salient point 11 is cylindricality or spherical.
In addition, the size of lead-bonding chip 3 is more than the size of upside-down mounting welding core 4, lead-bonding chip 3 and upside-down mounting core wire
Piece 4 is bonded together by insulating cement.
As shown in figures 1-8, the present invention also provides a kind of preparation method of multi-chip laminated packaging structure, including following step
Suddenly：
S1, first vector disk 13 is chosen, make or mount one layer of ephemeral key matched moulds 12 in the upper surface of first vector disk 13；
S2, connect up manufacture craft again using wafer scale, make the first passivation layer 1 and the first wiring layer 2 again；
S3, the back side of lead-bonding chip 3 is mounted on the first passivation layer 1, then with insulating cement by the back of the body of upside-down mounting welding core 4
Face is mounted on the front of lead-bonding chip 3；
S4, the bonding for carrying out with bonding wire 5 lead-bonding chip 3, then first again on wiring layer 2 array position carry out it is vertical
Routing forms orthogonal array lead 6, and lead is highly higher than the highest level height of upside-down mounting welding core；Wherein, orthogonal array lead 6
Material is copper cash；
S5, lead-bonding chip 3, the leaded fixation of upside-down mounting welding core 4 and institute formed by plastic-sealed body 7 using Shooting Technique；Wherein,
Shooting Technique is the mode of powder injection molding；
S6, by plastic-sealed body 7, unnecessary soldered ball and orthogonal array lead 6 polish flat outside, and make second in the upper surface of plastic-sealed body 7
The passivation layer 9 of wiring layer 8 and second again, the electrical interconnection of two chips is completed, array pad is then made by electroplating technology again, it
It is convex that spherical or cylindrical array is made on the pad positioned at the upper surface of plastic-sealed body 7 using wafer scale plant playing skill art or electroplating technology afterwards
Point, form complete dual chip stacked package body；Then it is bonded using solution bonding method by dual chip stacked package body and temporarily
Film is peeled off, and then forms multiple independent dual chip stacked package bodies by the cutting-up of disk；
S7, using Flip Chip Bond Technique, multiple independent dual chip stacked package bodies are stacked gradually together from the bottom to top, completed
Multi-chip laminated packaging structure.
Above-described is only the preferred embodiment of the present invention, it is noted that for one of ordinary skill in the art
For, without departing from the concept of the premise of the invention, various modifications and improvements can be made, these belong to the present invention
Protection domain.
Claims (10)
1. a kind of multi-chip laminated packaging structure, it is characterised in that including at least two dual chips stacked gradually from the bottom to top
Stacked package body, dual chip stacked package body include lead-bonding chip, upside-down mounting welding core, again passivation layer, wiring layer, bonding wire
With orthogonal array lead, upside-down mounting welding core is adhered on lead-bonding chip and the two injection integrates to form plastic-sealed body,
Passivation layer is additionally provided with the upper and lower surface of plastic-sealed body, then wiring layer is arranged between plastic-sealed body and passivation layer and passes through key
Plying and orthogonal array lead realize the electrical interconnection of lead-bonding chip and upside-down mounting welding core.
2. multi-chip laminated packaging structure according to claim 1, it is characterised in that passivation layer include the first passivation layer and
Second passivation layer, the first passivation layer are arranged at the lower surface of plastic-sealed body, and the second passivation layer is arranged at the upper surface of plastic-sealed body；Cloth again
Line layer includes the first wiring layer and the second wiring layer again again, first again wiring layer be arranged at lower surface and the first passivation of plastic-sealed body
Layer between, second again wiring layer be arranged between the upper surface of plastic-sealed body and the second passivation layer, bonding wire is electrically connected to lead key
Chip and first is closed again between wiring layer, orthogonal array lead is electrically connected to the first wiring layer and second again between wiring layer again.
3. multi-chip laminated packaging structure according to claim 2, it is characterised in that the first cloth again of wiring layer, second again
Pad is additionally provided with line layer, array salient point is additionally provided with the pad on wiring layer again positioned at second.
4. multi-chip laminated packaging structure according to claim 3, it is characterised in that pad is circular or square, array
Salient point is cylindricality or spherical.
5. multi-chip laminated packaging structure according to claim 1, it is characterised in that the size of lead-bonding chip is more than
The size of upside-down mounting welding core.
6. multi-chip laminated packaging structure according to claim 1, it is characterised in that lead-bonding chip and upside-down mounting core wire
Piece is bonded together by insulating cement.
A kind of 7. preparation method of multi-chip laminated packaging structure as described in claim 1-6 is any, it is characterised in that including
Following steps：
S1, first vector disk is chosen, make or mount one layer of ephemeral key matched moulds in the upper surface of first vector disk；
S2, make passivation layer and again wiring layer；
S3, by the attachment of the back side of lead-bonding chip over the passivation layer, then the back side of upside-down mounting welding core is mounted with insulating cement
In the front of lead-bonding chip；
S4, the bonding for carrying out with bonding wire lead-bonding chip, then array position carries out vertical routing shape on wiring layer again
Into orthogonal array lead, lead is highly higher than the highest level height of upside-down mounting welding core；
S5, lead-bonding chip, the leaded fixation of upside-down mounting welding core and institute formed by plastic-sealed body using Shooting Technique；
S6, unnecessary soldered ball outside plastic-sealed body and orthogonal array lead polished flat, and make in the upper surface of plastic-sealed body and connect up again
Layer and passivation layer, the electrical interconnection of two chips is completed, array pad is then made by electroplating technology again, eventually forms dual chip
Stacked package body；
S7, using Flip Chip Bond Technique, multiple independent dual chip stacked package bodies are stacked gradually together from the bottom to top, completed
Multi-chip laminated packaging structure.
8. the preparation method of multi-chip laminated packaging structure according to claim 7, it is characterised in that hanging down in step S4
Straight array leads material is copper cash.
9. the preparation method of multi-chip laminated packaging structure according to claim 7, it is characterised in that used in step S2
Wafer scale connects up manufacture craft again, and the Shooting Technique in step S5 is the mode of powder injection molding.
10. the preparation method of multi-chip laminated packaging structure according to claim 7, it is characterised in that made in step S6
Make to use wafer scale plant playing skill art or electroplating technology to make ball on the pad positioned at plastic-sealed body upper surface after array pad
Shape or cylindrical array salient point, form complete dual chip stacked package body；Then dual chip lamination is sealed using solution bonding method
Fill body and interim bonding film is peeled off, multiple independent dual chip stacked package bodies are then formed by the cutting-up of disk.
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| CN201710781927.7A CN107579009A (en) | 2017-09-02 | 2017-09-02 | A kind of multi-chip laminated packaging structure and preparation method thereof |
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Cited By (5)
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| CN108417556A (en) * | 2018-05-23 | 2018-08-17 | 奥肯思（北京）科技有限公司 | Multichip stacking encapsulation structure |
| CN109326580A (en) * | 2018-11-20 | 2019-02-12 | 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 | A kind of multi-chip package interconnection architecture and multi-chip package interconnected method |
| CN111900155A (en) * | 2020-08-19 | 2020-11-06 | 上海先方半导体有限公司 | Modular packaging structure and method |
| CN112770495A (en) * | 2019-10-21 | 2021-05-07 | 宏启胜精密电子(秦皇岛)有限公司 | Omnidirectional embedded module and manufacturing method thereof, packaging structure and manufacturing method thereof |
| CN113725153A (en) * | 2021-08-31 | 2021-11-30 | 中国电子科技集团公司第五十八研究所 | Multilayer multi-chip fan-out type three-dimensional integrated packaging method and structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108417556A (en) * | 2018-05-23 | 2018-08-17 | 奥肯思（北京）科技有限公司 | Multichip stacking encapsulation structure |
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| CN113725153A (en) * | 2021-08-31 | 2021-11-30 | 中国电子科技集团公司第五十八研究所 | Multilayer multi-chip fan-out type three-dimensional integrated packaging method and structure |
| CN113725153B (en) * | 2021-08-31 | 2023-10-27 | 中国电子科技集团公司第五十八研究所 | Multilayer multi-chip fan-out type three-dimensional integrated packaging method and structure |
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Application publication date: 20180112 |