CN110349933A - A kind of encapsulating structure and preparation method of wafer bonding stacked chips - Google Patents
A kind of encapsulating structure and preparation method of wafer bonding stacked chips Download PDFInfo
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- CN110349933A CN110349933A CN201910667794.XA CN201910667794A CN110349933A CN 110349933 A CN110349933 A CN 110349933A CN 201910667794 A CN201910667794 A CN 201910667794A CN 110349933 A CN110349933 A CN 110349933A
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- 238000009713 electroplating Methods 0.000 claims description 7
- 239000012778 molding material Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 4
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- 238000000034 method Methods 0.000 abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 230000006870 function Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
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- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
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- 239000011231 conductive filler Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 102000057593 human F8 Human genes 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000000206 moulding compound Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
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- 229920001568 phenolic resin Polymers 0.000 description 1
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- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/32146—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the layer connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Abstract
The invention discloses the encapsulating structures and preparation method of a kind of wafer bonding stacked chips, encapsulating structure includes chip bonding body, multiple monomer wafer stage chips including stacking setting, it is bonded between the monomer wafer stage chip by bonded layer, i.e., forms stacked chips after wafer bonding；Conductive through hole realizes the connection of stacked chips pad function leading-out terminal, and for the stacked chips that encapsulating structure provided in an embodiment of the present invention is formed by wafer bonding by side wall signal interconnection, encapsulation volume is small.Preparation method provided in an embodiment of the present invention is not necessarily to complexity TSV technique, avoids as directly or indirectly making chip internal stress and damage problem caused by through-hole to chip, and processing procedure process is simple, and production capacity is high.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, and in particular to a kind of encapsulating structure of wafer bonding stacked chips and
Preparation method.
Background technique
In recent years, in 3D chip package or wafer-level packaging, inverse bonding encapsulates the appearance of (Flip-Chip, FC) technique
The volume of chip package can be made to reduce, in order to increase input/output (Input/Output, I/O) interface, generally in FC technique
On the basis of through silicon via (Through Silicon Via, TSV) operation is carried out to chip, but silicon is carried out to chip or wafer
Through-hole operation will lead to wafer and generate internal stress, causes to damage to wafer.
Summary of the invention
Therefore, the present invention a kind of encapsulating structure and preparation method of wafer bonding stacked chips, overcomes in the prior art
In 3D chip package or wafer-level packaging, by the way that the defect of internal stress and damage can be generated to chip operation TSV.
In a first aspect, the present invention provides a kind of encapsulating structure of wafer bonding stacked chips, comprising: chip bonding body, packet
The multiple monomer wafer stage chips for stacking setting are included, are bonded between the monomer wafer stage chip by bonded layer；Conductive through hole,
It is connected to the function leading-out terminal of each monomer wafer stage chip.
In one embodiment, the encapsulating structure of the wafer bonding stacked chips, further includes: molding material coats institute
State chip bonding body.
In one embodiment, the encapsulating structure of the wafer bonding stacked chips, further includes: reroute layer, be formed in
Chip bonding body side is realized by conductive through hole and is electrically connected with the chip bonding body.
In one embodiment, the encapsulating structure of the wafer bonding stacked chips, further includes: multiple salient points are set to
On the multiple pads for rerouting layer.
In one embodiment, filling conducting resinl or conductive metal in the conductive through hole.
Second aspect, the embodiment of the present invention provide a kind of preparation method of round grade chip-packaging structure, include the following steps:
Preset quantity wafer stage chip is bonded by bonded layer, forms chip bonding body；The chip bonding body is cut
It cuts, forms multiple single modules；The multiple single module is packaged, recombination wafer is formed；In the crystalline substance for being located at bonded layer
The corresponding position of circle grade chip functions leading-out terminal forms conductive through hole.
In one embodiment, before described the step of being bonded preset quantity wafer stage chip by bonded layer, also
It include: that the opposite face of wafer stage chip bonding face is subjected to reduction processing.
In one embodiment, described formed in the corresponding position for being located at the wafer stage chip function leading-out terminal of bonded layer is led
After the step of electric through-hole, further includes: fill conducting medium in through-holes, and conducting medium is carried out interconnected electroplating, form weight
Wiring layer.
In one embodiment, described to fill conducting medium in through-holes, and conducting medium is subjected to interconnected electroplating, form weight
After the step of wiring layer, further includes: carry out salient point preparation rerouting layer.
In one embodiment, it is described reroute layer carry out salient point preparation the step of after, further includes: to recombination wafer into
Row cutting, forms single wafer stage chip structure.
1, the encapsulating structure of wafer bonding stacked chips provided by the invention, including, chip bonding body comprising stacking is set
The multiple monomer wafer stage chips set pass through bonded layer between monomer wafer stage chip and are bonded；Conductive through hole, with each monomer core
The function leading-out terminal of piece is connected to, and encapsulating structure provided in an embodiment of the present invention passes through side by the stacked chips that wafer bonding is formed
Wall signal interconnection, encapsulation volume are small.
2, the preparation method of the encapsulating structure of wafer bonding stacked chips provided by the invention, by preset quantity wafer scale core
Piece is bonded by bonded layer, forms chip bonding body；Chip bonding body is cut, multiple single modules are formed；It will
Multiple single modules are packaged, and form recombination wafer；It is being located at the corresponding of the wafer stage chip function leading-out terminal of bonded layer
Position formed conductive through hole, preparation method provided in an embodiment of the present invention be not necessarily to TSV technique, avoid due to chip directly or
Chip internal stress and damage problem caused by production through-hole indirectly, processing procedure process is simple, and production capacity is high.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the signal of a specific example of the encapsulating structure of wafer bonding stacked chips provided in an embodiment of the present invention
Figure；
Fig. 2 is showing for another specific example of the encapsulating structure of wafer bonding stacked chips provided in an embodiment of the present invention
It is intended to；
Fig. 3 is showing for another specific example of the encapsulating structure of wafer bonding stacked chips provided in an embodiment of the present invention
It is intended to；
Fig. 4 is showing for another specific example of the encapsulating structure of wafer bonding stacked chips provided in an embodiment of the present invention
It is intended to；
Fig. 5 is one specific example of encapsulating structure preparation method of wafer bonding stacked chips provided in an embodiment of the present invention
Flow chart；
Fig. 6 is the schematic diagram before chip bonding provided in an embodiment of the present invention is thinned；
Fig. 7 is chip thinning provided in an embodiment of the present invention treated schematic diagram；
Fig. 8 is the schematic diagram of chip bonding body provided in an embodiment of the present invention；
Fig. 9 is the schematic diagram of single module provided in an embodiment of the present invention；
Figure 10 is the schematic diagram of recombination wafer provided in an embodiment of the present invention；
Figure 11 is the schematic diagram provided in an embodiment of the present invention for forming conductive through hole；
Figure 12 is that another is specific for the encapsulating structure preparation methods of wafer bonding stacked chips provided in an embodiment of the present invention
Exemplary flow chart；
Figure 13 is the schematic diagram provided in an embodiment of the present invention for being formed and rerouting layer；
Figure 14 is provided in an embodiment of the present invention in the schematic diagram for rerouting layer progress salient point preparation.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also indirectly connected through an intermediary, it can be with
It is the connection inside two elements, can be wireless connection, be also possible to wired connection.For those of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
As long as in addition, the non-structure each other of technical characteristic involved in invention described below different embodiments
It can be combined with each other at conflict.
Embodiment 1
The present embodiment provides a kind of encapsulating structures of wafer bonding stacked chips, as shown in Figure 1, comprising: chip bonding body
1, including stacking the multiple monomer wafer stage chips 11 being arranged, it is bonded between the monomer wafer stage chip by bonded layer 12；
Conductive through hole 2 is connected to the function leading-out terminal 13 of each monomer wafer stage chip 11.Chip is to deposit in embodiments of the present invention
Chip is stored up, bonded layer will be passed through together between monomer wafer stage chip, pass through conductive through hole 2 and each monomer wafer stage chip
11 function leading-out terminal 13 is connected to, and can expand the memory capacity of chip.
The encapsulating structure of wafer bonding stacked chips provided by the invention, including, chip bonding body comprising stack setting
Multiple monomer wafer stage chips, be bonded by bonded layer between monomer wafer stage chip, i.e., form stacking core after wafer bonding
Piece；Conductive through hole is connected to the function leading-out terminal of each monomer chip, and encapsulating structure provided in an embodiment of the present invention passes through core
The side wall of piece bonding body carries out signal interconnection, and encapsulation volume is smaller.
In one embodiment, the encapsulating structure of wafer bonding stacked chips, as shown in Figure 2, further includes: molding material 3, packet
Cover chip bonding body 1 and conductive through hole 2.Chip bonding body 1 and conductive through hole 2 are packaged by molding material 3.This implementation
In example, molding material 3 is epoxy molding material, and it is matrix resin that epoxy molding material, which is by epoxy resin, with high-performance
Phenolic resin is curing agent, and it is powdery moulding compound made of filler, and a variety of additive mixtures of addition that silicon powder etc., which is added,.Plastic packaging
Process is that EMC is squeezed into die cavity with transfer molding process and embeds semiconductor chip therein, while crosslinking curing forms, at
For the semiconductor devices with certain structure external form.
In one embodiment, the encapsulating structure of wafer bonding stacked chips, as shown in Figure 3, further includes: reroute layer 4, shape
At in 1 side of chip bonding body, is realized by conductive through hole 2 and be electrically connected with chip bonding body 1.The embodiment of the present invention passes through weight
Each monomer wafer stage chip is carried out interconnected electroplating by wiring layer 4, and chip functions are drawn.
In one embodiment, the encapsulating structure of wafer bonding stacked chips, as shown in Figure 4, further includes: multiple salient points 5, if
It is placed on the multiple pads for rerouting layer 3.The multiple salient points 5 formed are convenient to be electrically connected with other devices.The present embodiment is convex
Point is all tin ball, and it may be other materials, such as copper ball that however, it is not limited to this in other embodiments.
In one embodiment, enclosure cavity processing enclosure cavity is done in the bond pad surface for rerouting layer 3
Abbreviation UBM (Under Ball Metal), the upper surface of UBM would generally be done tin ball (Solder Ball), be that copper is led below UBM
Line or copper pad.The purpose of UBM is to prevent tin ball from the metallic copper of copper conductor or copper pad and metallic tin are formed alloy when flowing back,
Cause tin ball not connect with chip firmly, the problem of reliability failures occurs.
In embodiments of the present invention, bonded layer is organic bond, such as organic gel；In conductive through hole filling conducting resinl or
Conductive metal, wherein the conductive filler of conducting resinl can be silver, copper, aluminium, zinc, iron, the powder of nickel and graphite and some conductings
Close object, conductive metal be copper, aluminium, zinc, iron, nickel or alloy, it is above only to be illustrated with this, be not limited.
Embodiment 2
The embodiment of the present invention provides a kind of preparation method of the encapsulating structure of wafer bonding stacked chips, as shown in figure 5, packet
Include following steps:
Step S10: the opposite face of wafer stage chip bonding face is subjected to reduction processing.By being conducive to contract after reduction processing
The size of small package, the schematic diagram being illustrated in figure 6 before being thinned are the schematic diagram after reduction processing as shown in Figure 7.
Step S11: preset quantity wafer stage chip is bonded by bonded layer, forms chip bonding body.In this hair
In bright embodiment, wafer stage chip is storage chip, and bonded layer is organic bond, such as organic gel, the chip bonding of formation
Body is as shown in Figure 8.
Step S12: the chip bonding body is cut, and forms multiple single modules.What the embodiment of the present invention was formed
Single module is as shown in Figure 9.
Step S13: the multiple single module is packaged, and forms recombination wafer.The core that the embodiment of the present invention is formed
Piece bonding body is as shown in Figure 10.
Step S14: conductive through hole is formed in the corresponding position for being located at the wafer stage chip function leading-out terminal of bonded layer.?
In the embodiment of the present invention, conductive through hole is formed by laser ablation or etching, as shown in figure 11.
In one embodiment, after executing step S14, as shown in figure 12, further includes:
Step S15: conducting medium is filled in through-holes, and conducting medium is subjected to interconnected electroplating, is formed and reroutes layer.This
Each monomer wafer stage chip is carried out interconnected electroplating by rerouting layer, by chip functions as shown in figure 13 by inventive embodiments
It draws.
Step S16: salient point preparation is carried out rerouting layer.The embodiment of the present invention, as shown in figure 14, by print solder paste or
The method production salient point of molding tin ball is directly placed as soldered ball, is conveniently electrically connected with other devices.
Step S17: recombination wafer is cut, single wafer stage chip structure is formed.The embodiment of the present invention will recombinate
After wafer cutting, single wafer stage chip structure as shown in Figure 4 is formed.The present invention uses the packing forms of wafer scale, production
More efficient, cost advantage is bigger.
The preparation method of the encapsulating structure of wafer bonding stacked chips provided by the invention, by preset quantity wafer stage chip
It is bonded by bonded layer, forms chip bonding body；Chip bonding body is cut, multiple single modules are formed；It will be more
A single module is packaged, and forms recombination wafer；In the corresponding positions for the wafer stage chip function leading-out terminal for being located at bonded layer
Set to form conductive through hole, preparation method provided in an embodiment of the present invention be not necessarily to TSV technique, avoid due to chip directly or
Chip internal stress and damage problem caused by production through-hole are connect, processing procedure process is simple, and production capacity is high.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes still within the protection scope of the invention.
Claims (11)
1. a kind of encapsulating structure of wafer bonding stacked chips characterized by comprising
Chip bonding body passes through key between the monomer wafer stage chip including stacking the multiple monomer wafer stage chips being arranged
Close layer bonding；
Conductive through hole is connected to the function leading-out terminal of each monomer wafer stage chip.
2. the encapsulating structure of wafer bonding stacked chips according to claim 1, which is characterized in that further include: molding material
Material, coats the chip bonding body.
3. the encapsulating structure of wafer bonding stacked chips according to claim 1 or 2, which is characterized in that further include: weight cloth
Line layer is formed in chip bonding body side, is realized by conductive through hole and is electrically connected with the chip bonding body.
4. the encapsulating structure of wafer bonding stacked chips according to claim 3, which is characterized in that further include: it is multiple convex
Point is set on the multiple pads for rerouting layer.
5. the encapsulating structure of wafer bonding stacked chips according to claim 1, which is characterized in that the bonded layer is to have
Machine adhesive.
6. the encapsulating structure of wafer bonding stacked chips according to claim 1, which is characterized in that in the conductive through hole
Fill conducting resinl or conductive metal.
7. a kind of preparation method of the encapsulating structure of wafer bonding stacked chips, which comprises the steps of:
Preset quantity wafer stage chip is bonded by bonded layer, forms chip bonding body；
The chip bonding body is cut, multiple single modules are formed；
The multiple single module is packaged, recombination wafer is formed；
Conductive through hole is formed in the corresponding position for being located at the wafer stage chip function leading-out terminal of bonded layer.
8. the preparation method of the encapsulating structure of wafer bonding stacked chips according to claim 7, which is characterized in that described
Before the step of preset quantity wafer stage chip is bonded by bonded layer, further includes:
The opposite face of wafer stage chip bonding face is subjected to reduction processing.
9. the preparation method of the encapsulating structure of wafer bonding stacked chips according to claim 7, which is characterized in that described
After being located at the step of corresponding position of wafer stage chip function leading-out terminal of bonded layer forms conductive through hole, further includes:
Conducting medium is filled in through-holes, and conducting medium is subjected to interconnected electroplating, is formed and is rerouted layer.
10. the preparation method of the encapsulating structure of wafer bonding stacked chips according to claim 9, which is characterized in that institute
It states and fills conducting medium in through-holes, and conducting medium is subjected to interconnected electroplating, formed after the step of rerouting layer, also wrapped
It includes:
Salient point preparation is carried out rerouting layer.
11. the preparation method of the encapsulating structure of wafer bonding stacked chips according to claim 10, which is characterized in that institute
It states after rerouting the step of layer carries out salient point preparation, further includes:
Recombination wafer is cut, single wafer stage chip structure is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910667794.XA CN110349933A (en) | 2019-07-23 | 2019-07-23 | A kind of encapsulating structure and preparation method of wafer bonding stacked chips |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910667794.XA CN110349933A (en) | 2019-07-23 | 2019-07-23 | A kind of encapsulating structure and preparation method of wafer bonding stacked chips |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021146860A1 (en) * | 2020-01-20 | 2021-07-29 | 深圳市汇顶科技股份有限公司 | Stacked chip, manufacturing method, image sensor, and electronic device |
| CN113793811A (en) * | 2021-11-16 | 2021-12-14 | 湖北三维半导体集成创新中心有限责任公司 | Connecting method of chip stacking structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100020766A (en) * | 2008-08-13 | 2010-02-23 | 주식회사 하이닉스반도체 | Stack package |
| CN101999167A (en) * | 2008-03-12 | 2011-03-30 | 垂直电路公司 | Support mounted electrically interconnected die assembly |
| CN102246298A (en) * | 2008-12-09 | 2011-11-16 | 垂直电路公司 | Semiconductor die interconnect formed by aerosol application of electrically conductive material |
| CN103413785A (en) * | 2013-08-02 | 2013-11-27 | 南通富士通微电子股份有限公司 | Chip cutting method and chip packaging method |
| US20140097544A1 (en) * | 2012-10-05 | 2014-04-10 | Altera Corporation | Side Stack Interconnection for Integrated Circuits and The Like |
| CN210136868U (en) * | 2019-07-23 | 2020-03-10 | 上海先方半导体有限公司 | Packaging structure of wafer bonding stacked chip |
-
2019
- 2019-07-23 CN CN201910667794.XA patent/CN110349933A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101999167A (en) * | 2008-03-12 | 2011-03-30 | 垂直电路公司 | Support mounted electrically interconnected die assembly |
| KR20100020766A (en) * | 2008-08-13 | 2010-02-23 | 주식회사 하이닉스반도체 | Stack package |
| CN102246298A (en) * | 2008-12-09 | 2011-11-16 | 垂直电路公司 | Semiconductor die interconnect formed by aerosol application of electrically conductive material |
| US20140097544A1 (en) * | 2012-10-05 | 2014-04-10 | Altera Corporation | Side Stack Interconnection for Integrated Circuits and The Like |
| CN103956330A (en) * | 2012-10-05 | 2014-07-30 | 阿尔特拉公司 | Side stack interconnection for integrated circuits and the like |
| CN103413785A (en) * | 2013-08-02 | 2013-11-27 | 南通富士通微电子股份有限公司 | Chip cutting method and chip packaging method |
| CN210136868U (en) * | 2019-07-23 | 2020-03-10 | 上海先方半导体有限公司 | Packaging structure of wafer bonding stacked chip |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021146860A1 (en) * | 2020-01-20 | 2021-07-29 | 深圳市汇顶科技股份有限公司 | Stacked chip, manufacturing method, image sensor, and electronic device |
| CN113793811A (en) * | 2021-11-16 | 2021-12-14 | 湖北三维半导体集成创新中心有限责任公司 | Connecting method of chip stacking structure |
| CN113793811B (en) * | 2021-11-16 | 2022-02-15 | 湖北三维半导体集成创新中心有限责任公司 | Connecting method of chip stacking structure |
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