WO2021146860A1

WO2021146860A1 - Stacked chip, manufacturing method, image sensor, and electronic device

Info

Publication number: WO2021146860A1
Application number: PCT/CN2020/073303
Authority: WO
Inventors: 陆斌; 姚国峰; 沈健
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2020-01-20
Filing date: 2020-01-20
Publication date: 2021-07-29
Also published as: CN111819689A

Abstract

A stacked chip, a manufacturing method, an image sensor, and an electronic device, capable of reducing the manufacturing cost of stacked chips. The stacked chip comprises: a carrier unit provided with a first accommodating structure therein, the first accommodating structure being a recess or a through hole; a first chip disposed in the first accommodating structure; a rewiring layer disposed above the first chip; a first pad disposed above the rewiring layer, the first pad being electrically connected to the first chip by means of the rewiring layer; and a second chip stacked above the carrier unit and the first chip, the second chip comprising a second pad, and the second pad being electrically connected to the first pad, wherein the surface area of the second chip is greater than that of the first chip.

Description

Stacked chip, manufacturing method, image sensor and electronic device

Technical field

This application relates to the field of semiconductor chips, and more specifically, to a stacked chip, a manufacturing method, an image sensor, and an electronic device.

Background technique

With the development of semiconductor and integrated circuit technology, the device types of chips are becoming more and more abundant, and the integration degree is getting higher and higher. On the two-dimensional plane, as the semiconductor technology develops to a certain extreme degree, the performance of the chip cannot be further improved. Therefore, a three-dimensional stacking concept has been proposed in the industry to expand the chip from two-dimensional to three-dimensional, that is, chip modules with different functions are stacked on top of each other for packaging, thereby improving the overall performance and yield of the chip.

In one implementation, the upper die and the lower die are stacked together in a wafer-to-wafer manner through a wafer-level bonding process (Wafer-level Bonding Process) to form a stacked Three-dimensional chip. In order to meet the stacking process requirements, the upper and lower wafers have the same wafer size, and the number of upper wafers on the upper wafer is equal to the number of wafers on the lower wafer, but when the upper and lower wafers are not the same type of wafers, This stacking method will cause a waste of wafer area and increase the manufacturing cost of stacked chips.

Therefore, how to reduce the manufacturing cost of stacked chips is an urgent problem to be solved.

Summary of the invention

The embodiments of the present application provide a stacked chip, a manufacturing method, an image sensor, and an electronic device, which can reduce the manufacturing cost of the stacked chip.

In a first aspect, a stacked chip is provided, including: a carrier unit in which a first accommodating structure is provided, and the first accommodating structure is a groove or a through hole; a first wafer is provided in the first accommodating The rewiring layer is arranged above the first wafer; the first pad is arranged above the rewiring layer, and the first pad is electrically connected to the first wafer through the rewiring layer; the second wafer , Stacked above the carrier unit and the first chip, the second chip includes a second pad, and the second pad is electrically connected to the first pad, wherein the surface area of the second chip is larger than the first pad The surface area of a wafer.

In the embodiment of the present application, the first accommodating structure in the carrier unit provides support and stability for the first wafer, so that a large-area second wafer can be stacked on a small-area first wafer, so that a stacked chip structure can be realized. At the same time, it is also possible to manufacture as many small-area first chips as possible on the wafer, reducing the cost of a single first chip, thereby reducing the overall manufacturing cost. In addition, the first chip is not bonded to the second chip in the manner of a wafer, but a single chip is placed in the first groove of the carrier unit, and the first chip and the second chip can be stacked before the first chip and the second chip are stacked. The first wafer and the second wafer are tested to screen out wafers with good performance and remove the wafers with poor performance to improve the overall chip yield and further reduce the overall manufacturing cost. In addition, unlike the wafer-level bonding method, the solution in this application stacks a single second wafer with the first wafer in the carrier unit, and does not need to align all the chips on the two stacked wafers. Therefore, the complexity of the process can be reduced, and the manufacturing efficiency of the chip can be improved.

In a possible implementation, the surface area of the second wafer is smaller than the surface area of the carrier unit.

In a possible implementation manner, the chip further includes: a specific pad disposed above the rewiring layer, the specific pad is electrically connected to the first chip through the rewiring layer; the specific pad is used to pass through The lead is connected to the circuit board in the device where the chip is located.

In a possible implementation manner, the specific pad is located outside the projection of the second wafer in the vertical direction.

In a possible implementation, the stacked chip is an image sensor chip; the second chip is a pixel chip, and the pixel chip includes a pixel array for receiving optical signals and converting them into electrical signals; the first chip It is a logic chip that includes a signal processing circuit for processing the electrical signal.

In a possible implementation, the second wafer further includes a substrate, a first dielectric layer, and a second metal circuit layer; the pixel array is formed in the substrate, and the first dielectric layer is disposed on the substrate. On the surface, the second metal circuit layer is formed in the first dielectric layer; the second metal circuit layer is electrically connected to the pixel array, and the second pad is provided in the second metal circuit layer.

In a possible implementation manner, the second pad is disposed outside the projection of the pixel array on the plane where the second metal circuit layer is located, and the first pad is located directly above the second pad.

In a possible implementation manner, the second wafer has a back-illuminated structure, the pixel array is close to the lower surface of the substrate, and the first dielectric layer is disposed on the lower surface of the substrate.

In a possible implementation manner, an opening is provided between the second metal circuit layer and the lower surface of the first dielectric layer to form the second pad in the second metal circuit layer.

In a possible implementation manner, the second wafer further includes a second dielectric layer, the second dielectric layer is disposed on a non-opening area on the lower surface of the first dielectric layer, and the second metal circuit layer is connected to the first dielectric layer. An opening is arranged between the lower surfaces of the dielectric layer to form the second pad in the second metal circuit layer.

In a possible implementation manner, the second wafer further includes a second dielectric layer covering the lower surface of the first dielectric layer, and the second metal circuit layer and the lower surface of the second dielectric layer An opening is arranged therebetween to form the second pad in the second metal circuit layer.

In a possible implementation manner, the second wafer has a front-illuminated structure, the pixel array is close to the upper surface of the substrate, and the first dielectric layer is disposed on the upper surface of the substrate; the second metal circuit An opening is provided between the layer and the lower surface of the substrate to form the second pad.

In a possible implementation manner, an underlying bump metallization layer or a through-hole interconnection structure is provided under the second pad, and an underlying bump metallization layer or the through-hole interconnection structure is provided under Solder balls.

In a possible implementation manner, the second wafer further includes: an optical component disposed above the pixel array, and the optical component includes a filter layer and/or a microlens array.

In a possible implementation manner, the second wafer further includes a transparent cover plate disposed above the optical element, wherein there is air or a transparent medium layer between the transparent cover plate and the optical element.

In a possible implementation manner, the chip further includes: a third dielectric layer and a fourth dielectric layer. The third dielectric layer is disposed between the rewiring layer and the carrier unit for forming a conductive channel to connect the rewiring layer. The wiring layer and the first metal circuit layer of the first chip; the fourth dielectric layer is disposed between the first pad and the rewiring layer, and is used to form a conductive channel to connect the rewiring layer and the first pad .

In a possible implementation, the chip further includes a first thermally conductive metal layer, the first thermally conductive metal layer is disposed on the upper surface of the fourth dielectric layer, and the first thermally conductive metal layer and the first pad are located on the same Horizontal surface.

In a possible implementation manner, if the first accommodating structure is a groove, the chip further includes: a second thermally conductive metal layer disposed on the bottom of the first accommodating structure, and the first wafer is disposed on the first accommodating structure. On the two heat-conducting metal layers, the second heat-conducting metal layer is connected to the lower surface of the carrier unit through at least one heat-conducting metal structure.

In a possible implementation, a third thermally conductive metal layer is further provided on the lower surface of the carrier unit, and the third thermally conductive metal layer is connected to the at least one thermally conductive metal structure.

In a possible implementation manner, a second accommodating structure is further provided in the carrier unit, and the second accommodating structure is a groove or a through hole; the chip further includes: a third wafer disposed in the second container The second chip is stacked above the carrier unit, the first chip and the third chip, the second chip is electrically connected to the first pad through a second pad on its lower surface, and The surface area of the second wafer is greater than the sum of the surface areas of the first wafer and the third wafer.

In a possible implementation manner, the rewiring layer is disposed above the first wafer and the third wafer, and the third wafer is electrically connected to the first wafer through the rewiring layer.

In a possible embodiment, the chip further includes a third pad disposed above the rewiring layer, and the third pad is electrically connected to the third chip through the rewiring layer; the second chip further includes The fourth pad is electrically connected to the third pad.

In a possible implementation manner, the third chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for storing electrical signals generated by the first chip and/or the second chip.

In a possible implementation manner, the third wafer is a dummy chip, which is used to balance mechanical stress during the processing of the chip.

In a possible implementation manner, the carrier unit is any one of a substrate, a molding compound, and a packaging substrate, wherein the material of the substrate is any one of silicon, glass, and ceramic.

In a second aspect, a method for manufacturing a stacked chip is provided, which includes: dividing a plurality of first chips from a first wafer; packaging the plurality of first chips in a carrier, and A rewiring layer is prepared above; a first pad is prepared above the rewiring layer, and the first pad is electrically connected to the first target chip through the rewiring layer; a plurality of second chips are prepared on a second wafer, The second target chip of the plurality of second chips is divided from the second wafer, the second target chip includes a second pad; the second target chip is stacked on the first target chip, and soldered The first bonding pad and the second bonding pad are electrically connected to the first target chip and the second target chip; the electrically connected whole of the first target chip and the second target chip are cut to obtain A stacked chip, wherein the surface area of the second target wafer is greater than the surface area of the first target wafer.

In a possible implementation, the manufacturing method further includes: preparing a specific pad above the rewiring layer, and the specific pad is electrically connected to the first target wafer through the rewiring layer; and the specific pad is used for It is connected to the circuit board in the device where the chip is located through the lead.

In a possible embodiment, the carrier is a substrate wafer, and packaging the plurality of first chips in the carrier includes: fabricating a plurality of first accommodating structures on the substrate wafer, the first The accommodating structure is a groove or a through hole; the plurality of first chips are fixed in the plurality of first accommodating structures, and the upper surface of the plurality of first chips is not higher than the upper surface of the substrate wafer; The rewiring layer is prepared above the substrate wafer on which the plurality of first wafers are fixed.

In a possible embodiment, the carrier is a plastic encapsulant, and encapsulating the plurality of first chips in the carrier includes: encapsulating the plurality of first chips in the plastic encapsulant, wherein the plurality of first chips The upper surface of a chip is in contact with air, and the upper surface of the plurality of first chips is not higher than the upper surface of the plastic compound; the rewiring layer is prepared on the plastic compound that encapsulates the plurality of first chips.

In a possible implementation manner, the carrier is a packaging substrate, and packaging the plurality of first chips in the carrier includes: packaging the plurality of first chips inside the packaging substrate; preparing in the packaging substrate The rewiring layer, wherein the rewiring layer includes a plurality of horizontally arranged metal circuit layers and a plurality of vertically arranged interconnection structures.

In a possible implementation, the stacked chip is an image sensor chip, the second target wafer is a pixel wafer, and the second target wafer includes a pixel array for receiving optical signals and converting them into electrical signals; A target chip is a logic chip, and the first target chip includes a signal processing circuit for processing the electrical signal.

In a possible implementation manner, the preparing a second target wafer on the second wafer includes: preparing a pixel array of the second target wafer in the second wafer, and placing the pixel array on the second wafer on the surface of the second wafer. Preparing a first dielectric layer and a second metal wiring layer, wherein the second metal wiring layer is formed in the first dielectric layer, and the second metal wiring layer is electrically connected to the pixel array; preparing the second pad, The second pad is formed in the second metal circuit layer; an electrical connection device is prepared under the second pad.

In a possible implementation, the second pad is formed outside the projection of the pixel array in its vertical direction.

In a possible embodiment, the second target wafer has a back-illuminated structure, the pixel array of the second target wafer is prepared in the second wafer, and the first wafer is prepared on the surface of the second wafer. The dielectric layer and the second metal circuit layer include: preparing the pixel array on the lower part of the second wafer, the pixel array being close to the lower surface of the second wafer; preparing the second wafer on the lower surface of the second wafer A dielectric layer and the second metal circuit layer.

In a possible implementation manner, the method further includes: bonding the second wafer to the substrate wafer by using a wafer bonding process; and thinning the upper surface of the second wafer , Wherein the pixel array is close to the upper surface of the second wafer after the thinning process.

In a possible implementation manner, the method further includes: disposing a transparent cover plate as a supporting structure above the pixel array, and performing a thinning process on the lower surface of the substrate wafer until the second metal circuit layer is close to The bottom surface of the substrate wafer.

In a possible implementation, the preparation of the second pad includes: performing an etching process on the lower surface of the substrate wafer to form an opening, and the opening is connected to the second metal circuit layer to form an opening in the second metal circuit layer. The second pad is formed in the second metal circuit layer.

In a possible implementation manner, the method further includes: arranging a transparent cover plate as a supporting structure above the pixel array, and performing a thinning process on the lower surface of the substrate wafer to completely remove the substrate wafer.

In a possible implementation manner, the preparing the second pad includes: performing an etching treatment on the lower surface of the first dielectric layer to form an opening, and the opening is connected to the second metal circuit layer to form an opening in the second metal circuit layer. The second pad is formed in the second metal circuit layer.

In a possible embodiment, the second target wafer has a front-illuminated structure, the pixel array of the second target wafer is prepared in the second wafer, and the first medium is prepared on the surface of the second wafer Layer and the second metal circuit layer, including: preparing the pixel array on the upper part of the second wafer, the pixel array being close to the upper surface of the second wafer; preparing the first pixel array on the upper surface of the second wafer A dielectric layer and the second metal circuit layer.

In a possible implementation manner, the preparing the second pad includes: performing an etching treatment on the lower surface of the second wafer to form an opening, and the opening is connected to the second metal circuit layer to form an opening in the second metal circuit layer. The second pad is formed in the second metal circuit layer.

In a possible implementation manner, preparing an electrical connection device under the second pad includes: preparing an under-bump metallization layer or a via interconnection structure under the second pad, and Solder balls are prepared under the metallization layer or the through-hole connection structure.

In a possible implementation manner, after preparing the pixel array of the second target wafer in the second wafer, the method further includes: preparing an optical component over the pixel array, the optical component including: a filter layer And/or micro lens array.

In a possible implementation manner, the manufacturing method further includes: dividing a plurality of third chips from the third wafer; packaging the plurality of third chips and the plurality of first chips in the carrier, The rewiring layer is electrically connected to a third target wafer among the plurality of third wafers; the whole of the first target wafer, the second target wafer, and the third target wafer is cut to obtain a stacked chip; Wherein, the surface area of the second target wafer is greater than the sum of the surface areas of the first target wafer and the third target wafer.

In a possible implementation manner, the third wafer is electrically connected to the first wafer through the rewiring layer.

In a possible implementation manner, the manufacturing method further includes: preparing a third pad above the rewiring layer, and the third pad is electrically connected to the third target chip through the rewiring layer; and soldering the third pad. The bonding pad and the fourth bonding pad of the second chip are electrically connected to the third target chip and the second target chip.

In a possible implementation, the third target chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for storing electricity generated by the first target chip and/or the second target chip. Signal.

In a possible implementation manner, the third target wafer is a dummy chip, which is used to balance mechanical stress during the processing of the chip.

In a third aspect, an image sensor is provided, including: a stacked chip as in the first aspect or any possible implementation of the first aspect.

In a fourth aspect, an electronic device is provided, including: a stacked chip as in the first aspect or any possible implementation of the first aspect.

By providing the above-mentioned stacked chips in the image sensor or the electronic device, the manufacturing cost of the chip is reduced, thereby reducing the overall manufacturing cost of the image sensor or the electronic device.

Description of the drawings

1 to 3 are schematic structural diagrams of three complementary metal oxide semiconductor image sensor chips according to embodiments of the present application.

FIG. 4 is a schematic distribution diagram of a plurality of pixel chips on a pixel wafer according to an embodiment of the present application.

FIG. 5 is a schematic distribution diagram of a plurality of logic chips on a logic wafer according to an embodiment of the present application.

FIG. 6 is a schematic diagram of the split structure of a stacked chip according to an embodiment of the present application.

7 to 9 are three schematic cross-sectional views of the carrier unit, the first wafer, and the rewiring layer according to an embodiment of the present application.

FIG. 10 is a schematic top view of a second wafer according to an embodiment of the present application.

11 to 14 are four schematic cross-sectional views of a second wafer according to an embodiment of the present application.

15 to 18 are other four cross-sectional schematic diagrams of the carrier unit, the first wafer, and the rewiring layer according to the embodiments of the present application.

FIG. 19 is a schematic structural diagram of a stacked chip according to an embodiment of the present application.

FIG. 20 is a schematic diagram of the split structure of another stacked chip according to an embodiment of the present application.

Figures 21 to 23 are other three cross-sectional schematic diagrams of the carrier unit, the first wafer, and the rewiring layer according to the embodiments of the present application.

FIG. 24 is a schematic structural diagram of another stacked chip according to an embodiment of the present application.

FIG. 25 is a schematic flow chart of a method for manufacturing a stacked chip according to an embodiment of the present application.

FIG. 26 is a schematic flow chart of another method for manufacturing a stacked chip according to an embodiment of the present application.

27 to 32 are partial cross-sectional views of a wafer after multiple process steps according to an embodiment of the present application.

FIG. 33 is a schematic flow chart of another method for manufacturing a stacked chip according to an embodiment of the present application.

34 to 37 are partial cross-sectional views of a wafer after multiple process steps according to an embodiment of the present application.

FIG. 38 is a schematic flowchart of another method for manufacturing a stacked chip according to an embodiment of the present application.

FIG. 39 is a schematic flow chart of another method for manufacturing a stacked chip according to an embodiment of the present application.

Fig. 40 is a schematic structural block diagram of an image sensor implemented according to the present application.

Fig. 41 is a schematic structural block diagram of an electronic device implemented according to the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

It should be understood that the specific examples in this document are only intended to help those skilled in the art to better understand the embodiments of the present application, rather than limiting the scope of the embodiments of the present application.

It should also be understood that, in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not correspond to the embodiments of the present application. The implementation process constitutes any limitation.

It should also be understood that the various implementation manners described in this specification can be implemented individually or in combination, which is not limited in the embodiments of the present application.

The technical solutions of the embodiments of the present application can be applied to various chips, such as memory chips, processing chips, sensor chips, etc., which are not limited in the embodiments of the present application.

Optionally, the technical solution of the embodiment of the present application can be applied to various image sensor chips, such as a biometric image sensor or an image sensor in a photographing device, but the embodiment of the present application is not limited thereto.

As a common application scenario, the chip provided in the embodiments of the present application can be used in mobile terminals such as smart phones, cameras, and tablet computers, or in other electronic devices such as servers and supercomputers.

Figures 1 to 3 show schematic structural diagrams of three complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensor chips 10, which are sensor chips that can convert optical images into digital signals , Widely used in various fields such as digital products, mobile terminals, security monitoring and scientific research industry. As a common application scenario, the image sensor chip 10 provided in the embodiment of the present application can be applied to a photographing device of an electronic device, for example, a front or rear camera of a mobile phone.

FIG. 1 shows a schematic structural diagram of a conventional image sensor chip 10. As shown in FIG. 1, the image sensor chip 10 is manufactured on a single wafer 100. The image sensor 10 on the wafer 100 can be roughly divided into two areas: a pixel array area 110 and a processing circuit area 120. Wherein, the pixel array area 110 includes a pixel array composed of a plurality of CMOS pixel units for receiving light signals and converting the light signals into corresponding electrical signals. The total number of pixels in the pixel array area 110 of the image sensor 10 is one of the main technical indicators for measuring the image sensor, which determines the photosensitive performance, resolution and other factors of the image sensor. Therefore, it generally occupies a larger area and is optional. Ground, the pixel array area 110 occupies more than 70% of the area of the entire wafer 100. In the pixel array area 110, each pixel unit is composed of a photo-diode (PD) and one or more CMOS switch tubes. Therefore, the pixel array area 110 has fewer device types, relatively simple circuit structure, and device process requirements. Relatively low, for example, the 65nm process can meet the design requirements of the pixel array area.

In addition, the processing circuit area 120 may include a control circuit for controlling the pixel array, a signal processing circuit for processing electrical signals generated by the pixel array, an analog-to-digital conversion circuit, a digital processing circuit and other functional circuits for working with the pixel array to generate digital images. Signal. The processing circuit area 120 occupies a small area on the entire wafer 100, but in these functional circuits, such as digital processing circuits, due to the need to implement more complex functions, the circuit structure is relatively complex, the device types are many and the integration is high, so Process requirements are relatively high. For example, processes of 45nm and below are required to meet the design requirements of functional circuits, and the processing costs of these processes are higher.

FIG. 2 shows a schematic structural diagram of a stacked image sensor chip 10. As shown in FIG. 2, the image sensor chip 10 is formed by stacking two upper and lower wafers, and the pixel array area 110 is located on the first wafer 101 for acquiring optical signals and converting them into electrical signals. The second wafer 102 contains a processing circuit area 120 composed of a large number of analog and digital circuits, including a signal processing circuit and a control circuit, the signal processing circuit is used to process electrical signals, and the control circuit is used to control the pixel array Pixel work. Optionally, the first chip 101 may be called a pixel die, and the corresponding wafer may be called a pixel wafer; and the second chip 102 may be called a logic die. The corresponding wafer is called logic wafer (Logic Wafer) or image signal processing wafer (Image Signal Processing Wafer, ISP Wafer). Among them, the shape and size of the pixel chip and the logic chip are exactly the same. During the stacking process, the pixel chip and the logic chip are completely overlapped in the vertical direction.

FIG. 3 shows a schematic structural diagram of another stacked image sensor chip 10. As shown in FIG. 3, the image sensor chip 10 is formed by stacking three layers of wafers, and from top to bottom are the pixel wafer 101, the memory wafer 103, and the logic wafer 102, respectively. The shapes and sizes of the three types of wafers are completely the same. During the stacking process, the pixel wafer 101, the logic wafer 102, and the memory wafer 103 completely overlap in the vertical direction. The memory chip 103 includes a storage circuit 130 for storing electrical signals generated by the pixel array and/or processing circuit. Optionally, the circuit structure of the memory circuit is relatively complicated, the integration is high, and the line width and line spacing are small. Therefore, a higher process is also required for manufacturing.

Optionally, the storage circuit may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) circuit. It should be understood that the storage circuit may also be other types of storage circuits, such as other random access memory (RAM) circuit or read only memory (ROM) circuit, which is not done in the embodiment of the application. Any restrictions.

Compared with the non-stacked structure in Figure 1, the stacked image sensor in Figures 2 and 3 has three advantages: First, the pixel array area and the processing circuit area will not occupy each other's space, so more can be placed Pixels, improve the photosensitive performance, resolution and so on of the image sensor. The second is that logic wafers can be made with more advanced process nodes, which will increase transistor density and computing power, so that stacked image sensor chips can provide more functions, such as hardware high dynamic range imaging (High Dynamic Range Imaging). , HDR), slow motion shooting, etc. The third is that the storage function can be integrated in the image sensor to achieve faster data reading speed. Therefore, stacked image sensors currently dominate high-end image sensors.

With reference to Figures 1 to 3 above, taking the traditional non-stacked image sensor chip and the stacked image sensor chip as an example, the structure and performance differences between the two are compared. It should be understood that chips in other fields, such as memory chips, The processor chip, etc. can also adopt the traditional non-stacked structure and the stacked structure. Compared with the non-stacked structure, the memory chips and processor chips that adopt the stacked structure also have their own advantages, such as more Large storage space, faster processing speed and smaller size, etc.

However, at present, when two layers of wafers are stacked together in a wafer-to-wafer (W2W) manner through a wafer-level bonding process, multiple dies on the two-layer wafers correspond one-to-one , And the size of the corresponding wafers in the two layers of wafers is the same. This method is used to facilitate the process of wafer alignment, and the bonding accuracy is high. However, when the structure and function of the circuits on the two layers of wafers are different, the areas of the circuits grown on the corresponding two wafers of the same area are different, so that the area of one layer of the wafers in the two layers of wafers is not fully utilized. , Increased manufacturing costs. In addition, in the wafer bonding process, a bad chip on one wafer may be forcibly bonded to a good chip on another wafer, which affects the yield rate and also causes an increase in manufacturing costs.

For example, as shown in FIG. 4, a plurality of pixel wafers 101 are prepared on the pixel wafer 11, and each pixel wafer includes a pixel array area 110, and most of the area in the pixel wafer 101 is occupied by the pixel array area 110. As shown in FIG. 5, the shape and size of the logic wafer 12 and the pixel wafer 11 are exactly the same, and a plurality of logic wafers 102 are prepared on the logic wafer 12. The plurality of logic wafers 102 have the same size and correspond to the plurality of pixel wafers 101 one-to-one. When the pixel wafer 11 and the logic wafer 12 are bonded at the wafer level, alignment is performed by markings around the wafer, and the pixel wafer 11 is stacked on the logic wafer 12, and the two are completely overlapped in the vertical direction. Each pixel wafer in the pixel wafer 11 is aligned with a logic wafer in the logic wafer 12, so that one pixel wafer is aligned and bonded Above a logic chip. Each logic chip 102 includes a processing circuit area 120. Only a part of the area of the logic chip 102 is occupied by the processing circuit area 120. Therefore, part of the space on the logic wafer 102 is wasted. In addition, partially failed or faulty chips on the pixel wafer 11 and the logic wafer 12 may be forcibly bonded to a good chip, resulting in chip failure after bonding and affecting the overall yield.

Similarly, if the stacked image sensor chip includes a memory chip, the wafer corresponding to the memory chip is a memory wafer, and the distribution of the chips on the memory wafer is similar to the distribution of the logic chips on the logic wafer 12 in FIG. The shape and size of the wafer, the pixel wafer and the logic wafer are exactly the same. When the wafer is bonded, the memory wafer is stacked on top of the logic wafer, and the pixel wafer is stacked on top of the memory wafer. The three are in the vertical direction. They are completely overlapped, and one pixel chip in the pixel wafer, one memory chip in the memory wafer, and one logic chip in the logic wafer are in one-to-one correspondence. Only part of the memory chip area is also occupied by the storage circuit, causing some space on the memory wafer to be wasted. The failure of the memory chip after forced bonding affects the overall yield, and the bonding of the three-layer wafer will also increase manufacturing Cost. For example, in the prior art, three layers of wafers with the same area are usually stacked through two wafer-level bonding, which will increase the process of bonding once, which will further increase the manufacturing process and manufacturing cost of the chip.

Based on the above-mentioned problems, this application proposes a stacked chip structure. By making full use of the size of the wafer, more chips are prepared, and the chips of different sizes are electrically connected, so as to achieve stacked chips while reducing the number of chips. The cost of each chip, thereby reducing the overall manufacturing cost of stacked chips.

FIG. 6 shows a schematic diagram of the split structure of a stacked chip according to an embodiment of the present application.

As shown in FIG. 6, the stacked chip 20 includes:

The carrier unit 200 is provided with a first accommodating structure 201, and the first accommodating structure is a groove or a through hole;

The first chip 210 is disposed in the first accommodating structure 201;

The second wafer 220 is stacked above the first wafer 210 and the carrier unit 200, and the surface area of the second wafer 220 is larger than the surface area of the first wafer 210.

Specifically, the first wafer 210 and the second wafer 220 have a sheet-like structure, and therefore, have a small thickness. The surface area of the first wafer 210 is the upper surface area or the lower surface area of the first wafer 210. Generally, the upper surface area and the lower surface area of the first wafer 210 are equal. Similarly, the surface area of the second wafer 220 is also the upper surface area or the lower surface area of the first wafer 210.

Since the surface area of the second wafer 220 is larger than the surface area of the first wafer 210, when the second wafer 220 needs to be stacked on the first wafer 210, a supporting structure is required. The carrier unit 200 is provided with a first accommodating structure 201 to accommodate the first wafer 210 and provide support for the first wafer 210 and the second wafer 220. Therefore, when the second wafer 220 is stacked on top of the first wafer 210, the second wafer 220 is also stacked above the carrier unit 200.

Optionally, in the embodiment of the present application, the carrier unit 200 is any one of a substrate, a molding compound, a molding substrate, and a circuit board, and the thickness of the carrier unit 200 is greater than that of the first wafer 210 described above.

Optionally, the first wafer 210 may be completely located inside the carrier unit 200, and the upper surface of the first wafer 210 is not higher than the upper surface of the carrier unit 200.

Specifically, if the first accommodating structure 201 is a groove, in one embodiment, the first accommodating structure 201 may be located inside the carrier unit 200, that is, the groove and the first wafer 210 are completely disposed in the carrier unit 200 In the interior, the first wafer 210 is lower than the upper surface of the carrier unit 200. In another embodiment, the first accommodating structure 201 may also be located on the upper surface of the carrier unit 200. In this case, the upper surface of the first wafer 210 and the upper surface of the carrier unit 200 may be on the same level. Of course, If the height of the first accommodating structure 201 is greater than the thickness of the first wafer 210, the upper surface of the first wafer 210 may also be lower than that of the carrier unit 200.

If the first accommodating structure 201 is a through hole, the first chip 210 is disposed in the through hole, and the four sides of the first chip 210 are fixedly connected to the walls of the through hole. Optionally, if the carrier unit 200 is a plastic package material , The first chip 210 is directly fixed in the through hole of the carrier unit 200. If the carrier unit 200 is a plastic package substrate, a circuit board or a substrate, the first chip 210 can be fixedly connected to the through hole by an adhesive layer or other fixing devices. middle. Optionally, at this time, the upper surface of the first wafer 210 is not higher than the upper surface of the carrier unit 200, and the lower surface of the first wafer 210 is not lower than the lower surface of the carrier unit 200.

When the first accommodating structure 201 is a through hole, the lower surface of the first wafer 210 is in contact with the air, which is beneficial to the heat dissipation of the first wafer 210, and can improve the reliability and reliability of the first wafer 210 and the entire stacked chip 20. Overall performance.

Hereinafter, taking the first accommodating structure 201 as a groove as an example to illustrate the overall structure of the stacked chip 20, unless otherwise specified, the case where the first accommodating structure 201 is a through hole can be referred to the following description. Hereinafter, if the first accommodating structure 201 is a groove, the first accommodating structure 201 is also written as the first groove 201, and if the first accommodating structure 201 is a through hole, the first accommodating structure 201 is also written It is the first through hole 201.

Optionally, the shape and size of the first groove 201 or the first through hole 201 in the carrier unit 200 may be the same as or slightly larger than the shape and size of the first wafer 210, wherein the first through hole 201 may be It is a square through hole, and the first groove 201 may be a square groove. In other words, the cross-sectional area of the first groove 201 in the carrier unit 200 may be the same as or slightly larger than the surface area of the first wafer 210. For example, the first wafer 210 has a sheet structure, the depth of the first groove 201 is the same as the thickness of the first wafer 210 or slightly larger than the thickness of the first wafer 210, and the length and width of the first groove 201 are also It is slightly larger than the length and width of the first wafer 210, so that the first groove 201 can completely accommodate the first wafer 210 therein. Optionally, the length, width, and depth of the first groove 201 are respectively larger than the length, width, and height of the first wafer 210 by 25 μm, or any other value, which is not limited in the embodiment of the present application.

In the embodiment of the present application, the surface area of the first chip 210 is smaller than the surface area of the second chip 220, and it is impossible to directly connect the Input Output (IO) port of the first chip 210 with the IO port of the second chip 220. For connection, the IO ports of the first chip 210 need to be fan-out packaged, or the IO ports of the first chip 210 need to be rearranged by other technical means.

Optionally, a re-distribution layer (RDL) 214 is provided above the first chip 210, and the re-distribution layer 214 is used to connect the input and output ports of the first chip 210 and perform processing on the IO ports of the first chip 210. Re-layout can improve the reliability of interconnection between chips.

7 to 9 show three schematic cross-sectional views of the carrier unit 200, the first wafer 210, and the rewiring layer 214.

As shown in FIG. 7, the carrier unit 200 may be a substrate where a first groove 201 (not shown in the figure) is provided in the substrate, and the first wafer 210 is provided in the first groove 201. The first wafer 210 is at the bottom of the first groove 201 through the first adhesive layer 211 to stably fix the first wafer 210 in the first groove 201. The adhesive layer includes but is not limited to die attach film (DAF).

Optionally, in one embodiment, when the thickness of the first adhesive layer 211 is d1 and the height of the first wafer 210 is d2, the sum of the thicknesses of the first wafer 210 and the first adhesive layer 211 d1+d2 is less than It is equal to the depth d0 of the first groove 201, in other words, the upper surface of the first wafer 210 is not higher than the upper surface of the carrier unit. Optionally, the difference between d1+d2 and d0 may be between 2 μm and 5 μm, or may be other values, which is not limited in the embodiment of the present application.

Of course, in addition to the foregoing embodiments, the upper surface of the first wafer 210 may also be higher than the upper surface of the carrier unit, which is not limited in the embodiment of the present application.

Optionally, the gap between the first wafer 210 and the first groove 201 may be filled with a dielectric layer 212 to further stably fix the first wafer 210 in the first groove 201. The dielectric layer 212 includes, but is not limited to, a polymer organic material, such as a dry film (Dry Film) material or other polymer material with good fluidity, or an inorganic material filled by a CVD process or a coating process, such as silicon oxide. , Silicon glass and so on. In the embodiment of the present application, the dielectric layer 212 can be a dry film material that can be photoetched, and can be filled between the first wafer 210 and the first groove 201 without voids under vacuum and heating conditions, and Using a photolithographic material as the dielectric layer, while filling and fixing the gap between the first groove and the first wafer, it can also facilitate the process and save the manufacturing time of the chip.

Optionally, as shown in FIG. 7, the first wafer 210 includes a first metal circuit layer 213, and the first metal circuit layer 213 is located on the surface of the first wafer 210, specifically the IO port of the first wafer 210, for It is electrically connected with other electrical components, for example, with the second wafer 220. In addition, the above-mentioned dielectric layer 212 may also cover the upper surface of the carrier unit 200 and a part of the upper surface of the first wafer 210 except for the first metal circuit layer 213.

In the embodiment of the present application, the substrate may be silicon, glass, ceramic or any other material, which is not limited in the embodiment of the present application. In a possible implementation, the carrier unit 200 is monocrystalline silicon.

As shown in FIG. 8, the carrier unit 200 may be a plastic molding compound, and it may specifically be an epoxy molding compound (EMC). Of course, the molding compound may also be other conventional chip packaging materials. For organic or inorganic materials, the embodiments of the present application do not specifically limit this.

In the embodiment of the present application, the first wafer 210 is wrapped and fixed by a plastic molding compound, and no additional filling material or glue layer is required to fix the first wafer 210. Optionally, in some embodiments, the upper surface of the first wafer 210 is not wrapped by molding compound, and the other five planes are covered by molding compound. In other embodiments, the upper surface and the lower surface of the first wafer 210 are not wrapped by the molding compound, and the remaining four surfaces are wrapped by the molding compound.

As shown in FIGS. 7 and 8, the rewiring layer 214 is disposed above the carrier unit 200 and the first wafer 210. The rewiring layer 214 includes a metal wiring layer, which is connected to the first metal circuit on the surface of the first wafer 210. The layer 213 is in contact to form an electrical connection between the two. Generally speaking, the rewiring layer usually includes a metal wiring layer and an insulating dielectric layer above or below the metal wiring layer. In FIG. 7 and FIG. 8 of the embodiment of the present application, only the rewiring layer 214 is shown. It should be understood that an insulating dielectric layer may be further provided above or below the metal wiring layer.

It should also be understood that FIG. 7 and FIG. 8 only show the case where the rewiring layer 214 includes only one metal wiring layer, and the rewiring layer 214 of the stacked chip may also include multiple metal wiring layers. If the rewiring layer 214 includes multiple metal wiring layers, an insulating dielectric layer is formed between the multiple metal wiring layers, and the multiple metal wiring layers can form electrical connections with each other. The metal wiring layer located at the bottom of, may be the same as the metal wiring layer in the rewiring layer 214 in FIG. 7.

As shown in FIG. 9, the carrier unit 200 may also be a circuit board, which is made of an insulating material, and is provided with multiple metal layers. The multiple metal layers may be copper metal or other metal materials for conducting electricity. Signals, the multi-layer metal layers can be connected through an interconnection structure to realize electrical signal transmission between the multi-layer metal layers.

In the embodiment of the present application, the first chip 210 may be completely disposed inside the circuit board, and its six surfaces are all wrapped by the insulating material of the circuit board, and at least one metal layer is connected to the IO port of the first chip 210 through the interconnection structure. (The first metal circuit layer) to realize the re-layout of the IO ports of the first chip 210.

Since the multi-layer metal layer and interconnection structure in the circuit board realize the function of the IO port re-layout of the first chip 210, in the embodiment of the present application, the multi-layer metal layer and the interconnection structure in the circuit board are also referred to as为Rewiring layer 214. The difference from the rewiring layer in Figures 7 and 8 is that the rewiring layer in Figure 9 is formed in the carrier unit, that is, the inside of the circuit board, while the rewiring layer in Figures 7 and 8 is formed in the carrier unit, that is, the liner. The bottom or the upper surface of the molding compound is formed.

Optionally, the carrier unit 200 may be a printed circuit board (Printed Circuit Board, PCB) or a package substrate (Package Substrate, SUB), and the embodiment of the present application does not specifically limit the type of the circuit board or the package substrate.

It should be understood that the foregoing FIGS. 7 to 9 only exemplarily show several schematic diagrams of re-layouting the ports of the first wafer 210 through the rewiring layer 214, and those skilled in the art can also use any of the existing technologies. The chip port may be re-layouted in a packaging manner, which is not specifically limited in the embodiment of the present application.

In the embodiment of the present application, the first accommodating structure in the carrier unit provides support and stability for the first wafer, so that a large-area second wafer can be stacked on a small-area first wafer, so that a stacked chip structure can be realized. At the same time, it is also possible to manufacture as many small-area first chips as possible on the wafer, reducing the cost of a single first chip, thereby reducing the overall manufacturing cost. In addition, the first chip is not bonded to the second chip in the manner of a wafer, but a single chip is placed in the first groove of the carrier unit, and the first chip and the second chip can be stacked before the first chip and the second chip are stacked. The first wafer and the second wafer are tested to screen out wafers with good performance and remove the wafers with poor performance to improve the overall chip yield and further reduce the overall manufacturing cost.

In the embodiment of the present application, different from the wafer-level bonding method, the solution of the embodiment of the present application stacks a single second chip with the first chip in the carrier unit, and there is no need to stack two stacked wafers. Aligning all the chips on the board can reduce the complexity of the process, thereby improving the manufacturing efficiency of the chips.

Optionally, the first wafer 210 and the second wafer 220 described above are used to implement different circuit functions. In a possible implementation manner, the stacked chip 20 is an image sensor chip, and the first wafer 210 may be The pixel chip 101 in FIG. 1 and the second chip 220 may be the logic chip 102 or the memory chip 103 in FIG. 1 described above. If the second chip 220 is a logic chip, the second chip includes a processing circuit area 120 composed of a large number of analog and digital circuits, including a signal processing circuit and a control circuit, and the signal processing circuit is used to process electrical signals , The control circuit is used to control the work of the pixels in the pixel array.

Optionally, if the stacked chip 20 is a processor chip, the first chip 210 may be a central processing unit (CPU) chip, and the second chip 220 may be a graphics processing unit (GPU) chip , Or other control processing wafers.

In another possible implementation, the stacked chip 20 may be a memory chip, where the first chip 210 is a logic chip, and the logic chip includes a processing circuit in the memory chip for controlling and processing signals. The second chip 220 is a storage chip and includes a storage circuit, which is used for data storage. Optionally, in the embodiment of the present application, a plurality of second chips may be stacked above the carrier unit 200 and the first chip 210, that is, logic Multiple storage wafers are stacked above the wafer to achieve a larger storage space for the storage chips.

It should be understood that the stacked chip 20 may also be chips in a variety of different fields, wherein the first chip and the second chip are functional chips that implement corresponding circuit functions, and the circuit functions of the first chip and the second chip are different.

Optionally, in the present application, the above-mentioned carrier unit 200 may be a unit partial area of a carrier, the carrier may be divided into a plurality of carrier units, and the carrier may be a substrate wafer, a molding compound or a circuit board, wherein the The carrier is provided with a plurality of first chips, and a rewiring layer is formed on or inside the carrier to re-layout the IO ports of the plurality of first chips.

Specifically, if the carrier is a substrate wafer, a plurality of first accommodating structures 201 are prepared on the substrate wafer by a process such as photolithography, and a plurality of first accommodating structures are placed one by one in the plurality of first accommodating structures. A chip; if the carrier is a plastic molding compound, the multiple first chips 210 are packaged simultaneously and wrapped in the plastic molding compound; if the carrier is a circuit board, the multiple first chips 210 are packaged in the circuit board.

The structure of the carrier unit 200, the first wafer 210, and the rewiring layer 214 in the stacked chip 20 in the present application is described above in conjunction with FIGS. 6-9. Below, in conjunction with the second wafer 220, the structure of the stacked chip 20 is further described. the whole frame.

Optionally, in one embodiment, the second wafer 220 is a single wafer after packaging, and the first wafer 210 is one of a plurality of wafers in the carrier. The second chip 220 may be stacked on the first chip 210 through a chip to wafer (C2W) stacking process.

Optionally, in another embodiment, the second wafer 220 is one of a plurality of wafers in the second wafer, and the first wafer 210 is one of a plurality of wafers in the substrate wafer. The second chip 220 may be stacked on the first chip 210 through a wafer-to-wafer (W2W) stacking process.

In this application, the structure of the stacked chip 20 under the C2W stacking process in the first embodiment is mainly introduced.

Optionally, in the embodiment of the present application, the first wafer 210 and the second wafer 220 in the stacked chip 20 are electrically connected through pads, that is, in the C2W stacking process, a plurality of first wafers 210 on the carrier pass through The rewiring layer forms new pads. The second wafer 220 also has pads. The first wafer 210 and the second wafer 220 are electrically connected to each other through the connection pads.

FIG. 10 shows a top view of the second wafer 220. Wherein, the second wafer is a pixel wafer in the image sensor chip.

As shown in FIG. 10, the second wafer 220 includes a pixel array and a peripheral circuit. The pixel array includes a plurality of pixel units for receiving light signals and performing optical imaging. The plurality of pixel units may be pixel units fabricated by using CMOS technology, which may include photodiodes (Photodiodes), metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) and other devices.

Peripheral circuits include: analog-to-digital conversion circuit, signal processing circuit 130, digital processing circuit, logic control circuit and so on. Among them, after the pixel array receives the optical signal and converts the optical signal into an electrical signal, the electrical signal is sent to the signal processing circuit and the analog-to-digital conversion circuit, the digital signal is obtained after the analog-to-digital conversion circuit is processed, and the digital signal is sent to the digital processing The circuit performs digital signal processing to obtain the image signal. The logic control circuit provides timing and other various control signals to the above-mentioned pixel array, analog-to-digital conversion circuit, signal processing circuit and digital processing circuit.

In addition, as shown in FIG. 10, the peripheral circuit area also includes a plurality of pads, the plurality of pads are the IO ports of the second chip 220, which are used to transmit the image signals generated by the second chip 220 to other electrical components. . In order to facilitate the distinction between the pads in the second wafer 220 and the pads in the first wafer 210, in this application, the pads in the first wafer 210 are also written as the first pads, and the pads in the second wafer 220 The pad is written as the second pad.

FIG. 11 shows a schematic cross-sectional view of the second wafer 220 described above.

As shown in FIG. 11, the second wafer 220 includes a pixel array and a second metal circuit layer 222, wherein the pixel array includes a plurality of pixel units 221. The plurality of pixel units 221 are located above the second metal circuit layer 222, and the second chip 220 has a backside illuminated (BSI) complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) structure. In the second wafer of the BSI structure, the intensity of the light signal received by the plurality of pixel units 221 is high, so the optical image formed is better.

The second metal circuit layer 222 is a circuit layer of the second chip 220 that connects the plurality of pixel units 221 and peripheral circuits. FIG. 11 only shows a second metal circuit layer 222. It should be understood that the second metal circuit layer may also It is a multilayer, which is not limited in the embodiment of the present application.

Optionally, the second metal circuit layer 222 may be formed in the first dielectric layer 2201, the first dielectric layer 2201 is disposed around the second metal circuit layer 222, and the first dielectric layer 2201 is an insulating medium, for example, Silicon, ceramics, glass, or other organic materials, etc.

In one embodiment, the first dielectric layer 2201 connects the pixel array and the second metal circuit layer 222. Wherein, the pixel array may be formed in a substrate, and the first dielectric layer 2201 is connected to the substrate.

Optionally, the second pads 2221 of the second chip 220 are formed in the second metal circuit layer 222, specifically, are formed in the surrounding area of the second metal circuit layer 222, in other words, are formed in the second chip in FIG. 220 in the area of the peripheral circuit.

Specifically, an opening is formed in the first dielectric layer 2201, and the opening connects the lower surface of the first dielectric layer 2201 and the second metal circuit layer 222, and the partial area on the second metal circuit layer corresponding to the opening constitutes the first Two bonding pads 2221.

Optionally, a plurality of openings are formed in the first dielectric layer 2201, so that a plurality of second pads 2221 are formed on the second metal circuit layer.

Further, an Under Bump Metallization (UBM) layer 2222 is formed under the second pad 2221, and solder balls 2223 are formed on the UBM layer. The solder balls 2223 are used to interact with the first chip 210. A pad is soldered to achieve electrical connection.

Optionally, the UBM layer 2222 may be a multilayer metal film such as titanium, chromium, copper, gold, etc., to improve the adhesion of the solder balls 2223. Optionally, the solder ball 2223 may also be referred to as a bump. The material of the solder ball 2223 may be gold, tin-lead alloy, or copper-nickel-gold alloy, etc. The embodiment of the present application does not have any influence on the materials of the UBM layer and the solder ball. Make specific restrictions.

Optionally, as shown in FIG. 11, above the plurality of pixel units 221, a filter layer 227 and a microlens array 226 are further provided. Specifically, the filter layer 227 and the microlens array 226 are provided on the plurality of pixels. Right above the unit 221. Optionally, each microlens in the microlens array 226 corresponds to one pixel unit in the plurality of pixel units 221. The pixel unit 221 is used to receive the optical signal condensed by the microlens and processed by the filter layer 227, and perform optical imaging based on the optical signal.

Optionally, each microlens in the microlens array 226 is a round lens or a square lens, and its upper surface is a spherical or aspherical surface, and the focal point of each microlens can be located on its corresponding pixel unit.

Optionally, the filter layer 227 may be a color filter unit. For example, the filter layer 227 includes three color filter units for transmitting red light signals, blue light signals, and green light signals, respectively. One color filter unit corresponds to at least one micro lens and at least one pixel unit. Optionally, the filter layer 227 can also be a filter used to filter visible light and block non-visible light, which can reduce the interference of infrared bands in the environment to optical imaging. It should be understood that, in the embodiment of the present application, the filter wavelength band of the filter layer can be any light waveband, and the wavelength range can be set according to actual imaging requirements, which is not limited in the embodiment of the present application.

Continuing to refer to FIG. 11, optionally, above the microlens array 226, a light transmission layer 228 is also provided. The light transmission layer 228 may be air or a transparent medium material, and the transparent medium material may be glass, resin or other materials. Inorganic transparent material.

It should be noted here that if the light transmission layer 228 is a transparent medium material, the transmittance of the material is different from the transmittance of the microlens array 226, so as not to affect the light condensing effect of the microlens array 226.

Optionally, a transparent cover 229 is further provided above the light transmission layer 228, and the transparent cover 229 may be glass or other transparent medium materials. If the light transmission layer 228 is air, the transparent cover 229 needs to be placed above the microlens array 226 through a supporting device, such as a bracket, a sealant, etc., and the supporting device is also placed on the peripheral circuit of the second chip 220 area.

FIG. 12 shows another schematic cross-sectional view of the second wafer 220 described above.

As shown in FIG. 12, in addition to the structure shown in FIG. 11, the second wafer 220 also includes a second dielectric layer 2202. The second dielectric layer 2202 is formed under the first dielectric layer 2201. Optionally, the material of the second dielectric layer 2201 may be the same as the material of the above-mentioned first dielectric layer 2201, for example, it may be a substrate material such as silicon, ceramic, glass, etc., or may be other dielectric materials with a certain mechanical strength. In order to improve the mechanical strength of the second wafer 220 and the entire stacked chip 20.

In the embodiment of the present application, the thickness of the second dielectric layer 2202 is relatively thin, for example, about 10 μm, which can increase the mechanical strength of the second wafer 220 together with the first dielectric layer 2201. Further, the lower surface of the second dielectric layer 2202 is not lower than the lowest point of the solder ball 2223, which does not affect the soldering effect of the solder ball 2223 connecting the first pad on the first chip 210, and can also reduce the second chip 220 The overall thickness of the stacked chip 20 after being soldered to the first wafer 210.

In addition, the second dielectric layer 2202 does not cover the open area of the first dielectric layer 2201. In one embodiment, the second dielectric layer 2202 may be located only in the lower area of the pixel array, and may not be located in the outer periphery. The lower area of the circuit.

FIG. 13 shows a third schematic cross-sectional view of the second wafer 220 described above.

As shown in FIG. 13, the second chip 220 includes a plurality of pixel units 221, a second metal circuit layer 222, a microlens array 226, a filter layer 227, a light transmission layer 228, and a transparent cover plate 229. The wafer 220 also includes a second dielectric layer 2202. The second dielectric layer 2202 is formed under the first dielectric layer 2201 and covers the lower surface of the first dielectric layer 2201.

In the embodiment of the present application, the second pad 2221 is not formed in the second metal circuit layer 222, but is formed on the lower surface of the second dielectric layer 2202. Similarly, the second pad 2221 is formed in the surrounding area of the lower surface of the second dielectric layer 2202, in other words, is formed in the area of the peripheral circuit of the second chip 220 in FIG. 10.

Specifically, the second pad 2221 is connected to the second metal wiring layer 222 through the via interconnection structure 2224. Specifically, the through-hole interconnection structure is a high-density packaging technology. By making vertical through holes and filling the through holes with conductive materials such as polysilicon, copper, tungsten, etc., the second metal circuit layer and the second metal circuit layer are completed by the through holes. For the interconnection between pads, through-hole technology can reduce interconnection length, signal delay, capacitance/inductance, low power consumption, high-speed communication, increase broadband, and miniaturization of device integration through vertical interconnection.

It should be understood that, in this application, the through-hole interconnection structure can be an interconnection structure of other materials in addition to the Through Silicon Via (TSV) interconnection structure, such as Through Mold Via (TMV). ) Interconnection structure, Through Glass Via (TGV) interconnection structure, Gallium Nitride through-hole interconnection structure, resin through-hole interconnection structure, etc. The embodiments of the present application are related to specific through-hole interconnection structure materials Not limited.

Specifically, a solder ball 2223 is provided under the second pad 2221 for connecting the second pad 2221 and the first pad on the first chip 210.

The foregoing FIGS. 11 to 13 show the second wafer with three BSI structures. Optionally, the second wafer 220 may also be a front-side illuminated (FSI) complementary metal oxide semiconductor (CMOS) structure, where The pixel array in the second wafer 220 is located below the second metal circuit layer, and the preparation process of the second wafer of the FSI structure is simple, which can reduce the processing cost.

FIG. 14 shows a schematic cross-sectional view of a second wafer of an FSI structure.

As shown in FIG. 14, in the second wafer 220, the second metal circuit layer 222 is formed in the first dielectric layer 2201, and a plurality of pixel units 221 in the pixel array are formed in the second dielectric layer 2202.

Further, the filter layer 227 and the microlens array 228 are formed above the second metal circuit layer 222, and the related technical solutions of the filter layer 227 and the microlens array 228 can be referred to the related description in FIG. 11 above. Go into details again.

Optionally, in the embodiment of the present application, a light transmission layer 228 and a transparent cover 229 may also be provided above the microlens array 228, where the light transmission layer 228 may be air or other transparent media.

Since the second metal circuit layer 222 is disposed above the plurality of pixel units 221, the second metal circuit layer 222 is far away from the lower surface of the second dielectric layer 2202 and cannot be directly formed in the second metal circuit layer 222. The second pad 2221 is electrically connected.

As shown in FIG. 14, in the embodiment of the present application, a via interconnection structure 2224 is provided under the second pad 2221, and the via interconnection structure 2224 is connected to the second pad 2221 and the lower surface of the second chip. Further, solder balls 2223 are provided under the through-hole interconnection structure 2224 for connecting to the first pad on the first chip 210.

Similarly, in the embodiment of the present application, the second pad 2221 is formed in the surrounding area of the second metal dielectric layer 222, in other words, is formed in the area of the peripheral circuit of the second chip 220 in FIG. 10. For the technical solutions of the second pad 2221, the through-hole interconnection structure 2224, and the solder ball 2223, reference may be made to the related description in FIG. 13, and details are not described herein again.

10 to 14 illustrate the structure of the second wafer 220 in the stacked chip 20 in the C2W stacking process. Below, in conjunction with FIG. 15 to FIG. 18, it will be described that in the C2W stacking process, the first wafer in the stacked chip 20 is described. A structure of a wafer 210, a carrier unit 220, and a rewiring layer 214.

Specifically, on the basis of FIGS. 7 to 9, the first pad of the first wafer 210 is formed by the rewiring layer 214, that is, the structure of the first wafer 210 in the stacked chip 20 under the C2W stacking process.

As shown in FIGS. 15 and 16, the carrier unit 200 is a substrate or a molding compound, the rewiring layer 214 is formed above the carrier unit 200, and at least one first pad 216 is formed above the rewiring layer 214.

Specifically, a third dielectric layer 212 is formed between the carrier unit 200 and the rewiring layer 214. The third dielectric layer 212 is an insulating material for connecting the carrier unit 200 and the rewiring layer 214. Specifically, an opening is formed in the third dielectric layer 212, and the opening is filled with a metal dielectric, and the metal dielectric connects the rewiring layer 214 and the pad 213 of the first wafer 210.

Optionally, the gap between the first wafer 210 and the first groove 201 in the carrier unit 200 may also be filled with the above-mentioned third dielectric layer 212 to further stably fix the first wafer 210 in the first groove 201 middle. The third dielectric layer 212 includes, but is not limited to, a polymer organic material, such as a dry film (Dry Film) material or other polymer materials with good fluidity. In the embodiment of the present application, the third dielectric layer 212 can be a dry film material that can be photoetched, and can fill the gap between the first wafer 210 and the first groove 201 without cavities under vacuum and heating conditions. , And the use of photolithographic materials as the third dielectric layer, while filling and fixing the gap between the first groove and the first wafer, it can also facilitate the process and save the manufacturing time of the chip.

A fourth dielectric layer 215 is formed between the rewiring layer 214 and the at least one first pad 216. Similarly, the fourth dielectric layer 215 is also an insulating material for connecting the at least one first pad 216 and the rewiring layer. 214. Specifically, at least one opening is formed in the fourth dielectric layer 215, and the opening is filled with a metal dielectric, and the metal dielectric connects the rewiring layer 214 and the at least one first pad 216.

Optionally, as shown in FIGS. 15 and 16, in addition to the at least one first pad 216 above the first wafer, at least one specific solder for electrical connection with other electrical components except the second wafer is also formed. The disk 217 is, for example, electrically connected to a PCB board or other types of substrates, where the PCB board or other types of substrates can be the substrates of the electronic device where the stacked chips are located, or can be the components of other electrical components in the electronic device. Substrate. In the embodiment of the present application, the at least one specific pad 217 may be connected to the PCB board by wire bonding (WB). Specifically, in some embodiments, at least one specific pad 217 is disposed on the periphery of at least one first pad 216. In other words, the distance between the specific pad 217 and the edge of the fourth dielectric layer 215 is greater than the distance between the first pad 216 and the first pad 216. The distance between the edges of the four dielectric layers 215.

In the embodiment of the present application, the stacked chip 20 is connected to the PCB board through specific pads and leads, which is different from a ball grid array (Ball Grid Array, BGA) packaging method. A ball grid array is formed on the surface of the stacked chip 20. In this packaging method, the heat of the stacked chip is conducted to the ball grid array, and multiple hot spots are formed, which affects the performance of the stacked chip. However, adopting the WB packaging method of the embodiment of the present application does not cause this hot spot problem, improves the reliability of the stacked chip, and makes the application scenarios of the stacked chip more extensive.

Optionally, in the application embodiments of FIG. 15 and FIG. 16, the above-mentioned specific pad 217 may also be provided on the lower surface of the carrier unit 200, and a through-hole interconnection structure is formed to connect the rewiring layer 214 and the specific pad 217, Further, solder balls are provided on the pads for electrical connection with other electrical components, such as PCB boards or other types of substrates, or other types of chips.

As shown in FIG. 17, the carrier unit 200 is a circuit board, the rewiring layer 214 is formed inside the carrier unit 200, and at least one first pad 216 is formed on the upper surface of the carrier unit 200 and is interconnected through the rewiring layer 214. The structure is connected to the pad 213 of the first wafer 210 itself.

Optionally, in the embodiment of the present application, at least one first pad 216 is formed in a peripheral area of the upper surface of the fourth dielectric layer 215, or formed in a peripheral area of the upper surface of the carrier unit 200.

The number of the first pads 216 may be greater than or equal to the number of the second pads 2221 of the second wafer 220 described above. If the number of the first pads 216 is equal to the number of the second pads 2221, then a first pad 216 and a second pad 2221 are in one-to-one correspondence, and the solder balls 2223 on the second pad 2221 are used for electrical connection. If the number of the first pads 216 is greater than the number of the second pads 2221, in addition to the first pads connected to the second pads, the other first pads can be connected to other electrical components by wire bonding.

Since the first wafer 210 can be a logic wafer or a storage wafer, or other wafers for data processing, for example, the first wafer 210 is a logic wafer in an image sensor chip, which can be used for image data generated by multiple pixel units. Processing. During the data processing operation of the first wafer 210, a large amount of heat will be generated, which will affect the overall performance of the first wafer 210 and the stacked chip 20. In addition, if the second wafer 220 above the first wafer 210 is a temperature-sensitive pixel wafer, the large amount of heat generated by the first wafer 210 will also affect the operation of the second wafer 220, further deteriorating the overall performance of the stacked chip 20.

Optionally, in order to improve the heat dissipation capability of the first wafer 210, as shown in FIGS. 14 to 17, a first thermally conductive metal layer 203 is provided on the upper surface of the fourth dielectric layer 215 or the upper surface of the carrier unit 200, which is beneficial to Heat dissipation of the first chip 210.

Specifically, as shown in FIGS. 15 and 16, the first thermally conductive metal layer 203 is located at the center area of the upper surface of the fourth dielectric layer 215, and the first thermally conductive metal layer 203 is located at the center of the upper surface of the carrier unit 200 in FIG. area.

The area of the first thermally conductive metal layer 203 may be greater than or equal to the area of the pixel array in the second wafer 220. In other words, the projection of the pixel array on the plane where the first thermally conductive metal layer 203 is located is completely in the first thermally conductive metal layer 203. At this time, the second wafer 220 is less affected by the heat of the first wafer 210. Of course, the area of the first thermally conductive metal layer 203 may also be smaller than the area of the pixel array in the second wafer 220, and the embodiment of the present application does not specifically limit the area of the first thermally conductive metal layer 203.

Optionally, the first thermally conductive metal layer 203 and the first pad 216 may be located on the same horizontal plane, and the two may be the same metal material. In the preparation process, the first thermally conductive metal layer can be prepared by using one process. 203 and the first pad 216.

In addition, as shown in FIG. 15 to FIG. 17, in addition to providing the first thermally conductive metal layer 203 to dissipate the heat generated by the first chip, at least one specific pad 217 is also provided above the first chip. The disk 217 is connected to the substrate through leads, and the heat generated during the operation of the first wafer 210 can also be conducted to the substrate through the leads, thereby improving the heat dissipation capability of the first wafer 210.

In addition to the foregoing embodiments, in order to further improve the heat dissipation capability of the first wafer 210, in a possible implementation manner, the lower surface of the first wafer 210 may be in contact with air. At this time, as described above, the carrier unit The first accommodating structure 201 in 200 is configured as a through hole.

In another possible implementation manner, when the first accommodating structure 201 in the carrier unit 200 is a groove, taking FIG. 18 as an example, a structure for improving the heat dissipation capacity of the first wafer 210 is described.

As shown in FIG. 18, the carrier unit 200 is a circuit board or a plastic-encapsulated substrate. Of course, the carrier unit 200 may also be the aforementioned substrate or a plastic-encapsulated material, and the corresponding solution can be referred to the following description.

Specifically, a second thermally conductive metal layer 204 is provided on the bottom of the first wafer 210, and a third thermally conductive metal layer 205 is provided on the lower surface of the carrier unit 200, and the second thermally conductive metal layer 204 and the third thermally conductive metal layer are connected through the interconnection structure. The layers 205 are connected to guide the heat of the first wafer 210 through the second thermally conductive metal layer 204 and the interconnection structure to the third thermally conductive metal layer 205 in contact with the air, thereby improving the heat dissipation capability of the first wafer 210.

Optionally, the third thermally conductive metal layer 205 may completely cover the lower surface of the carrier unit 200 to maximize the heat dissipation of the first wafer 210, or may only cover a part of the surface of the carrier unit 200, which is not done in this embodiment of the application. limited.

Optionally, the carrier unit 200 may have the same shape and size as the second wafer 220, and the projections of the carrier unit 200 and the second wafer 220 in the vertical direction completely coincide.

Optionally, the carrier unit 200 may have a different shape and size from the second wafer 220. Specifically, the surface area of the second wafer 220 is smaller than the surface area of the carrier unit 200, and the projection of the second wafer 220 on the carrier unit 200 is located on the carrier. In unit 200.

In this case, FIG. 19 shows a schematic structural diagram of a stacked chip 20.

As shown in FIG. 19, in the stacked chip 20, the second wafer is the second wafer 220 in FIG. 11, and the first wafer and carrier unit are the first wafer 210 and the carrier unit 200 in FIG. 16.

In the embodiment of the present application, the second pad 2221 and the solder ball 2223 of the second chip 220 are disposed above the first pad 216 of the first chip 210. The specific pad 217 is located on the periphery of the first pad 216, the projection of the second chip 220 on the carrier unit 200 does not cover the area where the specific pad 217 is located, and the specific pad 217 is located on the vertical projection of the second chip 220 Outside.

It should be understood that the second wafer in the stacked chip 20 may be any of the second wafers 220 in FIGS. 11 to 13, and the first wafer and the carrier unit may be any of the first wafers 210 in FIGS. 14 to 16 And carrier unit 200. In other words, the second wafer 220 in FIG. 11 can be combined with any of the situations in FIGS. 14 to 16 to form a stacked chip, and the second wafer 220 in FIGS. 12 and 13 can also be combined with those in FIGS. 14 to 16. Any combination of conditions forms a stacked chip, that is, in the above-mentioned application embodiment, a total of 9 specific structures of the stacked chip 20 are given.

FIG. 20 shows a schematic diagram of a separate structure of another stacked chip 20 according to an embodiment of the present application.

As shown in FIG. 20, the stacked chip 20 further includes:

The third wafer 230 is disposed in the second accommodating structure 202 of the carrier unit 200, and the second accommodating structure 202 is a groove or a through hole.

Optionally, the second wafer 220 described above is stacked on the third wafer 230, and the area of the second wafer 220 is larger than that of the third wafer 230.

Specifically, the third wafer 230 has a sheet-like structure and therefore has a small thickness. The surface area of the third wafer 230 is also the upper surface area or the lower surface area of the first wafer 210.

In a possible implementation, the surface area of the second wafer 220 is greater than the sum of the surface area of the first wafer 210 and the surface area of the third wafer 230. For example, the first wafer 210 and the third wafer 230 are completely located in the projection of the second wafer 220 in the vertical direction.

Optionally, the third wafer 230 may be completely located inside the carrier unit 200, and the upper surface of the third wafer 230 is not higher than the upper surface of the carrier unit 200.

Specifically, if the second accommodating structure 202 is a groove, in one embodiment, the second accommodating structure 202 may be located inside the carrier unit 200, that is, the groove and the third wafer 230 are completely disposed in the carrier unit 200 The third wafer 230 is lower than the upper surface of the carrier unit 200. In another embodiment, the second accommodating structure 202 may also be located on the upper surface of the carrier unit 200. At this time, the upper surface of the third wafer 230 and the upper surface of the carrier unit 200 may be on the same level. Of course, If the height of the second accommodating structure 202 is greater than the thickness of the third wafer 230, the upper surface of the third wafer 230 may also be lower than that of the carrier unit 200.

If the second accommodating structure 202 is a through hole, the third chip 230 is disposed in the through hole, and the four sides of the third chip 230 are fixedly connected to the walls of the through hole. Optionally, if the carrier unit 200 is a plastic package material , The third chip 230 is directly fixed in the through hole of the carrier unit 200. If the carrier unit 200 is a circuit board or a substrate, the third chip 230 can be fixedly connected in the through hole by an adhesive layer or other fixing devices. Optionally, at this time, the upper surface of the third wafer 230 is not higher than the upper surface of the carrier unit 200, and the lower surface of the third wafer 230 is not lower than the lower surface of the carrier unit 200.

When the second accommodating structure 202 is a through hole, the lower surface of the third wafer 230 is in contact with the air, which is beneficial to the heat dissipation of the third wafer 230, and can improve the reliability and reliability of the third wafer 230 and the entire stacked chip 20. Overall performance.

Hereinafter, taking the second accommodating structure 202 as a groove as an example to illustrate the overall structure of the stacked chip 20, unless otherwise specified, the case where the second accommodating structure 202 is a through hole can be referred to the following description. Hereinafter, if the second accommodating structure 202 is a groove, the second accommodating structure 202 is also written as the second groove 202, and if the second accommodating structure 202 is a through hole, the second accommodating structure 202 is also written It is the second through hole 202.

Optionally, the shape and size of the second groove 202 in the carrier unit 200 may be the same as the shape and size of the third wafer 230 or slightly larger than the third wafer 230. For example, the third wafer 230 has a sheet structure, the depth of the second groove 202 is the same as the thickness of the third wafer 230 or slightly larger than the thickness of the third wafer 230, and the length and width of the second groove 202 are also They are slightly larger than the length and width of the third wafer 230 respectively, so that the second groove 202 can completely accommodate the third wafer 230 therein. Optionally, the length, width, and depth of the second groove 202 are larger than the length, width, and height of the third wafer 230 by 25 μm, or any other value, which is not limited in the embodiment of the present application.

Optionally, in the embodiment of the present application, the third chip 230 may be used to implement circuit functions different from those of the first chip 210 and the second chip 220. For example, if the stacked chip 20 is an image sensor For the chip, the first chip 210 may be the pixel chip 101 in FIG. 1 described above, and the second chip 220 and the third chip 230 may be the logic chip 102 and the memory chip 103 in FIG. 1 described above, respectively.

It should be understood that the stacked chip 20 may also be a chip in a variety of other different fields, such as a memory chip, a processing chip, etc., wherein the first chip, the second chip, and the third chip are functional chips that implement corresponding circuit functions. And the circuit functions of the first chip, the second chip, and the third chip are different.

In the embodiment of the present application, by arranging the first wafer 210 and the third wafer 230 in the groove of the carrier unit 200, the large area of the second wafer 220 is stacked on the first wafer 210 and the third wafer 230. At the same time, as many first wafers 210 and third wafers 230 as possible can be grown on the wafer, reducing manufacturing costs. In addition, the space in the stacked chips can be fully utilized to stack the second wafer 220 on top of the first wafer 210 and the third wafer 230 without the need to bond the three wafers in sequence, thereby further reducing the process cost and also Reduce the volume of stacked chips. Third, it is also possible to test a single first wafer 210 and a single third wafer 230 before bonding to screen out wafers with good performance, remove the wafers with poor performance, and improve the overall chip yield. , To further reduce the overall manufacturing cost.

Optionally, the third chip 230 may be a dummy chip (Dummy die) in addition to a circuit function chip, that is, it is not used to realize a circuit function, and is only a substrate with a certain mechanical strength or a sheet-like object of other materials. . At this time, the third wafer 230 can balance the mechanical stress caused by the processing process, reduce the warpage of the carrier unit 200, and improve the overall mechanical performance of the stacked chip.

It should be understood that if the third chip 230 is a dummy chip, the rewiring layer 214 above the carrier unit 200 does not need to be electrically connected to the third chip 230, and the third chip 230 does not need to be electrically connected to the first chip 210 and the second chip. The two chips 220 are electrically connected.

Optionally, a rewiring layer 214 is provided above the first chip 210 and the third chip 230. The rewiring layer 214 is used to connect the IO ports of the first chip 210 and re-lay out the IO ports of the first chip 210. In addition, it is also used to connect the IO ports of the third chip 230 and re-layout the IO ports of the third chip 230.

Optionally, the third chip 230, the first chip 210, and the second chip 220 may also be stacked by wafer-level bonding, or stacked by bonding pads.

FIGS. 21 to 23 show three schematic cross-sectional views of the carrier unit 200, the first wafer 210, the third wafer 230, and the rewiring layer 214 in the pad connection mode, or the C2W stacking mode.

As shown in FIG. 21, the carrier unit 200 may be a substrate in which a first groove 201 and a second groove 202 (not shown in the figure) are arranged, and the first wafer 210 and the third wafer 230 are respectively arranged on The first groove 201 and the second groove 202 are located. The third wafer 230 is at the bottom of the second groove 202 through the third adhesive layer 231 to stably fix the third wafer 230 in the second groove 202. The adhesive layer includes but is not limited to DAF film. Optionally, in a possible implementation, when the thickness of the third adhesive layer 231 is d1 and the height of the third wafer 230 is d2, the sum of the thicknesses of the third wafer 230 and the third adhesive layer 231 is d1+ d2 is less than or equal to the depth d0 of the second groove 202, in other words, the upper surface of the third wafer 230 is not higher than the upper surface of the carrier unit. Optionally, the difference between d1+d2 and d0 may be between 2 μm and 5 μm, or may be other values, which is not limited in the embodiment of the present application. Optionally, in another possible implementation manner, the upper surface of the third wafer 230 may also be higher than the upper surface of the carrier unit.

Optionally, the gap between the third wafer 230 and the second groove 202 can also be filled with the aforementioned third dielectric layer 212 to further stably fix the third wafer 230 in the second groove 202.

Optionally, as shown in FIG. 21, the third chip 230 includes a third metal circuit layer 233, which is located on the surface of the third chip 230, specifically an IO port of the third chip 230, for It is electrically connected with other electrical components, such as the second wafer 220 and the first wafer 210. In addition, the above-mentioned third dielectric layer 212 may also cover the upper surface of the carrier unit 200 and a part of the upper surface of the third wafer 230 except for the third metal circuit layer 233.

As shown in FIG. 22, the carrier unit 200 may be a plastic packaging material, and it may specifically be an EMC material, which is not specifically limited in the embodiment of the present application.

In the embodiment of the present application, the third chip 230 is wrapped and fixed by a plastic encapsulant, and no additional filling material or glue layer is required to fix the third chip 230. Optionally, in some embodiments, the upper surface of the third wafer 230 is not wrapped by molding compound, and the other five planes are covered by molding compound. In other embodiments, all six surfaces of the third wafer 230 may also be wrapped by a plastic molding compound.

As shown in FIGS. 21 and 22, the rewiring layer 214 is disposed above the carrier unit 200 and the third wafer 230. The rewiring layer 214 is also a metal wiring layer, which is connected to the third metal circuit on the surface of the third wafer 230. The layer 233 is in contact to form an electrical connection between the two.

Optionally, in the embodiment of the present application, the rewiring layer 214 is also used to connect the third metal circuit layer 233 of the third wafer 230 and the first metal circuit layer 213 of the first wafer 210.

As shown in FIGS. 21 and 22, at least one first pad 216 is formed above the rewiring layer 214. For the related technical solutions of the at least one bonding pad 216, refer to the related descriptions of FIG. 15 and FIG. 16, which will not be repeated here.

Optionally, in the application embodiment of FIG. 21 and FIG. 22, a pad may also be provided on the lower surface of the carrier unit 200, and a through-hole interconnection structure may be formed to connect the rewiring layer 214 and the pad. Further, in the Soldering balls are provided on the pads for electrical connection with other electrical components, such as PCB boards or other types of substrates.

As shown in FIG. 23, the carrier unit 200 may also be a circuit board, which is made of an insulating material, and is provided with multiple metal layers. The multiple metal layers may be copper metal or other metal materials for conducting electricity. Signals, the multi-layer metal layers can be connected through an interconnection structure to realize electrical signal transmission between the multi-layer metal layers.

In the embodiment of the present application, the third chip 230 can be completely disposed inside the circuit board, and its six surfaces are all wrapped by the insulating material of the circuit board, and the rewiring layer 214 in the circuit board is connected to the IO port of the third chip 230. The re-layout of the IO ports of the third chip 230 is realized.

As shown in FIG. 23, at least one first pad 216 is formed above the carrier unit 200. For the related technical solutions of the at least one pad 216, refer to the related description of FIG. 17, and will not be repeated here.

Optionally, in the solutions of FIGS. 21 to 23, at least one third pad 218 is further formed above the rewiring layer 214, and the at least one third pad 218 is used to connect to the third chip through the rewiring layer 214 230.

Optionally, as shown in FIGS. 21 to 23, at least one specific pad 217 is provided on the periphery of the third pad 218, in other words, the distance between the specific pad 217 and the edge of the fourth dielectric layer 215 is greater than that of the first pad 216 The distance from the edge of the fourth dielectric layer 215.

It should be understood that if the third wafer 230 is a dummy chip, the third pad 218 may not be provided, and the position of the third pad 218 in FIGS. 21 to 23 may be set as the first pad 216.

Similarly, in order to solve the heat dissipation problem of the third chip 230, as shown in FIGS. 21 to 23, the first thermally conductive metal layer 203 covers the third chip 230 and the first chip 210.

Optionally, in the embodiment of the present application, in order to further improve the heat dissipation capability of the third chip 230, the lower surface of the third chip 230 may also be in contact with air. At this time, as described above, the carrier unit 200 The second accommodating structure 202 is configured as a through hole.

In another possible implementation manner, when the first accommodating structure 201 in the carrier unit 200 is a groove, a thermally conductive metal layer is also provided on the bottom of the third wafer 230, and the thermally conductive metal layer is connected to the bottom of the third wafer 230 through the interconnection structure. The third thermally conductive metal layer 205 on the lower surface of the carrier unit 200 is connected, thereby improving the heat dissipation capability of the third chip 230.

FIG. 24 shows a schematic structural diagram of a stacked chip 20. The stacked chip 20 is an image sensor chip.

As shown in FIG. 24, in the stacked chip 20, the second wafer is the second wafer 220 in FIG. 11, and the first wafer, the third wafer, and the carrier unit are the wafer structure in FIG. 22.

It should be understood that the second wafer in the stacked chip 20 may be any of the second wafers 220 in FIGS. 11 to 13, and the first wafer, the third wafer, and the carrier unit may be any of in FIGS. 21 to 23 Wafer structure. In other words, the second wafer 220 in FIG. 11 can be combined with any one of the cases in FIGS. 21 to 22 to form a stacked chip, and the second wafer 220 in FIGS. 12 and 13 can also be combined with those in FIGS. 21 to 23. Any combination of conditions forms a stacked chip, that is, in the above-mentioned application embodiment, nine specific structures of the stacked chip 20 are given.

Optionally, in the embodiment of the present application, the lower surface of the first wafer 220 is provided with at least one second pad and at least one fourth pad, and the at least one second pad is used to interact with at least one above the carrier unit. The first pad is electrically connected, and the at least one fourth pad is used for electrically connecting with the at least one third pad above the carrier unit.

Specifically, the formation process of the fourth bonding pad is the same as that of the second bonding pad, and both are bonding pads in the second metal circuit layer of the second target chip. The second pad is connected to the first pad of the first wafer, and the second pad and the fourth pad can be used to output the same electrical signal.

6 to 24, the device embodiment of the stacked chip of the present application is described in detail above, and the following describes the embodiment of the method of manufacturing the stacked chip of the present application in detail with reference to Figs. 25 to 20. It should be understood that the device The embodiment and the method embodiment correspond to each other, and the device embodiment can be referred to for similar description.

FIG. 25 is a schematic flow chart of a method for manufacturing a stacked chip. The manufacturing method is a stacked chip based on a C2W stacking method.

As shown in FIG. 25, the manufacturing method 200 of the stacked chip may include the following steps.

S210: Divide a plurality of first wafers from the first wafer.

Specifically, a plurality of first wafers are prepared on the first wafer, and the first wafers may be wafers of different materials such as silicon wafers.

Optionally, each of the plurality of first wafers may be the same as the first wafer 210 in the foregoing device embodiment.

If the first chip is a logic chip or a memory chip, or a chip in other fields, the manufacturing method and the cutting method on the wafer can be referred to related descriptions in the prior art, which will not be repeated here.

S220: Package a plurality of first chips in a carrier, the carrier includes a rewiring layer, and the rewiring layer is electrically connected to the first target chip among the plurality of first chips.

Optionally, the carrier may include any one of a substrate wafer, a molding compound, a packaging substrate, or a circuit board.

In a possible embodiment, the carrier includes a substrate wafer, and a plurality of first accommodating structures are fabricated on the substrate wafer, and the first accommodating structures are grooves or through holes. The plurality of first chips are fixed in the plurality of first accommodating structures, and the upper surface of the plurality of first chips is not higher than the upper surface of the substrate wafer.

Specifically, if the first accommodating structure is a groove, after preparing a plurality of first grooves on the substrate wafer, the plurality of first wafers are placed in a plurality of first wafers through a pick and place process. In the groove.

Optionally, in the embodiment of the present application, a plurality of first grooves may be prepared on the substrate wafer through a variety of process methods, including but not limited to: dry etching, Laser method, mechanical method, etc. The embodiments of the present application do not specifically limit this.

After the multiple first grooves are prepared on the substrate wafer, the multiple first wafers can be placed in the multiple first grooves by using a standard pick-and-place process. Wherein, the lower surface of the first wafer is provided with a first glue layer, and the first glue layer includes but is not limited to DAF.

Further, after placing the plurality of first wafers in the plurality of first grooves, a third dielectric layer is filled in the gaps between the plurality of first wafers and the plurality of first grooves and the upper surface of the carrier unit to The plurality of first wafers are further fixed.

Optionally, the above-mentioned related technical solutions such as the first groove, the first wafer, and the third dielectric layer can refer to the related description of FIG. 7 or FIG. 15.

Specifically, if the first accommodating structure is a through hole, the plurality of first wafers can be fixed in the plurality of first through holes through an adhesive layer. In this case, the heat dissipation capability of the plurality of first wafers can be improved.

After placing the plurality of first wafers in the plurality of first accommodating structures, a rewiring layer is prepared on the first target wafer among the plurality of first wafers, where the first target wafer may be in the plurality of first wafers Any one of the chips.

Specifically, a semiconductor process, such as exposure, development, and etching, can be used to open a window on the third dielectric layer to expose the first metal circuit layer on the upper surface of the first target wafer.

In this process step, the first metal circuit layer on the upper surface of each of the plurality of first wafers can be exposed at the same time.

Then, the rewiring layer of the first target wafer is prepared on the surface of the third dielectric layer above the first target wafer by using processes such as seed layer deposition, photolithography, and electroplating. Wherein, the rewiring layer is in contact with the first metal circuit layer of the first target wafer to form an electrical connection relationship.

In this process step, the rewiring layer of each of the multiple first wafers can also be prepared at the same time, and the rewiring layers of different first wafers are not connected to each other.

Optionally, the above-mentioned related technical solutions of the rewiring layer of the first target wafer can also refer to the related description of the rewiring layer 214 in FIG. 7 or FIG. 15.

In the embodiment of the present application, the substrate wafer may be silicon, glass, ceramic or any other material, which is not limited in the embodiment of the present application. In a possible embodiment, the substrate wafer is a single crystal silicon wafer.

In another possible embodiment, the carrier further includes a molding compound, and the plurality of first chips are encapsulated in the molding compound, wherein the upper surfaces of the plurality of first chips are in contact with air, and the plurality of The upper surface of the first wafer is not higher than the upper surface of the molding compound.

Optionally, the molding compound may specifically be epoxy resin molding compound, or other organic or inorganic materials used for chip packaging in the prior art, which are not specifically limited in the embodiment of the present application.

In the embodiment of the present application, the plurality of first wafers are wrapped and fixed by the molding compound, and no additional filling material or glue layer is required to fix the plurality of first wafers. Optionally, in some embodiments, the upper surfaces of the plurality of first wafers are not wrapped by the molding compound, and the other five planes are covered by the molding compound. In other embodiments, all six surfaces of the plurality of first wafers may also be wrapped by a plastic molding compound.

Further, a third dielectric layer is prepared on the plurality of first wafers and the molding compound. Specifically, semiconductor processes, such as exposure, development, and etching, may be used to open windows on the third dielectric layer to expose the first dielectric layer. The first metal circuit layer on the upper surface of the target wafer.

Optionally, the above-mentioned related technical solutions of the rewiring layer and the first target wafer can also refer to the related description in FIG. 8 or FIG. 16.

In a third possible implementation manner, the carrier further includes a packaging substrate, the plurality of first chips are packaged inside the packaging substrate, and the rewiring layer is prepared in the packaging substrate, wherein the rewiring layer includes multiple A metal circuit layer arranged horizontally and a plurality of interconnection structures arranged vertically.

Optionally, the packaging substrate can also be other types of circuit boards, such as PCB boards, etc. The technical solution for packaging the multiple first chips on the packaging substrate can be referred to related descriptions in the prior art, which will not be repeated here. .

S230: Prepare a first pad above the rewiring layer, and the first pad is electrically connected to the first target wafer through the rewiring layer.

In this step, the process of preparing the first pad on the rewiring layer can refer to the pad preparation technology in the prior art. The structure of the first target wafer, the rewiring layer, and the first pad formed after this step can be seen in FIG. 15 to FIG. 17, and the related technical solutions in this step can also be seen in the above description, and will not be repeated here.

S240: Prepare a plurality of second wafers on the second wafer, and separate the second target wafers of the plurality of second wafers from the second wafer, the second target wafers including second pads.

Optionally, a plurality of second wafers are prepared on the second wafer, and the second wafers are diced, where the second wafers may be wafers of different materials such as silicon wafers.

Optionally, the second target wafer may be any one of a plurality of second wafers, and it may specifically be a wafer that has passed inspection.

Optionally, the second target wafer may be the same as the second wafer 220 in the foregoing device embodiment.

The second chip is provided with a second pad. The second pad is an IO port of the second chip and can be used to transmit electrical signals of the second chip.

S250: Weld the first pad and the second pad to electrically connect the first target chip and the second target chip.

Specifically, the above-mentioned welding of the first pad and the second pad may use a welding technique in the prior art, for example, the first pad and the second pad are welded by a point connecting device such as a solder ball.

S260: Cutting the electrically connected whole of the first target wafer and the second target wafer to obtain a stacked chip, wherein the surface area of the second target wafer is larger than the surface area of the first target wafer.

Optionally, the stacked chip is an image sensor chip, the second target wafer is a pixel wafer, and the second target wafer includes a pixel array for receiving optical signals and converting them into electrical signals;

The first target chip is a logic chip, and the first target chip includes a signal processing circuit for processing the electrical signal.

Hereinafter, taking the second target wafer as a pixel wafer as an example, the preparation process of the second target wafer is described.

Optionally, the above step S240 may include the following steps.

S241: Prepare a pixel array of the second target wafer in the second wafer, and prepare a first dielectric layer and a second metal circuit layer on the surface of the second wafer, wherein the second metal circuit layer is formed on The first dielectric layer and the second metal circuit layer are electrically connected to the pixel array.

Specifically, the pixel array can be prepared in the second wafer through semiconductor processes such as doping, and then on the pixel array, that is, the first dielectric layer and the second dielectric layer are grown on the surface of the second wafer through semiconductor processes such as deposition and photolithography. Metal circuit layer.

Optionally, the first dielectric layer may be an insulating material layer, and the insulating dielectric layer may be an insulating material such as silicon oxide. The specific material of the insulating dielectric layer is not limited in the embodiment of the present application. Optionally, the second metal circuit layer may be a material such as gold, copper, or alloy, and the embodiment of the present application does not limit the specific material of the second metal circuit layer.

Optionally, the pixel array, the first dielectric layer and the second metal circuit layer may be the pixel array, the first dielectric layer 2201 and the second metal circuit layer 222 in any of the embodiments in FIG. 11 to FIG. The technical solution can refer to the above description.

S242: preparing the second pad, and the second pad is formed in the second metal circuit layer;

Optionally, the second pad is formed outside the projection of the pixel array on the plane where the second metal circuit layer is located. In other words, the second pad is formed in the surrounding area of the second metal circuit layer, not in the central area, and the pixel array is arranged above the central area.

S243: Prepare an electrical connection device under the second bonding pad.

Optionally, the electrical connection device includes but is not limited to solder balls, copper pillars, etc., which can be any electrical connection device in the prior art.

Optionally, a bottom bump metallization layer or a via interconnection structure is prepared under the second pad. The via interconnection structure includes but is not limited to TSV.

Further, solder balls or copper pillars are prepared under the metallization layer of the bottom layer of the bump or the through-hole connection structure.

In one embodiment, the second target wafer has a back-illuminated structure. In this case, as shown in FIG. 26, the above step S241 may include the following steps.

S2411: preparing the pixel array in the lower part of the second wafer, the pixel array being close to the lower surface of the second wafer, and preparing the first dielectric layer and the second metal on the lower surface of the second wafer Line layer.

Optionally, during the preparation process, it can be understood that the pixel array is prepared in the upper part of the second wafer, and then the first dielectric layer and the second metal circuit layer are prepared on the upper surface of the second wafer, and then the The second wafer is turned upside down to form a back-illuminated pixel wafer structure.

After this step, the structure of the second target wafer 220 is shown in FIG. 27, wherein the pixel array is composed of a plurality of pixel units 221 formed on the lower surface of the second wafer, and the second wafer is prepared below the second wafer. A dielectric layer 2201, and a second metal circuit layer 222 is formed in the first dielectric layer 2201. It should be noted here that the second metal circuit layer 222 has an electrical connection relationship with a plurality of pixel units 221 (not shown in FIG. 27).

S2412: Bonding the second wafer on the substrate wafer by using a wafer bonding process.

Specifically, after the first dielectric layer and the second metal circuit layer are prepared, the lower surface of the first dielectric layer is planarized. Optionally, a polishing treatment is performed on the lower surface of the first dielectric layer, and the polishing treatment includes, but is not limited to, a chemical-mechanical polishing (Chemical-Mechanical Planarization, CMP) process.

Optionally, in the embodiment of the present application, the upper surface of the substrate wafer is also planarized to form a smooth surface. After the planarization process, the flatness and roughness of the upper surface of the substrate wafer and the lower surface of the first dielectric layer meet certain threshold requirements before wafer-level bonding can be performed.

Specifically, the upper surface of the smooth substrate wafer and the lower surface of the first dielectric layer are bonded together, and then subjected to high temperature annealing, so that the bonding force between the second wafer and the insulating dielectric layer is enhanced, and the gap between the wafers is improved. This bonding method is also called Fusion Bonding.

Optionally, the bonding of the second wafer and the substrate wafer may also adopt other wafer-level bonding methods, such as various direct bonding processes, including but not limited to: Anodic Bonding, Surface activated bonding (Surface Activated Bonding, SAB), etc., as well as various indirect bonding processes through the intermediate layer, including but not limited to: Transient Liquid Phase (TLP) bonding, thermocompression bonding Methods such as (Thermal Compression Bonding) and Adhesive Bonding (Adhesive Bonding) are not specifically limited in the embodiments of the present application.

After this step, the structure of the second target wafer 220 is as shown in FIG. 28, wherein, after dicing, the substrate wafer in the stacked chip may be the second dielectric layer 2202 in the above device embodiment.

S2413: Perform a thinning process on the upper surface of the second wafer, where the pixel array is close to the upper surface of the second wafer after the thinning process.

Specifically, methods such as mechanical thinning, chemical thinning, chemical polishing, dry etching, etc. can be used to thin the upper surface of the substrate material of the second wafer. The specific thinning method is not described in the embodiment of this application. Any restrictions. In the process of thinning the second wafer, the substrate wafer can play a supporting role.

Optionally, in the embodiment of the present application, the second target wafer 220 is a pixel wafer. After this step, the structure of the second target wafer 220 is as shown in FIG. 29. The upper surface of the thinned second wafer is close to A plurality of pixel units 221 in the second target wafer.

S2414: Prepare an optical component above the pixel array, the optical component including: a filter layer and/or a micro lens array.

Specifically, the steps of growing the filter layer and the microlens array above the pixel array can be referred to the manufacturing process in the prior art. After this step, the structure of the second target wafer 220 is as shown in FIG. 30. The filter layer and the For the microlens array, reference may be made to the related description of the filter layer 227 and the microlens array 226 in the above device embodiment.

S2415: A transparent cover is provided as a support structure above the pixel array, and the lower surface of the substrate wafer is thinned.

Specifically, a transparent cover is provided as a support structure above the microlens array, and the space between the transparent cover and the microlens array is air or a transparent medium material.

Optionally, methods such as mechanical thinning, chemical thinning, chemical polishing, dry etching, etc. can be used to thin the lower surface of the substrate material of the substrate wafer. Make any restrictions. In the process of thinning the second wafer, the transparent cover wafer can play a supporting role.

Optionally, the lower surface of the substrate wafer is thinned until the second metal circuit layer is close to the lower surface of the substrate wafer after the thinning process. At this time, the thickness of the substrate wafer is very high. Small, for example, about 10 μm, which can improve the mechanical strength of the second target wafer.

After this step, the structure of the second target wafer 220 is shown in FIG. 31. In this figure, 228 may be a transparent medium material, that is, the light transmission layer in the above device embodiment. If 228 is air in the figure, a supporting device should be provided between the transparent cover 229 and the microlens array 226 to support the lens cover to be suspended above the microlens array 226.

Continuing to refer to FIG. 26, as shown in FIG. 26, the above step S242 may further include the following steps.

S2421: Perform an etching process on the lower surface of the substrate wafer to form an opening, and the opening is connected to the second metal circuit layer to form a second pad in the second metal circuit layer.

Specifically, dry etching or wet etching may be used to etch the lower surface of the substrate wafer to form openings to expose the second pad in the second metal circuit layer.

After this step, the structure of the second target wafer 220 is as shown in FIG. 32, in which the second pad 2221 is formed in the surrounding area of the second metal circuit layer.

Further, after this step, step S243 is performed to prepare an electrical connection device under the second pad. Specifically, a bottom bump metallization UBM layer is prepared under the second pad, and solder balls or copper pillars are prepared on the bottom bump metallization UBM layer. After step S243 is executed, the structure of the second target wafer 220 is as shown in FIG. 12.

Optionally, in step S2415, the lower surface of the substrate wafer may also be thinned to completely remove the substrate wafer. At this time, the thickness of the second target wafer can be further reduced.

At this time, as shown in FIG. 26, the above step S242 may further include the following steps.

S2422: Perform etching treatment on the lower surface of the first dielectric layer to form an opening, and the opening is connected to the second metal circuit layer to form the second pad in the second metal circuit layer.

Further, after this step, step S243 is performed to prepare an electrical connection device under the second pad. Specifically, a bottom bump metallization UBM layer is prepared under the second pad, and solder balls or copper pillars are prepared on the bottom bump metallization UBM layer. After performing step S243, the structure of the second target wafer 220 is as shown in FIG. 11.

Optionally, in the above step S2415, the lower surface of the substrate wafer may also be thinned slightly, or the lower surface of the substrate wafer may not be thinned.

After this step, step S243 is performed to prepare an electrical connection device under the second pad. Specifically, a through-hole interconnection structure, such as a TSV, is prepared under the second pad, and solder balls or copper pillars are prepared under the TSV. After performing step S243, the structure of the second target wafer 220 is as shown in FIG. 13.

Optionally, in this embodiment, if the lower surface of the substrate wafer is not thinned, the second target wafer 220 may not be provided with the transparent cover 229 and the light transmission layer 228.

In another embodiment, the second target wafer has a front-illuminated structure. In this case, as shown in FIG. 33, the above step S241 may include the following steps.

S2416: preparing a pixel array on the upper part of the second wafer, the pixel array being close to the upper surface of the second wafer, and preparing a first dielectric layer and a second metal circuit layer on the upper surface of the second wafer.

After this step, the structure of the second target wafer 220 is shown in FIG. 34, where the pixel array is composed of a plurality of pixel units 221 formed on the upper surface of the second wafer, and the second wafer is prepared above the second wafer. A dielectric layer 2201, and a second metal circuit layer 222 is formed in the first dielectric layer 2201. It should be noted here that the second metal circuit layer 222 has an electrical connection relationship with a plurality of pixel units 221 (not shown in FIG. 34).

S2414: Prepare an optical component above the pixel array, the optical component including: a filter layer and/or a microlens array.

After this step, the structure of the second target wafer 220 is shown in FIG. 35.

S2617: A transparent cover plate is arranged above the pixel array.

Optionally, this step can refer to the related description of step S2415. After this step, the structure of the second target wafer 220 is as shown in FIG. 36.

The above step S242 may include the following steps.

S2423: Perform an etching process on the lower surface of the second wafer to form an opening, and the opening is connected to the second metal circuit layer to form a second pad in the second metal circuit layer.

After this step, the structure of the second target wafer 220 is as shown in FIG. 37.

Further, after this step, step S243 is performed to prepare an electrical connection device under the second pad. Specifically, a through-hole interconnection structure, such as a TSV, is prepared under the second pad, and solder balls or copper pillars are prepared under the TSV. After step S243 is performed, the structure of the second target wafer 220 is as shown in FIG. 14.

Fig. 38 is a schematic flow chart of another method for manufacturing a stacked chip.

As shown in FIG. 38, the manufacturing method 300 of the stacked chip includes:

S310: Divide a plurality of first wafers from the first wafer

S320: Divide a plurality of third wafers from the third wafer;

S330: Package a plurality of first chips and a plurality of third chips in a carrier, the carrier includes a rewiring layer, and the rewiring layer is electrically connected to the first target chip and the third target chip.

S340: Prepare a first pad above the rewiring layer, and the first pad is electrically connected to the first target wafer through the rewiring layer.

S350: Prepare a second target chip on the second wafer, and separate the second target chip from the second wafer, where the second target chip includes a second pad.

S360: Weld the first pad and the second pad to electrically connect the first target chip and the second target chip.

S370: cutting the entirety of the first target wafer, the second target wafer, and the third target wafer to obtain a stacked chip, wherein the surface area of the second target wafer is larger than the surfaces of the first target wafer and the third target wafer The sum of the area.

Specifically, the foregoing step S310 may refer to step S210 in FIG. 25, and step S340 to step S360 may refer to step S230 to step S250 in FIG. 25.

Specifically, in step S320, a plurality of third wafers are prepared on the third wafer, and the third wafers may be silicon wafers and other wafers of different materials.

Optionally, each of the plurality of third wafers may be the same as the third wafer 230 in the foregoing device embodiment.

If the third chip is a memory chip or a chip in other fields, the manufacturing method and the cutting method on the wafer can be referred to related descriptions in the prior art, which will not be repeated here.

In step S330, the plurality of first wafers and the plurality of third wafers are packaged together in a carrier, the carrier includes a rewiring layer, and the rewiring layer is electrically connected to the first target wafer among the plurality of first wafers, and It is electrically connected to the third target chip among the plurality of third chips.

Optionally, the carrier may include any one of a substrate wafer, a molding compound, or a packaging substrate.

In a possible embodiment, the carrier includes a substrate wafer, and a plurality of first accommodating structures and a plurality of second accommodating structures are fabricated on the substrate wafer. The accommodating structure is the same and is a groove or a through hole. The plurality of third chips are fixed in the plurality of second accommodating structures, and the upper surface of the plurality of third chips is not higher than the upper surface of the substrate wafer.

Optionally, if the second accommodating structure is a groove, a plurality of third wafers are placed and fixed in a plurality of second grooves. The method of placing and fixing may be the same as the method of placing the plurality of first wafers in the plurality of first grooves, and will not be repeated here.

Optionally, if the second accommodating structure is a through hole, the plurality of third chips can be fixed in the plurality of second through holes through the adhesive layer. In this case, the heat dissipation capability of the plurality of third chips can be improved.

After placing the plurality of first wafers in the plurality of first accommodating structures and the plurality of third wafers in the plurality of second accommodating structures, a rewiring layer is prepared on the first target wafer and the third target wafer, wherein The first target wafer may be any one of a plurality of first wafers, and the third target wafer corresponds to the first target wafer, and it may be a third wafer adjacent to the first target wafer. Each of the plurality of first wafers has a corresponding third wafer.

In another possible embodiment, the carrier further includes a plastic encapsulant, and the plurality of first chips and a plurality of third chips are encapsulated in the plastic encapsulant, wherein the upper surface of the plurality of first chips and the air Contact, and the upper surfaces of the plurality of first wafers are not higher than the upper surface of the molding compound, the upper surfaces of the plurality of third wafers are in contact with air, and the upper surfaces of the plurality of third wafers are not higher than the upper surface The upper surface of the molding compound.

In a third possible implementation manner, the carrier further includes a packaging substrate, the plurality of first chips and the plurality of third chips are packaged inside the packaging substrate, and the rewiring layer is prepared in the packaging substrate, wherein: The rewiring layer includes multiple metal circuit layers arranged horizontally and a plurality of interconnect structures arranged vertically.

Optionally, the packaging substrate may also be other types of circuit boards, such as PCB boards, etc. The technical solution for packaging the multiple chips on the packaging substrate can be referred to related descriptions in the prior art, which will not be repeated here.

In the embodiment of the present application, the third target wafer is electrically connected to the first target wafer through the rewiring layer. However, the third target chip redistributes its IO ports through the redistribution layer. In other words, the third target chip does not form a pad on the carrier unit to be electrically connected to the second target chip, that is, the third target chip is not directly connected to the second target chip. The second target chip is electrically connected.

Optionally, the third target chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for acquiring and storing electrical signals generated by the first target chip.

Optionally, the third target wafer may also be a dummy chip, which is used to balance the mechanical stress during the processing of the chip.

FIG. 39 is a schematic flow chart of another method for manufacturing a stacked chip.

As shown in FIG. 39, the manufacturing method 400 of the stacked chip includes:

S410: Divide a plurality of first wafers from the first wafer;

S420: Divide a plurality of third wafers from the third wafer;

S430: Package a plurality of first chips and a plurality of third chips in a carrier, the carrier includes a rewiring layer, and the rewiring layer is electrically connected to the first target chip and the third target chip.

S440: Prepare a first pad and a third pad above the rewiring layer, the first pad is electrically connected to the first target wafer through the rewiring layer, and the third pad is electrically connected to the third target wafer through the rewiring layer .

Specifically, the process of preparing the third bonding pad is similar to that of preparing the first bonding pad, and the third bonding pads are distributed in the surrounding area above the rewiring layer for electrical connection with the third target wafer.

S450: Prepare a second target chip on the second wafer, and separate the second target chip from the second wafer, where the second target chip includes a second pad and a fourth pad.

Specifically, the formation process of the fourth pad is the same as that of the second pad, and both are pads in the second metal circuit layer of the second target chip. The only difference lies in the fourth pad and the pad of the third target chip. The second pad is connected to the pad of the first target chip, and the second pad and the fourth pad can be used to output the same electrical signal.

S460: Weld the first pad and the second pad to electrically connect the first target chip and the second target chip, and weld the third pad and the fourth pad to electrically connect the third target chip and the second target chip.

S470: Cutting the entirety of the first target wafer, the second target wafer, and the third target wafer to obtain a stacked chip, wherein the surface area of the second target wafer is larger than the surfaces of the first target wafer and the third target wafer The sum of the area.

In the embodiment of the present application, the third target wafer is electrically connected to the first target wafer through the rewiring layer. And the third target chip redistributes its IO ports through the rewiring layer, and the third target chip is electrically connected to the second target chip by forming a third pad on the carrier unit on the wiring layer.

Optionally, the third target chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for acquiring and storing electrical signals generated by the first target chip and/or the second target chip.

As shown in FIG. 40, an embodiment of the present application further provides an image sensor 30, and the image sensor 30 may include the stacked chip 20 of the foregoing application embodiment.

Specifically, the stacked chip 20 is a stacked image sensor chip, which is used to receive optical signals and convert the optical signals to obtain electrical signals. Optionally, the stacked image sensor chip may undergo subsequent processing processes such as packaging. To form an image sensor, the image sensor 30 may also include other electrical, optical or mechanical elements, which are not limited in the embodiment of the present application.

As shown in FIG. 41, an embodiment of the present application further provides an electronic device 40, and the electronic device 40 may include the stacked chip 20 of the foregoing application embodiment.

Optionally, the stacked chip 20 may be an image sensor chip, which is applied to various mobile terminal shooting devices, such as front or rear cameras of mobile phones, digital cameras, and so on.

The electronic equipment may also include optical devices such as a lens and an optical path guiding structure.

It should be understood that the specific examples in the embodiments of the present application are only to help those skilled in the art to better understand the embodiments of the present application, rather than limiting the scope of the embodiments of the present application.

It should be understood that the terms used in the embodiments of the present application and the appended claims are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. For example, the singular forms of "a", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

A person of ordinary skill in the art may be aware that, in combination with the examples described in the embodiments disclosed herein, the units can be implemented by electronic hardware, computer software, or a combination of both, in order to clearly illustrate the interchangeability of hardware and software. In the above description, the composition and steps of each example have been described generally in terms of function. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed system and device may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present application.

In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be realized in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of this application is essentially or the part that contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium. It includes several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code .

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Anyone familiar with the technical field can easily think of various equivalents within the technical scope disclosed in this application. Modifications or replacements, these modifications or replacements shall be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

A stacked chip, characterized in that it comprises:

The carrier unit is provided with a first accommodating structure, and the first accommodating structure is a groove or a through hole;

The first chip is arranged in the first accommodating structure;

The rewiring layer is arranged above the first chip;

A first pad is disposed above the rewiring layer, and the first pad is electrically connected to the first chip through the rewiring layer;

The second chip is stacked above the carrier unit and the first chip, the second chip includes a second pad, and the second pad is electrically connected to the first pad, wherein the The surface area of the second wafer is greater than the surface area of the first wafer.
The chip of claim 1, wherein the surface area of the second wafer is smaller than the surface area of the carrier unit.
The chip according to claim 1 or 2, wherein the chip further comprises: a specific pad disposed above the rewiring layer, the specific pad passing through the rewiring layer and the first Chip electrical connection;

The specific pad is used to connect to the circuit board in the device where the chip is located through a wire.
3. The chip of claim 3, wherein the specific pad is located outside the projection of the second wafer in the vertical direction.
The chip according to any one of claims 1 to 4, wherein the stacked chip is an image sensor chip;

The second wafer is a pixel wafer, and the pixel wafer includes a pixel array for receiving optical signals and converting them into electrical signals;

The first chip is a logic chip, and the logic chip includes a signal processing circuit for processing the electrical signal.
The chip according to claim 5, wherein the second wafer further comprises a substrate, a first dielectric layer, and a second metal circuit layer;

The pixel array is formed in the substrate, the first dielectric layer is disposed on the surface of the substrate, and the second metal circuit layer is formed in the first dielectric layer;

The second metal circuit layer is electrically connected to the pixel array, and the second pad is disposed in the second metal circuit layer.
7. The chip of claim 6, wherein the second pad is disposed outside the projection of the pixel array in its vertical direction, and the first pad is located directly above the second pad .
The chip according to claim 6 or 7, wherein the second wafer has a back-illuminated structure, the pixel array is close to the bottom surface of the substrate, and the first dielectric layer is disposed on the bottom surface of the substrate. The lower surface of the substrate.
8. The chip of claim 8, wherein an opening is provided between the second metal circuit layer and the lower surface of the first dielectric layer to form the second metal circuit layer in the second metal circuit layer. Two pads.
9. The chip according to claim 9, wherein the second wafer further comprises: a second dielectric layer, and the second dielectric layer is disposed in a non-opening area on the lower surface of the first dielectric layer.
The chip according to claim 9, wherein the second wafer further comprises: a second dielectric layer, the second dielectric layer covering the lower surface of the first dielectric layer, and the second metal circuit layer An opening is provided between the lower surface of the second dielectric layer to form the second pad in the second metal circuit layer.
The chip according to claim 6 or 7, wherein the second wafer has a front-illuminated structure, the pixel array is close to the upper surface of the substrate, and the first dielectric layer is disposed on the The upper surface of the substrate;

An opening is provided between the second metal circuit layer and the lower surface of the substrate to form the second pad in the second metal circuit layer.
The chip according to any one of claims 6 to 12, wherein a bottom bump metallization layer is provided under the second pad, or a through-hole interconnection structure is provided, and the bump bottom metal Solder balls are arranged under the chemical layer or the through-hole interconnection structure.
The chip according to any one of claims 6 to 13, wherein the second wafer further comprises: an optical component disposed above the pixel array, the optical component comprising a filter layer and/or micro Lens array.
The chip according to claim 14, wherein the second chip further comprises a transparent cover plate, the transparent cover plate is arranged above the optical element, wherein the transparent cover plate and the optical element The space is air or a transparent medium layer.
The chip according to any one of claims 1 to 15, wherein the chip further comprises: a third dielectric layer and a fourth dielectric layer,

The third dielectric layer is disposed between the rewiring layer and the carrier unit, and is used to form a conductive channel to connect the rewiring layer and the first metal circuit layer of the first wafer;

The fourth dielectric layer is disposed between the first pad and the rewiring layer, and is used to form a conductive channel to connect the rewiring layer and the first pad.
The chip according to claim 16, wherein the chip further comprises a first thermally conductive metal layer, the first thermally conductive metal layer is disposed on the upper surface of the fourth dielectric layer, and the first thermally conductive metal layer It is located on the same horizontal plane as the first pad.
The chip according to any one of claims 1 to 17, wherein if the first accommodating structure is a groove, the chip further comprises: a second thermally conductive metal layer disposed on the first container At the bottom of the structure, the first wafer is disposed on the upper surface of the second thermally conductive metal layer, and the second thermally conductive metal layer is connected to the lower surface of the carrier unit through at least one thermally conductive metal structure.
The chip according to claim 18, wherein a third thermally conductive metal layer is further provided on the lower surface of the carrier unit, and the third thermally conductive metal layer is connected to the at least one thermally conductive metal structure.
The chip according to any one of claims 1 to 19, wherein a second accommodating structure is further provided in the carrier unit, and the second accommodating structure is a groove or a through hole;

The chip further includes: a third wafer, which is arranged in the second accommodating structure;

The second chip is stacked above the carrier unit, the first chip, and the third chip, and the second chip is electrically connected to the first bonding pad through a second bonding pad on the lower surface of the second chip , And the surface area of the second wafer is greater than the sum of the surface areas of the first wafer and the third wafer.
The chip according to claim 20, wherein the rewiring layer is disposed above the first wafer and the third wafer, and the third wafer passes through the rewiring layer and the first wafer. The chip is electrically connected.
The chip according to claim 21, wherein the chip further comprises: a third pad disposed above the rewiring layer, the third pad passing through the rewiring layer and the third pad. Chip electrical connection;

The second chip further includes a fourth pad, and the fourth pad is electrically connected to the third pad.
The chip according to any one of claims 20 to 22, wherein the third chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for storing the first chip And/or electrical signals generated by the second wafer.
22. The chip of claim 20, wherein the third wafer is a dummy chip for balancing mechanical stress during the processing of the chip.
The chip according to any one of claims 1 to 24, wherein the carrier unit is any one of a substrate, a molding compound, a package substrate, and a circuit board, wherein the material of the substrate is Any of silicon, glass, ceramics.
A method for manufacturing a stacked chip, which is characterized in that it comprises:

Singulate a plurality of first wafers from the first wafer;

Encapsulating the plurality of first chips in a carrier;

Preparing a rewiring layer over the plurality of first wafers;

Preparing a first pad above the rewiring layer, and the first pad is electrically connected to a first target wafer of the plurality of first wafers through the rewiring layer;

Preparing a plurality of second wafers on a second wafer, and dividing a second target wafer of the plurality of second wafers from the second wafer, the second target wafer including a second bonding pad;

Stacking the second target chip above the first target chip, and soldering the first pad and the second pad to electrically connect the first target chip and the second target chip;

The whole of the electrically connected first target wafer and the second target wafer are cut to obtain a stacked chip, wherein the surface area of the second target wafer is larger than the surface of the first target wafer area.
The manufacturing method according to claim 26, wherein the manufacturing method further comprises:

Preparing a specific pad above the rewiring layer, and the specific pad is electrically connected to the first target wafer through the rewiring layer;

The specific pad is used to connect to the circuit board in the device where the stacked chip is located through a wire.
The manufacturing method according to claim 26 or 27, wherein the carrier is a substrate wafer, and the packaging of the plurality of first chips in the carrier comprises:

Fabricating a plurality of first accommodating structures on the substrate wafer, and the first accommodating structures are grooves or through holes;

Fixing the plurality of first wafers in the plurality of first accommodating structures;

The rewiring layer is prepared above the substrate wafer on which the plurality of first wafers are fixed.
The manufacturing method according to claim 26 or 27, wherein the carrier is a plastic molding compound, and encapsulating the plurality of first chips in the carrier includes:

Encapsulating the plurality of first chips in the molding compound, wherein the upper surfaces of the plurality of first chips are in contact with air;

The rewiring layer is prepared on the plastic encapsulant in which the plurality of first chips are encapsulated.
The manufacturing method according to claim 26 or 27, wherein the carrier is a packaging substrate, and the packaging of the plurality of first chips in the carrier comprises:

Packaging the plurality of first chips inside the packaging substrate;

The rewiring layer is prepared in the packaging substrate, wherein the rewiring layer includes multiple horizontally arranged metal circuit layers and a plurality of vertically arranged interconnection structures.
The manufacturing method according to any one of claims 26 to 30, wherein the stacked chip is an image sensor chip, the second target wafer is a pixel wafer, and the second target wafer includes a pixel array , Used to receive optical signals and convert them into electrical signals;

The first target chip is a logic chip, and the first target chip includes a signal processing circuit for processing the electrical signal.
The manufacturing method according to claim 31, wherein the preparing a plurality of second wafers on the second wafer comprises:

Prepare the pixel array of the second target wafer in the second wafer, and prepare a first dielectric layer and a second metal circuit layer on the surface of the second wafer, wherein the second metal circuit layer Formed in the first dielectric layer, and the second metal circuit layer is electrically connected to the pixel array;

Preparing the second pad, and the second pad is formed in the second metal circuit layer;

An electrical connection device is prepared under the second pad.
The manufacturing method according to claim 32, wherein the second pad is formed outside the projection of the pixel array in its vertical direction.
The manufacturing method according to claim 32 or 33, wherein the second target chip has a back-illuminated structure, and the pixel array of the second target chip is prepared in the second wafer, and Preparing a first dielectric layer and a second metal circuit layer on the surface of the second wafer includes:

Preparing the pixel array at the lower part of the second wafer, the pixel array being close to the lower surface of the second wafer;

The first dielectric layer and the second metal circuit layer are prepared on the lower surface of the second wafer.
The manufacturing method according to claim 34, wherein the manufacturing method further comprises:

Bonding the second wafer on the substrate wafer by using a wafer bonding process;

The upper surface of the second wafer is thinned, wherein the pixel array is close to the upper surface of the second wafer after the thinning process.
The manufacturing method according to claim 35, wherein the manufacturing method further comprises:

A transparent cover is arranged above the pixel array as a supporting structure, and the lower surface of the substrate wafer is thinned until the second metal circuit layer is close to the lower surface of the substrate wafer.
The manufacturing method according to claim 35 or 36, wherein the preparing the second bonding pad comprises:

The lower surface of the substrate wafer is etched to form an opening, and the opening is connected to the second metal circuit layer to form the second pad in the second metal circuit layer.
The manufacturing method according to claim 35, wherein the manufacturing method further comprises:

A transparent cover is arranged above the pixel array as a supporting structure, and the lower surface of the substrate wafer is thinned to completely remove the substrate wafer.
The manufacturing method according to claim 38, wherein the preparing the second bonding pad comprises:

The lower surface of the first dielectric layer is etched to form an opening, and the opening is connected to the second metal circuit layer to form the second pad in the second metal circuit layer.
The manufacturing method according to claim 32 or 33, wherein the second target wafer has a front-illuminated structure, and the pixel array of the second target wafer is prepared in the second wafer, and the The preparation of a first dielectric layer and a second metal circuit layer on the surface of the second wafer includes:

Preparing the pixel array on the upper part of the second wafer, the pixel array being close to the upper surface of the second wafer;

The first dielectric layer and the second metal circuit layer are prepared on the upper surface of the second wafer.
The manufacturing method of claim 40, wherein the preparing the second bonding pad comprises:

The lower surface of the second wafer is etched to form an opening, and the opening is connected to the second metal circuit layer to form the second pad in the second metal circuit layer.
The manufacturing method according to any one of claims 32 to 41, wherein the preparing an electrical connection device under the second bonding pad comprises:

Preparing a bottom bump metallization layer or a via interconnection structure under the second pad,

A solder ball is prepared under the metallization layer of the bottom bump of the bump or the through-hole connection structure.
The manufacturing method according to any one of claims 32 to 42, wherein after the pixel array of the second target wafer is prepared in the second wafer, the manufacturing method further comprises:

An optical component is prepared above the pixel array, and the optical component includes: a filter layer and/or a microlens array.
The manufacturing method according to any one of claims 26 to 43, wherein the manufacturing method further comprises:

Divide a plurality of third wafers from the third wafer;

Packaging the plurality of third chips together with the plurality of first chips in the carrier, and the rewiring layer is electrically connected to a third target chip among the plurality of third chips;

Cutting the entirety of the first target wafer, the second target wafer, and the third target wafer to obtain a stacked chip;

Wherein, the surface area of the second target wafer is greater than the sum of the surface areas of the first target wafer and the third target wafer.
The manufacturing method according to claim 44, wherein the third wafer is electrically connected to the first wafer through the rewiring layer.
The manufacturing method according to claim 45, wherein the manufacturing method further comprises:

Preparing a third pad above the rewiring layer, and the third pad is electrically connected to the third target wafer through the rewiring layer;

Soldering the third pad and the fourth pad of the second chip to electrically connect the third target chip and the second target chip.
The manufacturing method according to any one of claims 44 to 46, wherein the third target chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for storing the first An electrical signal generated by a target wafer and/or the second target wafer.
The manufacturing method according to claim 44, wherein the third target wafer is a dummy chip, which is used to balance mechanical stress during the processing of the chip.
An image sensor, characterized by comprising: the stacked chip according to any one of claims 1-25.
An electronic device, characterized by comprising: the stacked chip according to any one of claims 1-25.