WO2021092777A1

WO2021092777A1 - Stacked chip, manufacturing method, image sensor, and electronic device

Info

Publication number: WO2021092777A1
Application number: PCT/CN2019/117674
Authority: WO
Inventors: 姚国峰; 沈健
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2019-11-12
Filing date: 2019-11-12
Publication date: 2021-05-20
Also published as: CN110945660A; CN110945660B

Abstract

A stacked chip, a manufacturing method, and an electronic device, capable of reducing the manufacturing cost of the stacked chip. The stacked chip comprises: a carrier wafer 200 formed with a first recess 201; a first wafer 210 arranged in the first recess 201; and a second wafer 220 stacked on the first wafer 210 and the carrier wafer 200. The surface area of the second wafer 220 is larger than the surface area of the first wafer 210; a redistribution layer is arranged between the second wafer 220 and the first wafer 210, and the second wafer 220 is electrically connected to the first wafer 210 by means of the redistribution layer. According to the method, the first recess in the carrier wafer supports and stabilizes the first wafer, and the second wafer having a larger area is stacked on the first wafer having a smaller area, so that the first wafers having smaller areas can be manufactured on the wafer as many as possible while a stacked chip structure is achieved, the cost of a single first wafer is reduced, and thus the total manufacturing cost is reduced.

Description

Stacked chip, manufacturing method, image sensor and electronic device

Technical field

This application relates to the field of semiconductor chips, and more specifically, to a stacked chip, a manufacturing method, an image sensor, and an electronic device.

Background technique

With the development of semiconductor and integrated circuit technology, chip device types are becoming more and more abundant, and the integration degree is getting higher and higher. On the two-dimensional plane, as the semiconductor technology develops to a certain extreme degree, the performance of the chip cannot be further improved. Therefore, a three-dimensional stacking concept is currently proposed in the industry to expand the chip from two-dimensional to three-dimensional, that is, chip modules with different functions are stacked on top of each other for packaging, thereby improving the overall performance and yield of the chip.

In one implementation, the upper die and the lower die are stacked together in a wafer-to-wafer manner through a wafer-level bonding process (Wafer-level Bonding Process) to form a stacked Three-dimensional chip. In order to meet the stacking process requirements, the upper and lower wafers have the same wafer size, and the number of upper wafers on the upper wafer is equal to the number of wafers on the lower wafer, but when the upper and lower wafers are not the same type of wafers, This stacking method will cause a waste of wafer area and increase the manufacturing cost of stacked chips.

Therefore, how to reduce the manufacturing cost of stacked chips is an urgent problem to be solved.

Summary of the invention

The embodiments of the present application provide a stacked chip, a manufacturing method, an image sensor, and an electronic device, which can reduce the manufacturing cost of the stacked chip.

In the first aspect, a stacked chip is provided, including:

A carrier wafer with a first groove provided therein;

The first wafer is set in the first groove;

A second wafer stacked on top of the carrier wafer and the first wafer, and the surface area of the second wafer is larger than the surface area of the first wafer;

A rewiring layer located between the second wafer and the first wafer, and the second wafer is electrically connected to the first wafer through the rewiring layer.

In the embodiment of the present application, the first groove in the carrier wafer provides support and stability for the first wafer, so that a large-area second wafer can be stacked on a small-area first wafer, so that a stacked chip structure can be realized. At the same time, it is also possible to manufacture as many small-area first chips as possible on the wafer, reducing the cost of a single first chip, thereby reducing the overall manufacturing cost of the chip.

In a possible implementation manner, the stacked chip is an image sensor chip;

The second chip is a pixel chip, and the pixel chip includes a pixel array for receiving optical signals and converting them into electrical signals;

The first chip is a logic chip, and the logic chip includes a signal processing circuit for processing the electrical signal.

In the technical solution of the embodiment of the present application, the signal processing circuit in the image sensor chip and the pixel circuit are arranged separately, which can increase the photosensitive area on the pixel wafer in the image sensor chip, thereby reducing the cost of the stacked image sensor chip. At the same time, the performance of the image sensor can also be improved.

In a possible implementation, the surface area of the carrier wafer is equal to the surface area of the second wafer, and a stack is formed between the second wafer and the first wafer through wafer-level bonding.

By adopting the technical solution of the embodiment of the present application, in the manufacturing process, the stacked chip can be prepared by a wafer-level bonding process, and before the wafer-level bonding is performed, a single first chip and the on-wafer The second wafer is tested to screen out wafers with good performance and remove the wafers with poor performance to improve the overall chip yield and further reduce the overall manufacturing cost.

In a possible implementation manner, the rewiring layer is provided with a plurality of first electrical connection points electrically connected to each row of pixel units in the pixel array, and the position distribution of the plurality of first electrical connection points is consistent with that of the pixel. The position distribution of a column of pixel units in the array is consistent; and/or, the rewiring layer is provided with a plurality of second electrical connection points electrically connected to each column of pixel units in the pixel array, The position distribution is consistent with the position distribution of a row of pixel units in the pixel array.

Through the solution of the embodiment of the present application, only the pixel array circuit is retained in the pixel array, and all other control circuits are arranged in the logic chip. Through the electrical connection of the rewiring layer, the logic chip is realized to each row and the pixel array in the pixel array. The control of each column of pixels can further increase the photosensitive area of the image sensor chip.

In a possible embodiment, the chip further includes a filling layer disposed between the first wafer and the first recess, the upper surface of the carrier wafer, and the upper surface of the first wafer. An area outside the metal circuit layer;

Wherein, the filling layer is used to fix the first wafer in the first groove, and the first metal circuit layer is the circuit layer of the first wafer.

In a possible implementation, the rewiring layer is disposed on the filling layer and the upper surface of the first metal circuit layer, and is used to electrically connect the first metal circuit layer and the second wafer.

In a possible implementation, the chip further includes an insulating dielectric layer covering the rewiring layer and the filling layer, and the upper surface of the insulating dielectric layer is bonded to the lower surface of the second wafer Together.

In a possible implementation, the filling layer is a dry film material layer that can be used for photolithography.

In a possible embodiment, the chip further includes a through-hole interconnection structure, and the through-hole interconnection structure is used to electrically connect the second wafer and the first wafer.

In a possible embodiment, the second chip includes a second metal circuit layer and a top metal circuit layer, wherein the second metal circuit layer is located inside the second chip, and the top metal circuit layer is located on the second chip. The upper surface of

The first via interconnection structure in the via interconnection structure connects the top metal circuit layer and the rewiring layer, and the second via interconnection structure in the via interconnection structure connects the top metal circuit layer and the The second metal circuit layer, wherein the rewiring layer is electrically connected to the circuit layer of the first chip.

In a possible embodiment, the chip further includes a first adhesive layer disposed on the lower surface of the first chip, and the first adhesive layer is used to bond the first chip to the first chip. In a groove.

In a possible embodiment, the upper surface of the first wafer is not higher than the upper surface of the carrier wafer.

In a possible implementation manner, a second groove is further provided in the carrier wafer, and the chip further includes: a third wafer, and the third wafer is provided in the second groove;

The second chip is stacked above the first chip, the third chip, and the carrier chip, and the surface area of the second chip is larger than the sum of the surface areas of the first chip and the third chip.

In the technical solution of the embodiment of the present application, by arranging both the first wafer and the third wafer in the groove of the carrier wafer, the second wafer with a large area is stacked on top of the first wafer and the third wafer. At the same time, as many first and third wafers as possible can be grown on the wafer, reducing manufacturing costs.

In a possible embodiment, the third chip, the first chip and the second chip are stacked by wafer-level bonding.

In the technical solution of the embodiment of the present application, the space in the stacked chips can be fully utilized, and the second wafer can be bonded on top of the first and third wafers by a single wafer bonding process, instead of using two wafers. In the circular bonding process, three wafers are bonded sequentially, thereby further reducing the process cost. In addition, before wafer-level bonding, a single first wafer and a single third wafer can be tested to screen out wafers with good performance, remove the wafers with poor performance, and improve the quality of the overall chip. Rate, further reducing the overall manufacturing cost.

In a possible implementation manner, the first wafer is electrically connected to the third wafer through the rewiring layer, and the second wafer is electrically connected to the third wafer through a via interconnection structure.

In a possible implementation, the third chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for storing electrical signals generated by the first chip and/or the second chip.

Through the solution of the embodiment of the present application, the memory chip can be integrated into the stacked chip, the signal processing capability and processing speed of the chip can be improved, and the chip performance can be further optimized.

In a possible implementation manner, the second wafer is a pixel wafer in an image sensor chip, the pixel array of the pixel wafer is close to the upper surface of the pixel wafer, and a filter layer and/or a light filter layer are disposed on the pixel array. Micro lens array.

Through the solution of the embodiment of the present application, the pixel array in the pixel wafer is close to the upper surface of the pixel wafer, and the pixel wafer is a back-illuminated image sensing structure, which can increase the intensity of the light signal received by the pixel array.

In a possible implementation, the material of the carrier wafer is any one of silicon, glass, and ceramic.

In a second aspect, a method for manufacturing a stacked chip is provided, including:

Making a plurality of first grooves on the carrier wafer;

Dividing a plurality of first chips from the first wafer, and fixing the plurality of first chips in the plurality of first grooves of the carrier wafer;

Preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed;

Stacking the second wafer on top of the carrier wafer on which the rewiring layer is made;

Electrically connecting the plurality of second chips in the second wafer after the stack to the plurality of first chips through the rewiring layer;

Cutting the electrically connected second wafer and the whole of the first wafer to obtain a plurality of stacked chips;

Wherein, the plurality of second wafers correspond to the plurality of first wafers one-to-one, and are respectively stacked above the plurality of first wafers, and the surface area of each second wafer of the plurality of second wafers is larger than the The surface area of each first wafer in the plurality of first wafers.

In the embodiment of the present application, the first groove in the carrier wafer provides support and stability for a plurality of first wafers, and a second wafer including a plurality of second wafers is stacked on the carrier wafer, thereby realizing a large area The second chip is stacked on the small-area first chip. While realizing the stacked chip structure, it is also possible to manufacture as many small-area first chips on the wafer as possible, reducing the cost of a single first chip, thereby reducing The overall manufacturing cost.

In a possible implementation manner, the stacking the second wafer on the carrier wafer on which the rewiring layer is formed includes:

The second wafer is bonded above the carrier wafer on which the rewiring layer is formed by using a wafer bonding process, wherein the surface area of the second wafer is equal to the surface area of the carrier wafer.

Through the implementation of this application, the wafer bonding process is used to bond two types of wafers of different sizes. Before bonding, a single first wafer and multiple second wafers on the second wafer are tested to The wafers with good performance are screened out, and the wafers with poor performance are removed, so as to improve the yield of the overall chip and further reduce the overall manufacturing cost.

In a possible implementation, the stacked chip is an image sensor chip, the plurality of second chips are pixel chips, and each of the plurality of second chips includes a pixel array for receiving optical signals and converting them into electrical signals ；

The plurality of first chips are logic chips, and each of the plurality of first chips includes a signal processing circuit for processing the electrical signal.

In a possible implementation manner, after stacking the second wafer on the carrier wafer on which the rewiring layer is formed, the manufacturing method further includes:

Thinning the upper surface of the second wafer;

Wherein, the pixel arrays of the plurality of second wafers in the second wafer are close to the upper surface of the second wafer after the thinning process.

In a possible implementation manner, after the upper surface of the second wafer is thinned, the manufacturing method further includes: preparing filters on the pixel arrays of the plurality of second wafers in the second wafer. Layer and/or micro lens array.

Compared with the chip-to-wafer bonding method, the solution of the embodiment of the present application can reduce the process procedure and reduce the process cost without affecting the overall performance of the pixel chip.

In a possible implementation, after fixing the plurality of first wafers in the plurality of first grooves of the carrier wafer, the manufacturing method further includes:

Filling the gaps between the plurality of first dies and the plurality of first recesses and the upper surface of the carrier wafer with a filling material;

The filling material is heated in a vacuum environment to form a stable filling layer.

In a possible implementation manner, the preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed includes:

Windowing is performed on the filling layer to remove the local filling layer above the plurality of first metal circuit layers on the upper surface of the plurality of first wafers, wherein the plurality of first metal circuit layers are in the plurality of first wafers的线层;

The rewiring layer is prepared above the filling layer and the plurality of first metal circuit layers, and the rewiring layer is used to electrically connect the plurality of first metal circuit layers and the plurality of second chips in the second wafer.

Preparing an insulating dielectric layer above the rewiring layer and the filling layer, and the insulating dielectric layer is used to cover the rewiring layer and the filling layer;

A wafer bonding process is used to bond the upper surface of the insulating dielectric layer and the lower surface of the second wafer.

In a possible implementation manner, the bonding the upper surface of the insulating dielectric layer and the lower surface of the second wafer using a wafer bonding process includes:

The upper surface of the insulating dielectric layer and the lower surface of the second wafer are planarized, wherein the flatness of the upper surface of the insulating dielectric layer and the lower surface of the second wafer after the planarization is equal to that of the lower surface of the second wafer. /Or the roughness meets the preset threshold;

The upper surface of the insulating dielectric layer is attached to the lower surface of the second wafer, and high-temperature annealing is performed to bond the upper surface of the insulating dielectric layer and the lower surface of the second wafer.

In a possible embodiment, the filling material is a dry film material that can be used for photolithography.

In a possible implementation, the fixing the plurality of first wafers in the plurality of first grooves of the carrier wafer includes:

Placing the plurality of first wafers into the plurality of first grooves through a pick-and-place process;

Wherein, the lower surfaces of the plurality of first wafers are respectively provided with a first adhesive layer, and the lower surfaces of the plurality of first wafers are bonded in the plurality of first grooves through the first adhesive layer.

In a possible implementation manner, the upper surfaces of the plurality of first wafers are not higher than the upper surface of the carrier wafer.

In a possible implementation manner, electrically connecting the plurality of second chips in the second wafer after the stack to the plurality of first chips through the rewiring layer includes:

A plurality of through-hole interconnection structures are prepared in the stacked second wafers and the plurality of first wafers, and the through-hole interconnection structures are used to connect a plurality of second metal layers through a plurality of top metal wiring layers. The circuit layer is electrically connected to the rewiring layer;

Wherein, the rewiring layer is electrically connected to the circuit layers of the plurality of first wafers, the plurality of second metal circuit layers are circuit layers in the plurality of second wafers, and the plurality of top metal circuit layers are disposed on the plurality of circuit layers. The upper surface of a second wafer.

In a possible implementation manner, before preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed, the manufacturing method further includes:

Forming a plurality of second grooves on the carrier wafer, and the plurality of second grooves and the plurality of first grooves are located on the same surface of the carrier wafer;

Dividing a plurality of third chips from the third wafer, and fixing the plurality of third chips in the plurality of second grooves of the carrier wafer;

The preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed includes:

Preparing the rewiring layer on the carrier wafer on which the plurality of first chips and the plurality of third chips are fixed;

After stacking the second wafer on the carrier wafer on which the rewiring layer is formed, the manufacturing method further includes:

Electrically connecting the plurality of second chips in the second wafer after the stack to the plurality of third chips through the rewiring layer;

Wherein, the plurality of second chips correspond to the plurality of third chips one-to-one, the plurality of second chips are stacked above the plurality of first chips, the plurality of third chips, and the carrier wafer, and the The surface area of each second wafer in the plurality of second wafers is greater than the sum of the surface area of a first wafer in the plurality of first wafers and a third wafer in the plurality of third wafers.

In a possible implementation manner, the plurality of first wafers are electrically connected to the plurality of third wafers through the rewiring layer, and the plurality of second wafers are electrically connected to the plurality of third wafers through a plurality of through-hole interconnect structures. The chip is electrically connected.

In a possible implementation manner, the plurality of third chips are a plurality of memory chips, and include a storage circuit for storing electrical signals generated by the plurality of first chips and/or the plurality of second chips.

In a possible implementation manner, the substrate material of the carrier wafer is any one of silicon, glass, and ceramic.

In a third aspect, an image sensor is provided, including: a stacked chip as in the first aspect or any possible implementation of the first aspect.

In a fourth aspect, an electronic device is provided, including: a stacked chip as in the first aspect or any possible implementation of the first aspect.

By arranging the above-mentioned stacked chips in the image sensor or the electronic device, the manufacturing cost of the chip is reduced, thereby reducing the overall manufacturing cost of the image sensor or the electronic device.

Description of the drawings

1 to 3 are schematic structural diagrams of three complementary metal oxide semiconductor image sensor chips according to embodiments of the present application.

FIG. 4 is a schematic distribution diagram of a plurality of pixel wafers on a pixel wafer according to an embodiment of the present application.

FIG. 5 is a schematic distribution diagram of a plurality of logic chips on a logic wafer according to an embodiment of the present application.

FIG. 6 is a schematic diagram of the split structure of a stacked chip according to an embodiment of the present application.

Fig. 7 is a schematic cross-sectional view of a stacked chip according to an embodiment of the present application.

Fig. 8 is a schematic cross-sectional view of another stacked chip according to an embodiment of the present application.

FIG. 9 is a schematic diagram of the split structure of another stacked chip according to an embodiment of the present application.

Fig. 10 is a schematic cross-sectional view of another stacked chip according to an embodiment of the present application.

Fig. 11 is a schematic flow chart of a method for manufacturing a stacked chip according to an embodiment of the present application.

FIG. 12 is a schematic distribution diagram of a plurality of first grooves on a carrier wafer according to an embodiment of the present application.

FIG. 13 is a schematic flow chart of another method for manufacturing a stacked chip according to an embodiment of the present application.

14 to 20 are partial cross-sectional views of a wafer after multiple process steps according to an embodiment of the present application.

FIG. 21 is a schematic flowchart of another method for manufacturing a stacked chip according to an embodiment of the present application.

Fig. 22 is a schematic structural block diagram of an image sensor implemented according to the present application.

Fig. 23 is a schematic structural block diagram of an electronic device implemented according to the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

It should be understood that the specific examples in this document are only to help those skilled in the art to better understand the embodiments of the present application, rather than limiting the scope of the embodiments of the present application.

It should also be understood that, in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not correspond to the embodiments of the present application. The implementation process constitutes any limitation.

It should also be understood that the various implementation manners described in this specification can be implemented individually or in combination, which is not limited in the embodiments of the present application.

The technical solutions of the embodiments of the present application can be applied to various chips, such as memory chips, processing chips, sensor chips, etc., which are not limited in the embodiments of the present application.

Optionally, the technical solution of the embodiment of the present application may be applied to various image sensor chips, such as a biometric image sensor or an image sensor in a photographing device, but the embodiment of the present application is not limited thereto.

As a common application scenario, the chip provided in the embodiments of the present application can be used in mobile terminals such as smart phones, cameras, and tablet computers, or in other electronic devices such as servers and supercomputers.

Figures 1 to 3 show schematic structural diagrams of three complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensor chips 10. The CMOS image sensor chip is a sensor chip that can convert optical images into digital signals. , It is widely used in various fields such as digital products, mobile terminals, security monitoring and scientific research industry. As a common application scenario, the image sensor chip 10 provided in the embodiment of the present application can be applied to a photographing device of an electronic device, for example, a front or rear camera of a mobile phone.

FIG. 1 shows a schematic structural diagram of a conventional image sensor chip 10. As shown in FIG. 1, the image sensor chip 10 is manufactured on a single wafer 100. The image sensor 10 on the wafer 100 can be roughly divided into two areas: a pixel array area 110 and a processing circuit area 120. Wherein, the pixel array area 110 includes a pixel array composed of a plurality of CMOS pixel units for receiving light signals and converting the light signals into corresponding electrical signals. The total number of pixels in the pixel array area 110 of the image sensor 10 is one of the main technical indicators for measuring the image sensor, which determines the photosensitive performance, resolution and other factors of the image sensor. Therefore, it generally occupies a larger area and is optional. Ground, the pixel array area 110 occupies more than 70% of the area of the entire wafer 100. In the pixel array area 110, each pixel unit is composed of a photo-diode (PD) and one or more CMOS switch tubes. Therefore, the pixel array area 110 has fewer device types, relatively simple circuit structure, and device process requirements. Relatively low, for example, the 65nm process can meet the design requirements of the pixel array area.

In addition, the processing circuit area 120 may include a control circuit for controlling the pixel array, a signal processing circuit for processing electrical signals generated by the pixel array, an analog-to-digital conversion circuit, a digital processing circuit and other functional circuits for working with the pixel array to generate digital images. signal. The processing circuit area 120 occupies a small area on the entire wafer 100, but in these functional circuits, such as digital processing circuits, due to the need to implement more complex functions, the circuit structure is relatively complex, the device types are many and the integration is high, so The process requirements are relatively high. For example, processes of 45nm and below are required to meet the design requirements of functional circuits, and the processing costs of these processes are higher.

FIG. 2 shows a schematic structural diagram of a stacked image sensor chip 10. As shown in FIG. 2, the image sensor chip 10 is formed by stacking two upper and lower wafers. The pixel array area 110 is located on the first wafer 101 and is used to obtain optical signals and convert them into electrical signals. The second wafer 102 contains a processing circuit area 120 composed of a large number of analog and digital circuits, including a signal processing circuit and a control circuit, the signal processing circuit is used to process electrical signals, and the control circuit is used to control the pixel array Pixel work. Optionally, the first chip 101 may be called a pixel die, and the corresponding wafer may be called a pixel wafer; and the second chip 102 may be called a logic die. The corresponding wafer is called logic wafer (Logic Wafer) or image signal processing wafer (Image Signal Processing Wafer, ISP Wafer). Among them, the shape and size of the pixel chip and the logic chip are exactly the same. During the stacking process, the pixel chip and the logic chip are completely overlapped in the vertical direction.

FIG. 3 shows a schematic structural diagram of another stacked image sensor chip 10. As shown in FIG. 3, the image sensor chip 10 is formed by stacking three layers of wafers, and from top to bottom are the pixel wafer 101, the memory wafer 103, and the logic wafer 102, respectively. The shapes and sizes of the three types of wafers are completely the same. During the stacking process, the pixel wafer 101, the logic wafer 102, and the memory wafer 103 completely overlap in the vertical direction. The memory chip 103 includes a storage circuit 130 for storing electrical signals generated by the pixel array and/or processing circuit. Optionally, the circuit structure of the memory circuit is relatively complicated, the integration is high, and the line width and line spacing are small. Therefore, a higher process is also required for manufacturing.

Optionally, the storage circuit may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) circuit. It should be understood that the storage circuit may also be other types of storage circuits, such as other random access memory (RAM) circuit or read only memory (ROM) circuit, which is not done in the embodiment of the application. Any restrictions.

Compared with the non-stacked structure in Figure 1, the stacked image sensor in Figures 2 and 3 has three advantages: First, the pixel array area and the processing circuit area will not occupy each other's space, so more can be placed Pixels, improve the photosensitive performance, resolution and so on of the image sensor. The second is that logic wafers can be made with more advanced process nodes, which will increase transistor density and computing power, so that stacked image sensor chips can provide more functions, such as hardware high dynamic range imaging (High Dynamic Range Imaging). , HDR), slow motion shooting, etc. The third is that the storage function can be integrated in the image sensor to achieve faster data reading speed. Therefore, stacked image sensors currently dominate high-end image sensors.

With reference to Figures 1 to 3 above, taking the traditional non-stacked image sensor chip and the stacked image sensor chip as an example, the structure and performance differences between the two are compared. It should be understood that chips in other fields, such as memory chips, The processor chip, etc. can also adopt the traditional non-stacked structure and the stacked structure. Compared with the non-stacked structure, the memory chips and processor chips that adopt the stacked structure also have their own advantages, such as more Large storage space, faster processing speed and smaller size, etc.

However, at present, when two layers of wafers are stacked together in a wafer-to-wafer (W2W) manner through a wafer-level bonding process, multiple dies on the two-layer wafers correspond one-to-one , And the size of the corresponding wafers in the two layers of wafers is the same. This method is used to facilitate the process of wafer alignment, and the bonding accuracy is high. However, when the structure and function of the circuits on the two layers of wafers are different, the areas of the circuits grown on the corresponding two wafers of the same area are different, so that the area of a certain layer of wafers in the two layers of wafers is not fully utilized , Increased manufacturing costs. In addition, in the wafer bonding process, a bad chip on one wafer may be forcibly bonded to a good chip on another wafer, which affects the yield rate and also causes an increase in manufacturing costs.

For example, as shown in FIG. 4, a plurality of pixel wafers 101 are prepared on the pixel wafer 11, and each pixel wafer includes a pixel array area 110, and most of the area in the pixel wafer 101 is occupied by the pixel array area 110. As shown in FIG. 5, the shape and size of the logic wafer 12 and the pixel wafer 11 are exactly the same, and a plurality of logic wafers 102 are prepared on the logic wafer 12. The plurality of logic wafers 102 have the same size and correspond to the plurality of pixel wafers 101 one-to-one. When the pixel wafer 11 and the logic wafer 12 are bonded at the wafer level, alignment is performed by markings around the wafer, and the pixel wafer 11 is stacked on the logic wafer 12, and the two are completely overlapped in the vertical direction. Each pixel wafer in the pixel wafer 11 is aligned with a logic wafer in the logic wafer 12, so that one pixel wafer is aligned and bonded Above a logic chip. Each logic chip 102 includes a processing circuit area 120. Only part of the area of the logic chip 102 is occupied by the processing circuit area 120. Therefore, part of the space on the logic wafer 102 is wasted. In addition, part of the failed or faulty chips on the pixel wafer 11 and the logic wafer 12 may be forcibly bonded to a good chip, resulting in chip failure after bonding and affecting the overall yield.

Similarly, if the stacked image sensor chip includes a memory chip, the wafer corresponding to the memory chip is a memory wafer, and the distribution of the chips on the memory wafer is similar to the distribution of the logic chips on the logic wafer 12 in FIG. The shape and size of the wafer, the pixel wafer and the logic wafer are exactly the same. When the wafer is bonded, the memory wafer is stacked on top of the logic wafer, and the pixel wafer is stacked on top of the memory wafer. The three are in the vertical direction. They are completely overlapped, and one pixel chip in the pixel wafer, one memory chip in the memory wafer, and one logic chip in the logic wafer are in one-to-one correspondence. Only part of the memory chip area is also occupied by the storage circuit, causing some space on the memory wafer to be wasted. The failure of the memory chip after forced bonding affects the overall yield, and the bonding of the three-layer wafer will also increase manufacturing Cost. For example, in the prior art, three layers of wafers with the same area are usually stacked through two wafer-level bonding, which will increase the process of bonding once, which will further increase the manufacturing process and manufacturing cost of the chip.

In addition, in another chip-to-wafer (C2W) bonding process, a plurality of pixel wafers are grown on the pixel wafer, and a microlens array is formed on the upper surface of the microlens array. On the upper surface of the pixel wafer. After multiple logic chips are prepared on the logic wafer, the multiple logic chips are cut, and then the multiple logic chips are bonded to the bottom surface of the pixel wafer. At this time, the pixel wafer needs to be placed upside down. That is, the upper surface provided with the micro lens array faces downwards and the lower surface faces upwards, so that electrical connections between a plurality of small logic chips and pixel wafers can be realized. Therefore, it is necessary to provide a temporary substrate with temporary bonding glue above the microlens array to facilitate the electrical connection between the logic chip and the pixel wafer. After the logic chip and the pixel wafer are connected, the bonding glue on the surface of the microlens array is removed, but there may be glue residue during the removal process, which affects the performance of the pixel chip, thereby affecting the yield and overall performance of the chip. In addition, due to the increase of the process in the chip manufacturing process, the cost of the chip will also increase.

Based on the above-mentioned problems, this application proposes a stacked chip structure. By making full use of the size of the wafer, more wafers are prepared, and wafer-level bonding of wafers of different sizes is performed, so as to achieve stacked chips at the same time. , To reduce the cost of a single wafer, thereby reducing the overall manufacturing cost of stacked chips. In addition, there is no need to set temporary bonding glue and remove the temporary bonding glue during the bonding process, which will not bring additional process costs, and will not affect the performance of the optical devices in the chip.

FIG. 6 shows a schematic diagram of the split structure of a stacked chip according to an embodiment of the present application.

As shown in FIG. 6, the stacked chip 20 includes:

A carrier wafer 200, in which a first groove 201 is provided;

The first wafer 210 is arranged in the first groove 201;

The second wafer 220 is stacked above the first wafer 210 and the carrier wafer 200, and the surface area of the second wafer 220 is larger than the surface area of the first wafer 210.

Specifically, the first wafer 210 and the second wafer 220 have a sheet-like structure, and therefore, have a small thickness. The surface area of the first wafer 210 is the upper surface area or the lower surface area of the first wafer 210. Generally speaking, the upper surface area and the lower surface area of the first wafer 210 are equal. Similarly, the surface area of the second wafer 220 is also the upper surface area or the lower surface area of the first wafer 210.

Specifically, the carrier wafer 200 is a substrate wafer with a thickness greater than that of the first wafer 210, and the carrier wafer 200 is used to carry the first wafer 210 and the second wafer 220. The carrier wafer may be silicon, glass, Ceramics or other arbitrary materials are not limited in the embodiments of the present application. In a possible implementation, the carrier wafer 200 is monocrystalline silicon.

Optionally, in the embodiment of the present application, the above-mentioned first chip 210 and the second chip 220 are used to implement different circuit functions. For example, if the stacked chip 20 is an image sensor chip, the first chip 210 may It is the pixel chip 101 in FIG. 1 described above, and the second chip 220 may be the logic chip 102 or the memory chip 103 in FIG. 1 described above. If the second chip 220 is a logic chip, the second chip includes a processing circuit area 120 composed of a large number of analog and digital circuits, including a signal processing circuit and a control circuit, and the signal processing circuit is used to process electrical signals , The control circuit is used to control the work of the pixels in the pixel array.

Optionally, if the stacked chip 20 is a processor chip, the first chip 210 may be a central processing unit (CPU) chip, and the second chip 220 may be a graphics processing unit (GPU) chip , Or other control processing wafers. It should be understood that the stacked chip 20 may be chips in a variety of different fields, in which the first chip and the second chip are functional chips that implement corresponding circuit functions, and the circuit functions of the first chip and the second chip are different.

Optionally, the shape and size of the first groove 201 in the carrier wafer 200 may be the same as or slightly larger than the shape and size of the first wafer 210. In other words, the shape and size of the first groove 201 in the carrier wafer 200 The cross-sectional area may be the same as or slightly larger than the surface area of the first wafer 210. For example, the first wafer 210 has a sheet structure, the depth of the first groove 201 is the same as the thickness of the first wafer 210 or slightly larger than the thickness of the first wafer 210, and the length and width of the first groove 201 are also It is slightly larger than the length and width of the first wafer 210 respectively, so that the first groove 201 can completely accommodate the first wafer 210 therein. Optionally, the length, width, and depth of the first groove 201 are 25 μm larger than the length, width, and height of the first wafer 210 respectively, or any other value, which is not limited in the embodiment of the present application.

Since the surface area of the second wafer 220 is larger than the surface area of the first wafer 210, when the second wafer 220 needs to be stacked on the first wafer 210, a supporting structure is required. For example, the carrier wafer 200 in the embodiment of the present application is the first wafer. The first wafer 210 and the second wafer 220 provide support. Therefore, when the second wafer 220 is stacked on the first wafer 210, the second wafer 220 is also stacked on the carrier wafer 200. Optionally, the second chip 220 may be stacked on the first chip 210 through a wafer-level bonding process.

Optionally, in addition to the above-mentioned method of disposing the second wafer 220 in the first groove of the carrier wafer 200, the second wafer 220 may also be directly bonded and fixed on the carrier wafer 200, or the second wafer 220 may be fixed by other fixing methods. The two wafers 220 are stably fixed on the carrier wafer 200, which is not limited in the embodiment of the present application.

Optionally, a re-distribution layer (RDL) 214 is provided between the second wafer 220 and the carrier wafer 200 and the first wafer 210, and the second wafer 220 communicates with the first wafer through the re-distribution layer 214. 210 electrical connection. The rewiring layer 214 is used to connect the Input Output (IO) ports of the first chip 210 and re-layout the IO ports of the first chip 210, which can improve the reliability of interconnection between the chips. The second wafer 220 is connected to the first wafer 210 by being connected to the rewiring layer 214.

Optionally, in a possible implementation manner, the surface area of the carrier wafer 200 is equal to the surface area of the second wafer 220, and the second wafer 220 and the first wafer 210 are stacked by wafer-level bonding.

If the second chip 220 is a logic chip and the first chip 210 is a pixel chip, the signal processing circuit and the control circuit in the logic chip are electrically connected to the pixel chip through the rewiring layer.

In the embodiment of the present application, the first groove in the carrier wafer is used to provide support and stability for the first wafer, so that a large-area second wafer can be stacked on a small-area first wafer, so that the stacking chip structure can be implemented. At the same time, it is also possible to manufacture as many small-area first chips as possible on the wafer, reducing the cost of a single first chip, thereby reducing the overall manufacturing cost. In addition, the first chip is not bonded to the second chip in the manner of a wafer, but a single chip is placed in the first groove of the carrier chip. The carrier chip and the second chip can be the carrier wafer and the second chip respectively. The wafers on the wafer, the carrier wafer, and the second wafer are bonded at the wafer level. Therefore, a single first wafer can be tested to screen out wafers with good performance before wafer-level bonding. Removal of poor-performance wafers improves the overall chip yield and further reduces the overall manufacturing cost. Third, it is also possible to test multiple second wafers on the second wafer before wafer-level bonding, and screen out second wafers with good performance. At the position of the groove, placing a substitute of the same size as the first wafer without placing the first wafer can also increase the overall chip yield and reduce manufacturing costs.

FIG. 7 shows a schematic cross-sectional view of a stacked chip 20 according to an embodiment of the present application.

Optionally, as shown in FIG. 7, in the embodiment of the present application, the first wafer 210 is at the bottom of the first groove 201 through the adhesive layer 211 to stably fix the first wafer 210 in the first groove 201 . The adhesive layer includes but is not limited to die attach film (DAF). When the thickness of the adhesive layer 211 is d1 and the height of the first wafer 210 is d2, the sum d1+d2 of the thickness of the first wafer 210 and the adhesive layer 211 is less than or equal to the depth d0 of the first groove 201, in other words, the first wafer 210 The upper surface of 210 is not higher than the upper surface of the carrier wafer. Optionally, the difference between d1+d2 and d0 may be between 2 μm and 5 μm, or may be other values, which is not limited in the embodiment of the present application.

Optionally, the gap between the first wafer 210 and the first groove 201 may be filled with a filling layer 212 to further stably fix the first wafer 210 in the first groove 201. The filling layer 212 includes, but is not limited to, a polymer organic material, such as a dry film (Dry Film) material or other polymer materials with good fluidity. In the embodiment of the present application, the filling layer 212 can be a dry film material that can be photoetched, and can fill the space between the first wafer 210 and the first groove 201 without cavities under vacuum and heating conditions, and A photolithographic material is used as the filling layer, while filling and fixing the gap between the first groove and the first wafer, it can also facilitate the process and save the manufacturing time of the chip.

Optionally, as shown in FIG. 7, the first wafer 210 includes a first metal circuit layer 213, and the first metal circuit layer 213 is located on the surface of the first wafer 210, specifically the IO port of the first wafer 210, for It is electrically connected with other electrical components, for example, with the second wafer 220. In addition, the above-mentioned filling layer 212 may also cover the upper surface of the carrier wafer 200 and a part of the upper surface of the first wafer 210 except for the first metal circuit layer 213.

As shown in FIG. 7, the rewiring layer 214 described above is formed on the first metal circuit layer 213 and the filling layer 212. The rewiring layer 214 is also a metal wiring layer, which is in contact with the first metal on the surface of the first wafer 210. The circuit layer 213 is in contact to form an electrical connection between the two.

It should be understood that only one rewiring layer 214 is shown in FIG. 7, and the stacked chip may also include multiple rewiring layers 214. If the stacked chip 20 includes multiple rewiring layers 214, an insulating dielectric layer is formed between the multiple rewiring layers 214, and the multiple rewiring layers 214 can form electrical connections with each other. The lowermost rewiring layer 214 in 214 may be the same as the rewiring layer 214 in FIG. 7.

Optionally, above the at least one rewiring layer 214 and the filling layer 212, an insulating dielectric layer 215 is further formed to cover the entire area of the at least one rewiring layer 214 and the filling layer 212. The upper surface of the layer 215 is a flat surface with flatness and roughness that meets certain threshold requirements, so as to reduce the influence of the unevenness of the stack topography caused by the at least one rewiring layer 214, so that the second wafer 220 and the first The bonding of the wafer 210 is stable. In the embodiment of the present application, the material of the insulating dielectric layer 215 includes, but is not limited to, an insulating medium such as silicon oxide, and the specific material is not limited.

Continuing to refer to FIG. 7, the lower surface of the second wafer 220 is bonded to the insulating dielectric layer 215 above the first wafer 210. Optionally, the lower surface of the second wafer 220 is also a flat surface, and also has flatness and roughness that meet a certain threshold requirement, so that the bonding between the second wafer 220 and the insulating dielectric layer 215 is stable.

Optionally, the electrical connection between the first wafer 210 and the second wafer 220 may be achieved through a through-hole interconnection structure, such as a Through Silicon Via (TSV) interconnection structure. Specifically, the through-hole interconnection structure is a high-density packaging technology. Vertical through holes are made between the wafer and the wafer, and the through holes are filled with conductive materials such as polysilicon, copper, and tungsten. The through holes are used to complete the gap between the wafers. Through vertical interconnection, through-hole technology can reduce the length of interconnection, reduce signal delay, reduce capacitance/inductance, realize low power consumption between chips, high-speed communication, increase broadband and realize miniaturization of device integration.

It should be understood that, in the present application, the through-hole interconnection structure can be an interconnection structure of other materials, such as a gallium nitride through-hole interconnection structure, a resin through-hole interconnection structure, etc., in addition to the through-silicon via interconnection structure. The embodiments of the present application do not limit the specific materials of the through-hole interconnection structure. The through-silicon-via interconnection structure is used as an example for illustration. For other types of through-hole interconnection structures, reference may be made to related descriptions, which will not be repeated here.

Specifically, as shown in FIG. 7, a top metal circuit layer 223 is formed on the surface of the second wafer 220. The top metal circuit layer may include a metal pad, and a second metal is also formed inside the second wafer 220. The circuit layer 222, and the second metal circuit layer 222 is used to transmit electrical signals of the second chip 220. Optionally, in the embodiment of the present application, the TSV interconnect structure includes a first TSV 2241 and a second TSV 2242, wherein the first TSV interconnect structure 2241 is connected to the top metal circuit layer 223 and The rewiring layer 214 above the first wafer 210 and the second through silicon via structure 2242 are connected to the top metal circuit layer 223 and the second metal circuit layer 222 inside the second wafer 220. Therefore, the second metal circuit layer 222 in the second wafer 220 is connected to the rewiring layer 214 of the first wafer 210 through the through silicon via interconnection structure, thereby achieving electrical connection between the first wafer 210 and the second wafer 220.

Optionally, the metal pads on the surface of the second wafer 220 are also used to connect the second wafer 220 with other electrical devices. For example, the metal pads can be connected to a printed circuit board (PCB) or other types of circuit substrates by wire bonding (WB).

Optionally, in a possible implementation manner, the stacked chip 20 may be a memory chip, wherein the first chip 210 is a logic chip, and the logic chip includes a processing circuit in the memory chip for controlling signals. And deal with it. The second chip 220 is a storage chip and includes a storage circuit, which is used for data storage. Optionally, in the embodiment of the present application, a plurality of second chips may be stacked on the carrier chip 200 and the first chip 210, that is, logic A plurality of storage chips are stacked above the chip to achieve a larger storage space for the storage chips.

Optionally, in another possible embodiment, the stacked chip 20 may also be a stacked image sensor chip, wherein the second chip 220 may be a pixel chip, and the first chip 210 may be a logic chip. The chip may also be a memory chip. Optionally, in the embodiment of the present application, the pixel chip, logic chip, and memory chip may be the same as the pixel chip 101, logic chip 102, and memory chip 103 in FIG. Go into details.

Optionally, in this embodiment, each row of pixel units in the pixel array of the pixel chip can be connected to a row drive circuit on the logic chip, and the row drive circuit is used to drive each row of pixel units in the pixel chip to work in sequence and receive Light signal. Optionally, each column of pixel units in the pixel array can also be connected to a column control circuit on the logic chip, and the column control circuit is used to drive the signal transmission of each column of pixel units in the pixel chip.

In this case, the pixel unit in the pixel wafer can be connected to the IO interface in the logic wafer through the rewiring layer 214. Specifically, the rewiring layer 214 is provided with a plurality of first electrical connection points electrically connected to each row of pixel units in the pixel array, and the position distribution of the plurality of first electrical connection points is consistent with the position distribution of a column of pixel units in the pixel array , And/or, the rewiring layer 214 is provided with a plurality of second electrical connection points electrically connected to each column of pixel units in the pixel array, and the position distribution of the multiple second electrical connection points is consistent with the position of a row of pixel units in the pixel array The distribution is consistent. For example, each row of pixel units are connected to the rewiring layer 214, and the positions of the first electrical connection points of each row of pixel units connected to the rewiring layer 214 correspond to the positions below each row of pixels, and a column of pixel units can be formed. Distribute the same connection points.

Through the technical solutions of the embodiments of the present application, all the circuits in the pixel chip except the pixel unit can be arranged in the logic chip, and the IO ports are redistributed through the rewiring layer above the logic chip and connected to each row of pixels. Unit or each column of pixel units, thereby further increasing the area of the pixel array on the pixel chip and improving the sensitivity of the image sensor.

Of course, the pixel chip may also include other related control circuits besides the pixel array, such as the row control circuit and the column control circuit mentioned above. In this case, the number of interconnected ports between the pixel chip and the logic chip can be reduced, and the stability of the chip can be improved. .

FIG. 8 shows a schematic cross-sectional view of a stacked image sensor chip 20 according to an embodiment of the present application.

Optionally, as shown in FIG. 8, the second wafer 220 is a pixel wafer, and the second wafer 220 may be a back-illuminated (BI) image sensor structure or a traditional front-illuminated image sensor structure.

Specifically, in addition to the above-mentioned second metal circuit layer 222 and the top metal circuit layer 223 on the surface of the second chip 220, the second chip 220 also includes a pixel array circuit that includes a plurality of pixel units 221 , Used to receive optical signals and perform optical imaging. If the second chip 220 is a back-illuminated image sensor structure, the plurality of pixel units 221 in the second chip 220 are close to the upper surface of the second chip 220 and can receive a sufficient amount of light signals and generate relatively large electrical signals. In addition, the second metal circuit layer 222 in the second chip 220 is located under the plurality of pixel units 221. If the second chip 220 has a traditional front-illuminated image sensor structure, the plurality of pixel units 221 are located under the second metal circuit layer 222 in the second chip 220, and are far away from the upper surface of the second chip 220, and the received The amount of light signal is weak, and the quality of the electrical signal produced by it is poor.

Further, as shown in FIG. 8, the upper surface of the second wafer 220 is further provided with a filter layer 227 and a microlens array 226. Specifically, the filter layer 227 and the microlens array 226 are provided on the plurality of pixel units 221. Directly above. Optionally, each microlens in the microlens array 226 corresponds to one pixel unit of the plurality of pixel units 221. The pixel unit 221 is used to receive the optical signal condensed by the microlens and processed by the filter layer 227, and perform optical imaging based on the optical signal.

Optionally, each microlens in the microlens array 226 is a round lens or a square lens, and its upper surface is a spherical or aspherical surface, and the focal point of each microlens can be located on its corresponding pixel unit.

Optionally, the filter layer 227 may be a color filter unit. For example, the filter layer 227 includes three color filter units for transmitting red light signals, blue light signals, and green light signals, respectively. One color filter unit corresponds to at least one micro lens and at least one pixel unit. Optionally, the filter layer 227 can also be a filter used to filter visible light and block non-visible light, which can reduce the interference of the infrared band in the environment on optical imaging. It should be understood that, in the embodiment of the present application, the filter wavelength band of the filter layer can be any light waveband, and the wavelength range can be set according to actual imaging requirements, which is not limited in the embodiment of the present application.

FIG. 9 shows a schematic diagram of the split structure of another stacked chip 20 according to an embodiment of the present application.

As shown in FIG. 9, the stacked chip 20 further includes:

The third wafer 230 is disposed in the second groove 202 of the carrier wafer 200 described above.

Optionally, the above-mentioned second wafer 220 is stacked above the third wafer 230, and the area of the second wafer 220 is larger than that of the third wafer 230.

Optionally, the third chip 230, the first chip 210, and the second chip 220 are stacked by wafer-level bonding.

In a possible implementation, the surface area of the second wafer 220 is greater than the sum of the surface area of the first wafer 210 and the surface area of the third wafer 230. For example, the first wafer 210 and the third wafer 230 are completely located in the projection of the second wafer 220 in the vertical direction.

Optionally, the shape and size of the second groove 202 in the carrier wafer 200 may be the same as the shape and size of the third wafer 230 or slightly larger than the third wafer 230. For example, the third wafer 230 has a sheet structure, the depth of the second groove 202 is the same as the thickness of the third wafer 230 or slightly larger than the thickness of the third wafer 230, and the length and width of the second groove 202 are also They are slightly larger than the length and width of the third wafer 230 respectively, so that the second groove 202 can completely accommodate the third wafer 230 therein. Optionally, the length, width, and depth of the second groove 202 are larger than the length, width, and height of the third wafer 230 by 25 μm, or any other value, which is not limited in the embodiment of the present application.

Optionally, in the embodiment of the present application, the third chip 230 may be used to implement circuit functions different from those of the first chip 210 and the second chip 220. For example, if the stacked chip 20 is an image sensor For the chip, the first chip 210 may be the pixel chip 101 in FIG. 1 described above, and the second chip 220 and the third chip 230 may be the logic chip 102 and the memory chip 103 in FIG. 1 described above, respectively.

It should be understood that the stacked chip 20 may also be a chip in a variety of other different fields, such as a memory chip, a processing chip, etc., wherein the first chip, the second chip, and the third chip are functional chips that implement corresponding circuit functions. And the circuit functions of the first chip, the second chip, and the third chip are different.

In the embodiment of the present application, by arranging the first wafer 210 and the third wafer 230 in the groove of the carrier wafer 200, the large area of the second wafer 220 is stacked on the first wafer 210 and the third wafer 230. At the same time, as many first wafers 210 and third wafers 230 as possible can be grown on the wafer, reducing manufacturing costs. In addition, the space in the stacked chips can be fully utilized, and the second wafer 220 can be bonded on top of the first wafer 210 and the third wafer 230 by one wafer bonding process, instead of using two wafer bonding processes , The three wafers are bonded sequentially, thereby further reducing the process cost. Third, it is also possible to test a single first wafer 210 and a single third wafer 230 before bonding to screen out wafers with good performance, remove wafers with poor performance, and improve the overall chip yield. , To further reduce the overall manufacturing cost. Similarly, it is also possible to test multiple second wafers 220 on the second wafer before wafer-level bonding, to screen out second wafers with good performance, and to select the first wafer corresponding to the second wafer with poor performance. At the positions of the grooves and the second grooves, placing substitutes of the same size as the first and third wafers instead of placing the first and third wafers can also increase the overall chip yield and reduce manufacturing costs .

FIG. 10 shows a schematic cross-sectional view of another stacked image sensor chip 20 according to an embodiment of the present application.

Optionally, as shown in FIG. 10, the second wafer 220 is a pixel wafer. Optionally, the second wafer 220 may be a back-illuminated image sensor structure or a traditional front-illuminated image sensor structure. For the related technical solution of the second wafer 220, reference may be made to the related description in FIG. 7 or FIG. 8, which will not be repeated here.

In the embodiment of the present application, the first chip 210 and the third chip 230 may be a logic chip and a memory chip, respectively. For the related technical solutions of the first wafer 210, reference may also be made to the related description in FIG. 7 or FIG. 8, which will not be repeated here.

As shown in FIG. 10, in the third wafer 230, the third wafer 230 is at the bottom of the second groove 202 through the adhesive layer 231 to stably fix the third wafer 230 in the second groove 202. The adhesive layer includes, but is not limited to, a wafer bonding film. Similarly, when the thickness of the adhesive layer 231 is d'1 and the height of the third wafer 230 is d'2, the sum d'1+d'2 of the thickness of the third wafer 230 and the adhesive layer 231 is less than or equal to the second concave The depth d'0 of the groove 202, optionally, the difference between d'1+d'2 and d'0 can be between 2-5 μm, or other values, which is not limited in the embodiment of the present application.

Optionally, the gap between the third wafer 230 and the second groove 202 can also be filled with a filling layer 212 to further stably fix the third wafer 230 in the second groove 202.

Optionally, as shown in FIG. 10, the third wafer 230 includes a third metal circuit layer 233, and the third metal circuit layer 233 is located on the surface of the third wafer 230 and is used to interact with other electrical components, such as the second wafer. 220 makes electrical connections. The above-mentioned filling layer 212 may also cover a part of the upper surface of the third wafer 230 except for the third metal circuit layer 233.

As shown in FIG. 10, at least one rewiring layer 214 is also formed on the third metal circuit layer 233 and the filling layer 212, which is used to connect the third metal circuit layer 233 of the third wafer 230 and other electrical components. Specifically, the rewiring layer 214 may be laterally connected to the first metal circuit layer 213 on the surface of the first wafer 210 and the third metal circuit layer 233 on the surface of the third wafer. And through the at least one rewiring layer 214, the interface position of the third metal circuit layer 233 in the third chip can be re-layout, which can improve the reliability of the interconnection between the chips.

Continuing to refer to FIG. 10, the insulating dielectric layer 215 completely covers the rewiring layer 214 and the filling layer 212 above the first wafer 210 and the third wafer 230. In addition, the upper surface of the insulating dielectric layer 215 and the lower surface of the second wafer 220 are both flat surfaces, and the two can be bonded together by a bonding process.

Optionally, the third wafer 230 is also electrically connected to the second wafer 220 through a through silicon via interconnection structure. Specifically, the multiple first TSV interconnect structures 2241 in the TSV interconnect structure are connected to the top metal line layer 223 and the rewiring layer 214. Among them, one first TSV interconnect structure 2241 is connected to the first TSV interconnect structure. The rewiring layer 214 above the wafer 210 is connected to the first metal circuit layer 213 on the surface of the first wafer 210 through the rewiring layer 214. The other first TSV interconnect structure 2241 is connected to the rewiring layer 214 above the third wafer 230, and is connected to the third metal wiring layer 233 on the surface of the third wafer 230 through the rewiring layer 214. In addition, the multiple second TSV interconnect structures 2242 in the TSV interconnect structure are connected to the top metal circuit layer 223 and the second metal circuit layer 222 in the second wafer 220. Therefore, the second metal circuit layer 222 in the second wafer 220 is connected to the rewiring layer 214 through the through silicon via interconnection structure, thereby achieving electrical connection between the third wafer 230 and the second wafer 220 and the first wafer 210 and the second wafer 210 The electrical connection of the two chips 220. Optionally, the top metal circuit layer 223 is also used to connect the second chip 220 and other electrical devices.

6 to 10, the device embodiment of the stacked chip of the present application is described in detail above, and the following describes the embodiment of the method of manufacturing the stacked chip of the present application in detail with reference to Figs. 11 to 21. It should be understood that the device The embodiment and the method embodiment correspond to each other, and the similar description can refer to the device embodiment.

Fig. 11 is a schematic flow chart of a method for manufacturing a stacked chip.

As shown in FIG. 11, the manufacturing method 200 of the stacked chip may include the following steps.

S210: Fix a plurality of first wafers in a plurality of first grooves of the carrier wafer.

Optionally, each of the plurality of first wafers may be the same as the first wafer 210 in the foregoing device embodiment. The carrier wafer may be the same as the carrier wafer 21 in the above device embodiment. The plurality of first grooves may be the same as the first grooves 201 in the above-mentioned device embodiment.

As shown in FIG. 12, a plurality of first grooves 201 are provided on the carrier wafer 21. The sizes of the plurality of first grooves are completely the same, and the plurality of first grooves 201 are distributed on the carrier wafer 21 in an array.

After preparing a plurality of first grooves on the carrier wafer, a plurality of discrete first wafers are fixed in the first grooves.

S220: preparing the rewiring layers of the plurality of first chips on the carrier wafer on which the plurality of first chips are fixed.

Optionally, the rewiring layer of each first wafer in the plurality of first wafers may be the same as the rewiring layer 214 of the first wafer in the foregoing device embodiment. Specifically, in the embodiment of the present application, the rewiring layers of the multiple first wafers are used to redistribute the IO ports in the multiple first wafers, so as to facilitate electrical connection with other electronic components and improve the overall performance of the chip. .

S230: Stack the second wafer on top of the carrier wafer on which the rewiring layer is formed.

Optionally, a wafer-level bonding process of wafer-to-wafer bonding may be used to bond the second wafer to the carrier wafer. Wherein, the surface area of the second wafer is equal to the surface area of the carrier wafer. Adopting this bonding method is easy to realize the process, the preparation speed of the chip is fast, and the process cost can be reduced.

S240: Electrically connect the plurality of second chips in the stacked second wafer with the plurality of first chips through the rewiring layer.

Specifically, in the embodiment of the present application, a plurality of second wafers have been prepared on the second wafer, and after the second wafer is bonded on the carrier wafer, the plurality of second wafers and the carrier wafer In other words, the number of the second wafers is the same as the number of the first wafers, and a second wafer is stacked above each first wafer. Among the second wafers The area of each second wafer is greater than the area of its corresponding first wafer. Optionally, each second wafer of the plurality of second wafers may be the same as the second wafer 220 in the foregoing device embodiment.

Specifically, the plurality of first chips are electrically connected to the rewiring layer, and the plurality of second chips in the second wafer are electrically connected to the rewiring layer, so as to realize the electrical connection between the plurality of second chips and the plurality of first chips. connection.

S250: Cutting the electrically connected second wafer and the whole of the first wafer to obtain a plurality of stacked chips.

Optionally, the stacked chip obtained by cutting may be the stacked chip 20 in the device embodiment shown in FIGS. 6 to 8.

In the embodiment of the present application, the first groove in the carrier wafer is used to provide support and stability for the plurality of first wafers, and the second wafer including the plurality of second wafers is directly bonded to the carrier using a wafer-level bonding process On the wafer, it is possible to stack a large-area second wafer on a small-area first wafer. While realizing the stacked chip structure, it is also possible to manufacture as many small-area first wafers on the wafer as possible to reduce the cost. The cost of the first chip, thereby reducing the overall manufacturing cost. In addition, before bonding, a single first wafer can be tested to screen out wafers with good performance, and wafers with poor performance can be removed, so as to improve the overall chip yield and further reduce the overall manufacturing cost. Third, it is also possible to test multiple second wafers on the second wafer before wafer-level bonding, and screen out second wafers with good performance. At the position of the groove, placing a substitute of the same size as the first wafer without placing the first wafer can also increase the overall chip yield and reduce manufacturing costs.

FIG. 13 shows a schematic flowchart of another method 200 for manufacturing a stacked chip.

As shown in FIG. 13, the above step S210 may include the following steps.

S211: Prepare and cut multiple first wafers on the first wafer.

Specifically, the multiple first wafers are multiple wafers prepared on the first wafer and cut from the first wafer. Further, the plurality of first wafers are wafers that meet the performance requirements after being tested. Optionally, N chips can be prepared on the first wafer, where N is a positive integer, the number of the plurality of chips is M, and M is a positive integer less than N.

S212: Prepare a plurality of first grooves on the carrier wafer, and place the plurality of first wafers into the plurality of first grooves through a pick and place (Pick and Place) process.

Optionally, in the embodiment of the present application, a plurality of first grooves can be prepared on the carrier wafer by a variety of process methods, including but not limited to: dry etching, laser Law, mechanical law, etc. The embodiment of the application does not specifically limit this.

Specifically, FIG. 14 shows a partial cross-sectional view of the wafer along the A-A' direction in FIG. 12. Two first grooves 201 with the same shape and size are formed on the carrier wafer 21.

After the plurality of first grooves are prepared on the carrier wafer, the plurality of first wafers can be placed in the plurality of first grooves by using a standard pick-and-place process. Wherein, the lower surface of the first wafer is provided with a first adhesive layer, and the first adhesive layer includes but is not limited to DAF.

Specifically, FIG. 15 shows a cross-sectional view after this process step. As shown in FIG. 15, the two first wafers 210 are respectively fixed on the bottom of the first groove 201 through the first adhesive layer 211. A first metal circuit layer 213 is formed on the upper surface of the first chip 210, which may be an IO interface of the first chip 210.

S213: Fill the gaps between the plurality of first wafers and the plurality of first recesses and the upper surface of the carrier wafer with a filling material, and heat the filling material in a vacuum environment to form a stable filling layer.

Specifically, the filling material may be a dry film or other polymer materials with good fluidity. In particular, the filling material may be a dry film material that can be photoetched. The filling material is attached to the surface of the carrier wafer by an automatic film attaching machine, and can be automatically filled in the gaps between the plurality of first wafers and the plurality of first grooves due to its fluidity. Then, it is cured under vacuum and heating conditions to form a stable filling layer, which can be filled in the voids of the plurality of first wafers and the plurality of first grooves without cavities, so as to ensure that the plurality of first wafers are in the first Structural stability in the groove.

Specifically, FIG. 16 shows a cross-sectional view after this process step. As shown in FIG. 16, the filling layer 212 fills the gap between the two first wafers 210 and the two first grooves 201 and the upper surface of the carrier wafer 200.

Optionally, the foregoing step S220 may include:

S221: Perform a windowing process on the filling layer to remove the filling layer above the plurality of first metal circuit layers on the upper surface of the plurality of first wafers, and prepare a rewiring layer above the filling layer.

Specifically, a semiconductor process, such as exposure, development, and etching, can be used to open a window on the filling layer to expose the multiple first metal circuit layers on the upper surfaces of the multiple first wafers.

Then, a rewiring layer is prepared on the surface of the plurality of first metal circuit layers and the filling layer by using processes such as seed layer deposition, photolithography, and electroplating. Wherein, the rewiring layer is in contact with a plurality of first metal layers to form an electrical connection relationship.

Specifically, FIG. 17 shows a cross-sectional view after this process step. As shown in FIG. 17, the rewiring layer 214 is a pattern layer of metal lines, and includes a plurality of electrical connection lines. Specifically, the rewiring layer 214 is formed on the filling layer 212 and the plurality of first metal circuit layers 213, and is in contact with the plurality of first metal circuit layers 213 to form an electrical connection relationship.

Optionally, the manufacturing method is a method of manufacturing a stacked image sensor, and the rewiring layer 214 is provided with electrical connection lines corresponding to each row of pixel units and/or each column of pixel units in the pixel array of the image sensor. The distribution of the connection positions of the electrical connection lines is consistent with the distribution of a column of pixel units and/or a row of pixel units in the pixel array. For example, the pixel units of each row are connected to the rewiring layer 214, and the connection positions of the pixel units of each row to the rewiring layer 214 are respectively located below each row of pixels, which can form the same connection points as a column of pixel units. .

Optionally, the above step S230 may include the following steps.

S231: Prepare an insulating dielectric layer above the rewiring layer and the filling layer, and after planarizing the upper surface of the insulating dielectric layer and the lower surface of the second wafer, bond them together.

Specifically, a semiconductor manufacturing process is used to prepare an insulating dielectric layer above the rewiring layer and the filling layer to cover the entire area of the rewiring layer and the filling layer. Optionally, the semiconductor manufacturing process includes but is not limited to: physical vapor deposition (Chemical Vapor Deposition, CVD), chemical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), etc., this application The embodiment does not specifically limit this. Optionally, the insulating dielectric layer may be an insulating material such as silicon oxide, and the embodiment of the present application does not limit the specific material of the insulating dielectric layer.

Since the rewiring layer is an uneven pattern layer, an insulating dielectric layer is prepared above the rewiring layer to form a flat interface, which is convenient for wafer bonding. Specifically, after the insulating dielectric layer is prepared, the upper surface of the insulating dielectric layer is planarized. Optionally, a polishing treatment is performed on the upper surface of the insulating dielectric layer, and the polishing treatment includes, but is not limited to, a chemical-mechanical polishing (Chemical-Mechanical Planarization, CMP) process.

Optionally, in the embodiment of the present application, the lower surface of the second wafer is also planarized to form a smooth surface. After the planarization process, the flatness and roughness of the lower surface of the second wafer and the upper surface of the insulating dielectric layer meet certain threshold requirements before wafer-level bonding can be performed.

Specifically, the lower surface of the smooth second wafer and the upper surface of the insulating dielectric layer are bonded together, and then subjected to high-temperature annealing, so that the bonding force between the second wafer and the insulating dielectric layer is enhanced, and the inter-wafer adhesion is improved. Bonding force. This bonding method is also called Fusion Bonding. Optionally, the bonding between the second wafer and the carrier wafer may also adopt other wafer-level bonding methods, such as ultra-high vacuum bonding and surface activated bonding. , SAB), plasma activated bonding and other methods, which are not specifically limited in the embodiments of the present application.

Optionally, a plurality of second wafers are grown on the second wafer, and the second wafer may be a pixel wafer in an image sensor, and includes a pixel array composed of a plurality of pixel units. Optionally, the pixel wafer may be a back-illuminated image sensor structure, or may be a traditional front-illuminated image sensor structure. If the pixel wafer is a back-illuminated image sensor structure, the substrate of the pixel wafer is the upper surface of the pixel wafer. In other words, in the embodiment of the present application, the upper surface of the second wafer is a substrate material, such as a silicon substrate.

Optionally, after the foregoing step S231, the manufacturing method 200 further includes:

S232: Perform a thinning process on the upper surface of the second wafer.

Specifically, methods such as mechanical thinning, chemical thinning, chemical polishing, etc. may be used to thin the substrate material of the second wafer, and the embodiment of the present application does not make any limitation on the specific thinning method. In the process of thinning the second wafer, the carrier wafer can play a supporting role.

Optionally, if the second chip of the second wafer is a pixel chip, the upper surface of the thinned second wafer is close to the pixel array in the second chip, in other words, close to the plurality of photodiodes in the second chip. In the embodiment of the present application, the second metal circuit layer of the second chip is located below the pixel array, and the second metal circuit layer is used to transmit electrical signals of the second chip.

Specifically, FIG. 18 shows a cross-sectional view after this process step. As shown in FIG. 18, the second wafer 22 is bonded above the insulating dielectric layer 215, wherein the two second wafers 220 in the second wafer 22 are stacked above the two first chips 210 respectively. After the thinning process, in the second wafer 220, a plurality of pixel units 221 are close to the upper surface of the second wafer 22. The second metal circuit layer 222 in the second wafer 220 is formed under the plurality of pixel units 221.

Optionally, the above step S240 may include the following steps.

S241: Prepare a plurality of via interconnection structures, and electrically connect the plurality of second metal circuit layers and the rewiring layer through a plurality of top metal circuit layers.

Optionally, multiple through silicon via interconnection structures are prepared by the through silicon via interconnection technology. The through silicon via interconnection technology includes processes such as preparation of the through silicon via structure and filling of conductive materials in the through holes.

Optionally, the through silicon via interconnection structure is used to electrically connect the second metal circuit layer in the second wafer with the rewiring layer through the top metal circuit layer; wherein the top metal circuit layer is disposed on the upper surface of the second wafer, The TSV interconnect structure includes a first TSV interconnect structure and a second TSV interconnect structure, and the first TSV interconnect structure is used to connect the second metal circuit layer and the top layer in the second wafer The metal circuit layer, the second through silicon via interconnection structure is used to connect the rewiring layer and the top metal circuit layer. Therefore, through the through silicon via interconnection structure and the top metal circuit layer, the second metal circuit layer in the second wafer and the rewiring layer are electrically connected together, and the rewiring layer is electrically connected to the first metal circuit in the first wafer. Layer contact, so as to realize the electrical connection relationship between the second wafer and the first wafer.

Optionally, the conductive material filled in the TSV interconnect structure includes but is not limited to copper, polysilicon, and the like.

Specifically, FIG. 19 shows a cross-sectional view after this process step. As shown in FIG. 19, a plurality of top metal wiring layers 223 are formed on the surface of the second wafer 220, and the TSV interconnection structure includes a first TSV 2241 and a second TSV 2242, wherein the first TSV The interconnect structure 2241 connects the top metal circuit layer 223 and the rewiring layer 214, and the second TSV structure 2242 connects the top metal circuit layer 223 and the second metal circuit layer 222.

Optionally, if the second wafer is a pixel wafer, after the above steps, a filter layer and a microlens array can be grown above the pixel array. The filter layer and the microlens array can be the same as the filter layer 227 in FIG. 8 And the micro lens array 226 is the same.

Using the solution of the embodiment of the present application, compared to the wafer-to-wafer bonding method, the filter layer and microlens array are prepared on the surface of the pixel wafer after the wafer bonding is performed, and there is no need to set up during the bonding process. Temporary bonding glue and removal of temporary bonding glue will not bring additional process costs and will not affect the performance of the optical devices in the chip.

Optionally, after the foregoing step S231, the foregoing step S250 may include:

S251: Perform wafer dicing along the dicing path of the carrier wafer to obtain multiple stacked chips.

Specifically, the multiple wafers on the carrier wafer are cut along the dicing path of the carrier wafer to obtain multiple stacked chips. The dicing path of the carrier wafer is also the dicing path of the second wafer. Each stacked chip includes a first wafer on a carrier wafer and a second wafer stacked above the first wafer. Optionally, the obtained stacked chip may be the stacked chip 20 in the device embodiment in FIGS. 6 to 8 described above.

Specifically, FIG. 20 shows a cross-sectional view after this process step. As shown in FIG. 20, after cutting along the dotted line shown in the figure, two stacked chips are obtained. The two stacked chips may be image sensor chips or other types of chips.

By adopting the solution of the embodiment of the present application, a plurality of stacked chips can be prepared by using a wafer-level bonding process, which can reduce the cost of each chip while optimizing the process. In addition, it is also possible to test the first wafer before bonding, so as to reject wafers with poor performance, retain wafers with better performance, and improve the overall yield of stacked chips.

FIG. 21 is a schematic flowchart of another method 300 for manufacturing a stacked chip.

As shown in FIG. 21, the manufacturing method 300 of the stacked chip may include the following steps.

S310: Fix a plurality of first wafers in a plurality of first grooves of the carrier wafer.

S320: Fix a plurality of third wafers in a plurality of second grooves of the carrier wafer.

Optionally, in the embodiment of the present application, the plurality of third chips may be the same as the third chip 230 in the foregoing device embodiment. Optionally, the first chip and the third chip may be logic chips and memory chips, respectively.

Specifically, step S310 may be the same as step S210 described above, and may include step S211 to step S213 described above. In step S320, the process of fixing the plurality of third chips in the plurality of second grooves of the carrier wafer can refer to the above step S210, step S211 to step S213, and the third chip and the third recess in the above device embodiment. Description of the slot.

Optionally, a plurality of first grooves and a plurality of second grooves can be prepared on the carrier wafer at the same time, and then the plurality of first wafers and the plurality of third wafers are respectively placed on the corresponding In the groove. Optionally, the lower surface of the plurality of third wafers is also provided with a DAF layer, and the plurality of third wafers are fixed on the bottom of the plurality of second grooves through the DAF.

Optionally, by coating the surfaces of the plurality of first wafers and the plurality of third wafers with a filler material, the filler material fills the gaps between the plurality of first wafers and the plurality of first grooves, and at the same time Fill the gaps between the plurality of third wafers and the plurality of second grooves. After heating and curing the filling material to form a filling layer, the plurality of third wafers and the plurality of first wafers are all stably fixed in the groove.

S330: preparing rewiring layers of a plurality of first chips and a plurality of third chips on the carrier wafer.

Specifically, the rewiring layer is formed above the plurality of first wafers and the plurality of third wafers, and is electrically connected to the plurality of first wafers and the plurality of third wafers.

Specifically, the above-mentioned filling layer is windowed to remove the filling layer above the plurality of first metal circuit layers on the upper surfaces of the plurality of first wafers and the plurality of third metal circuit layers on the upper surfaces of the plurality of third wafers, A rewiring layer is prepared above the filling layer.

Specifically, semiconductor processes, such as exposure, development, and etching, can be used to open windows on the filling layer to expose the upper surfaces of the first metal circuit layers and the upper surfaces of the third wafers. In multiple third metal circuit layers.

Then, a rewiring layer is prepared on the surface of the plurality of first metal circuit layers and the filling layer by using processes such as seed layer deposition, photolithography, and electroplating. Wherein, the rewiring layer is in contact with a plurality of first metal circuit layers and a plurality of third metal circuit layers to form an electrical connection relationship.

In addition, the rewiring layer may be laterally connected to the first metal circuit layer on the surface of the first chip and the third metal circuit layer on the surface of the third chip. And through the rewiring layer, the position of the IO interface of the third metal circuit layer in the third chip can be re-layout, which can improve the reliability of interconnection between the chips.

S340: Stack the second wafer on top of the carrier wafer on which the rewiring layer is formed.

S350: Electrically connect the plurality of second chips in the second wafer with the plurality of first chips through the rewiring layer.

Specifically, this step S340 and step S350 can refer to the aforementioned step S230 and step S240, and can also refer to the aforementioned step S231 to step S241, which will not be repeated here.

It should be noted here that after the second wafer is bonded above the carrier wafer, a corresponding first wafer and a first wafer are provided below each second wafer among the plurality of second wafers in the second wafer. Three chips, and the area of the second chip is greater than the sum of the areas of the first chip and the third chip. After bonding, each second wafer of the plurality of second wafers is stacked above its corresponding first wafer and third wafer.

It should be understood that multiple other numbers of wafers may also be arranged under the second wafer, and the multiple wafers are correspondingly arranged in the grooves of the carrier wafer. The embodiment of the present application does not have a specific number of wafers in the stacked chip. Make a limit.

S360: Electrically connect the plurality of second chips in the second wafer with the plurality of third chips through the rewiring layer.

Specifically, this step S360 can be performed simultaneously with the above step S350, and the specific implementation is similar to the above step S350.

Optionally, the third wafer is also electrically connected to the second wafer through the through silicon via interconnection structure. Specifically, a top metal circuit layer is grown on the surface of the second wafer, and a plurality of first TSV interconnect structures in the TSV interconnect structure are connected to the top metal circuit layer and the rewiring layer. Among them, one of the first TSV interconnect structures is connected to the top metal circuit layer and the rewiring layer. The via interconnection structure is connected to the rewiring layer above the first wafer, and is connected to the first metal circuit layer on the surface of the first wafer through the rewiring layer. Another first TSV interconnect structure is connected to the rewiring layer above the third wafer, and is connected to the third metal circuit layer on the surface of the third wafer through the rewiring layer. In addition, the multiple second TSV interconnect structures in the TSV interconnect structure connect the top metal circuit layer and the second metal circuit layer in the second wafer. Therefore, the second metal circuit layer in the second wafer is connected to the rewiring layer through the through silicon via interconnection structure, thereby achieving electrical connection between the third wafer and the second wafer and the electrical connection between the first wafer and the second wafer.

Optionally, after the above steps, the manufacturing method 300 further includes:

S370: Perform wafer dicing along the dicing path of the carrier wafer to obtain multiple stacked chips.

In the embodiment of the present application, the stacked chips obtained by cutting include three wafers, wherein the second wafer is stacked above the first wafer and the third wafer. Optionally, the obtained stacked chip may be the stacked chip 20 in the device embodiment in FIG. 9 to FIG. 10 described above.

By adopting the solution of the embodiment of the present application, the position space in the stacked chips can be fully utilized, and large-area chips can be stacked on top of multiple small-area chips, and as many small chips as possible can be grown on the wafer, reducing manufacturing cost. In addition, the bonding between multiple wafers does not require multiple wafer bonding processes, thereby further reducing process costs.

As shown in FIG. 22, an embodiment of the present application further provides an image sensor 30, and the image sensor 30 may include the stacked chip 20 of the foregoing application embodiment.

Specifically, the stacked chip 20 is a stacked image sensor chip, which is used to receive optical signals and convert the optical signals to obtain electrical signals. Optionally, the stacked image sensor chip may undergo subsequent processing processes such as packaging. To form an image sensor, the image sensor 30 may also include other electrical, optical, or mechanical elements, which are not limited in the embodiment of the present application.

As shown in FIG. 23, an embodiment of the present application further provides an electronic device 40, and the electronic device 40 may include the stacked chip 20 of the foregoing application embodiment.

Optionally, the stacked chip 20 may be an image sensor chip, which is used in various mobile terminal shooting devices, such as front or rear cameras of mobile phones, digital cameras, and so on.

The electronic equipment may also include optical devices such as a lens and an optical path guiding structure.

It should be understood that the specific examples in the embodiments of the present application are only for helping those skilled in the art to better understand the embodiments of the present application, rather than limiting the scope of the embodiments of the present application.

It should be understood that the terms used in the embodiments of the present application and the appended claims are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. For example, the singular forms of "a", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

A person of ordinary skill in the art may be aware that, in combination with the examples described in the embodiments disclosed herein, the units can be implemented by electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the interchangeability of hardware and software. In the above description, the composition and steps of each example have been described generally in terms of function. Whether these functions are performed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

In the several embodiments provided in this application, it should be understood that the disclosed system and device may be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present application.

In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of this application is essentially or the part that contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium. It includes several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disks or optical disks and other media that can store program codes. .

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Anyone familiar with the technical field can easily think of various equivalents within the technical scope disclosed in this application. Modifications or replacements, these modifications or replacements shall be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A stacked chip, characterized in that it comprises:

A carrier wafer with a first groove provided therein;

The first wafer is arranged in the first groove;

A second wafer stacked above the carrier wafer and the first wafer, and the surface area of the second wafer is larger than the surface area of the first wafer;

A rewiring layer located between the second wafer and the first wafer, and the second wafer is electrically connected to the first wafer through the rewiring layer.
The chip according to claim 1, wherein:

The stacked chip is an image sensor chip;

The second wafer is a pixel wafer, and the pixel wafer includes a pixel array for receiving optical signals and converting them into electrical signals;

The first chip is a logic chip, and the logic chip includes a signal processing circuit for processing the electrical signal.
The chip according to claim 1 or 2, wherein the surface area of the carrier wafer is equal to the surface area of the second wafer, and the second wafer and the first wafer pass through wafer level Bonding to form a stack.
The chip according to any one of claims 1 to 3, wherein the chip further comprises a filling layer, and the filling layer is arranged between the first wafer and the first groove, and the The upper surface of the carrier wafer and the area on the upper surface of the first wafer excluding the first metal circuit layer;

Wherein, the filling layer is used to fix the first wafer in the first groove, and the first metal circuit layer is a circuit layer of the first wafer.
4. The chip according to claim 4, wherein the rewiring layer is disposed on the filling layer and the upper surface of the first metal circuit layer for electrically connecting the first metal circuit layer and the The second wafer.
The chip according to claim 4 or 5, wherein the chip further comprises an insulating dielectric layer, the insulating dielectric layer covering the rewiring layer and the filling layer, on the insulating dielectric layer The surface is bonded to the lower surface of the second wafer.
The chip according to any one of claims 4 to 6, wherein the filling layer is a dry film material layer that can be used for photolithography.
The chip according to any one of claims 1 to 7, wherein the chip further comprises a through-hole interconnection structure, and the through-hole interconnection structure is used to electrically connect the second wafer and the second wafer. One chip.
8. The chip of claim 8, wherein the second wafer comprises a second metal circuit layer and a top metal circuit layer, wherein the second metal circuit layer is located inside the second wafer, and the top layer The metal circuit layer is located on the upper surface of the second chip;

The first via interconnection structure in the via interconnection structure connects the top metal circuit layer and the rewiring layer, and the second via interconnection structure in the via interconnection structure connects the top layer The metal circuit layer and the second metal circuit layer, wherein the rewiring layer is electrically connected to the circuit layer of the first wafer.
The chip according to any one of claims 1 to 9, wherein the chip further comprises a first adhesive layer, the first adhesive layer is disposed on the lower surface of the first wafer, and the first adhesive layer The glue layer is used for bonding the first chip in the first groove.
The chip according to any one of claims 1 to 10, wherein the upper surface of the first wafer is not higher than the upper surface of the carrier wafer.
The chip according to any one of claims 1 to 11, wherein a second groove is further provided in the carrier wafer, and the chip further comprises: a third wafer, and the third wafer is provided in the carrier wafer. In the second groove;

The second wafer is stacked above the first wafer, the third wafer, and the carrier wafer, and the surface area of the second wafer is larger than the surface area of the first wafer and the third wafer Sum.
The chip according to claim 12, wherein the third chip, the first chip and the second chip are stacked by wafer-level bonding.
The chip according to claim 12 or 13, wherein the first wafer is electrically connected to the third wafer through the rewiring layer, and the second wafer is electrically connected to the third wafer through a via interconnection structure. Three-chip electrical connection.
The chip according to any one of claims 12 to 14, wherein the third chip is a memory chip in an image sensor chip, and the memory chip includes a storage circuit for storing the first chip And/or electrical signals generated by the second wafer.
The chip according to any one of claims 1 to 15, wherein the second chip is a pixel chip in an image sensor chip, and the pixel array of the pixel chip is close to the upper surface of the pixel chip A filter layer and/or a micro lens array are arranged above the pixel array.
The chip according to any one of claims 1 to 16, wherein the material of the carrier wafer is any one of silicon, glass, and ceramic.
A method for manufacturing a stacked chip, which is characterized in that it comprises:

Making a plurality of first grooves on the carrier wafer;

Dividing a plurality of first wafers from the first wafer, and fixing the plurality of first wafers in the plurality of first grooves of the carrier wafer;

Preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed;

Stacking a second wafer on top of the carrier wafer on which the rewiring layer is made;

Electrically connecting the plurality of second chips in the second wafer after the stack to the plurality of first chips through the rewiring layer;

Cutting the electrically connected second wafer and the whole of the first wafer to obtain a plurality of stacked chips;

Wherein, the plurality of second wafers correspond to the plurality of first wafers one-to-one, and are respectively stacked above the plurality of first wafers, and each second wafer of the plurality of second wafers The surface area is greater than the surface area of each first wafer in the plurality of first wafers.
18. The manufacturing method of claim 18, wherein the stacking of the second wafer on the carrier wafer on which the rewiring layer is formed comprises:

The second wafer is bonded above the carrier wafer on which the rewiring layer is formed by using a wafer bonding process, wherein the surface area of the second wafer is equal to that of the carrier wafer The surface area is equal.
The manufacturing method according to claim 18 or 19, wherein the stacked chip is an image sensor chip, the plurality of second chips are pixel chips, and each of the plurality of second chips includes a pixel array, Used to receive optical signals and convert them into electrical signals;

The plurality of first chips are logic chips, and each of the plurality of first chips includes a signal processing circuit for processing the electrical signal.
22. The manufacturing method of claim 20, wherein after stacking the second wafer on the carrier wafer on which the rewiring layer is formed, the manufacturing method further comprises:

Thinning the upper surface of the second wafer;

Wherein, the pixel arrays of the plurality of second wafers in the second wafer are close to the upper surface of the second wafer after the thinning process.
22. The manufacturing method of claim 21, wherein after thinning the upper surface of the second wafer, the manufacturing method further comprises: placing a plurality of second wafers in the second wafer A filter layer and/or a micro lens array are prepared above the pixel array.
The manufacturing method according to any one of claims 18 to 22, wherein after the plurality of first wafers are fixed in the plurality of first grooves of the carrier wafer, the manufacturing method Also includes:

Filling the gaps between the plurality of first dies and the plurality of first recesses and the upper surface of the carrier wafer with a filling material;

The filling material is heated in a vacuum environment to form a stable filling layer.
22. The manufacturing method of claim 23, wherein the preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed includes:

The filling layer is windowed to remove the partial filling layer above the multiple first metal circuit layers on the upper surface of the multiple first wafers, wherein the multiple first metal circuit layers are the multiple The circuit layer in the first chip;

The rewiring layer is prepared above the filling layer and the plurality of first metal circuit layers, and the rewiring layer is used to electrically connect the plurality of first metal circuit layers and the second wafer Multiple second wafers.
The manufacturing method according to claim 23 or 24, wherein the stacking of the second wafer on the carrier wafer on which the rewiring layer is formed comprises:

Preparing an insulating dielectric layer above the rewiring layer and the filling layer, where the insulating dielectric layer is used to cover the rewiring layer and the filling layer;

A wafer bonding process is used to bond the upper surface of the insulating dielectric layer and the lower surface of the second wafer.
26. The manufacturing method of claim 25, wherein the bonding the upper surface of the insulating dielectric layer and the lower surface of the second wafer using a wafer bonding process comprises:

The upper surface of the insulating dielectric layer and the lower surface of the second wafer are planarized, wherein the upper surface of the insulating dielectric layer after the planarization process and the lower surface of the second wafer The flatness and/or roughness meets the preset threshold;

The upper surface of the insulating dielectric layer is bonded to the lower surface of the second wafer, and high-temperature annealing is performed to bond the upper surface of the insulating dielectric layer and the lower surface of the second wafer.
The manufacturing method according to any one of claims 23 to 26, wherein the filling material is a dry film material that can be used for photolithography.
The manufacturing method according to any one of claims 18 to 27, wherein the fixing the plurality of first wafers in the plurality of first grooves of the carrier wafer comprises:

Putting the plurality of first wafers into the plurality of first grooves through a pick-and-place process;

Wherein, the lower surfaces of the plurality of first wafers are respectively provided with a first adhesive layer, and the lower surfaces of the plurality of first wafers are bonded in the plurality of first grooves through the first adhesive layer.
The manufacturing method according to any one of claims 18 to 28, wherein the upper surface of the plurality of first wafers is not higher than the upper surface of the carrier wafer.
The manufacturing method according to any one of claims 18 to 29, wherein a plurality of second wafers in the second wafer after being stacked are connected to the plurality of first wafers through the rewiring layer. The chip is electrically connected, including:

A plurality of through-hole interconnection structures are prepared in the plurality of second wafers and the plurality of first wafers after the stack, and the plurality of through-hole interconnection structures are used to connect a plurality of The second metal circuit layer is electrically connected to the rewiring layer;

Wherein, the rewiring layer is electrically connected to the circuit layers of the plurality of first wafers, the plurality of second metal circuit layers are circuit layers in the plurality of second wafers, and the plurality of top metal circuits The layer is disposed on the upper surface of the plurality of second wafers.
The manufacturing method according to any one of claims 18 to 30, wherein before preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed, the manufacturing method further comprises:

Forming a plurality of second grooves on the carrier wafer, and the plurality of second grooves and the plurality of first grooves are located on the same surface of the carrier wafer;

Dividing a plurality of third wafers from the third wafer, and fixing the plurality of third wafers in the plurality of second grooves of the carrier wafer;

The preparing a rewiring layer on the carrier wafer on which the plurality of first wafers are fixed includes:

Preparing the rewiring layer on the carrier wafer on which the plurality of first chips and the plurality of third chips are fixed;

After stacking the second wafer on the carrier wafer on which the rewiring layer is formed, the manufacturing method further includes:

Electrically connecting a plurality of second chips in the second wafer after the stack to the plurality of third chips through the rewiring layer;

Wherein, the plurality of second wafers correspond to the plurality of third wafers one-to-one, and the plurality of second wafers are stacked on the plurality of first wafers, the plurality of third wafers, and the carrier crystal Above the circle, and the surface area of each second wafer among the plurality of second wafers is larger than the surface area of one first wafer among the plurality of first wafers and one third wafer among the plurality of third wafers Sum.
The manufacturing method according to claim 31, wherein the plurality of first wafers are electrically connected to the plurality of third wafers through the rewiring layer, and the plurality of second wafers pass through a plurality of through holes. The interconnection structure is electrically connected to the plurality of third wafers.
The manufacturing method according to claim 31 or 32, wherein the plurality of third chips are a plurality of memory chips, including a storage circuit for storing the plurality of first chips and/or the plurality of The electrical signal generated by the second wafer.
The manufacturing method according to any one of claims 18 to 33, wherein the substrate material of the carrier wafer is any one of silicon, glass, and ceramic.
An image sensor, characterized by comprising: the stacked chip according to any one of claims 1 to 17.
An electronic device, characterized by comprising: the stacked chip according to any one of claims 1 to 17.