CN113690261A - Method for forming CMOS image sensor - Google Patents
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Abstract
A method of forming a CMOS image sensor, comprising: providing a first wafer; forming one or more first chips on a first wafer, wherein the first chips have a first specification size; providing a second wafer; forming one or more second chips on a second wafer, wherein the second chips have a second specification size, and the second specification size is different from the first specification size; cutting the first wafer to form a plurality of independent first chips; cutting the second wafer to form a plurality of independent second chips; and splicing the plurality of first chips and the plurality of second chips to form a third chip, so that the utilization rate of the wafer is improved, and the production flexibility of the image sensor chip is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a CMOS image sensor.
Background
An image sensor is a device that converts an optical signal into an electrical signal, and is widely used in digital televisions and visual communication markets. At present, two types of devices, namely, a Charge-Coupled Device (CCD) and a Complementary Metal Oxide Semiconductor (CMOS), are widely used. Among them, CMOS sensors are currently the most attractive and are considered to have the most potential for development.
The application field of the large-area array CMOS image sensor is more and more extensive, and the requirements of the large-area array CMOS image sensor in high-end applications such as medical and industrial X-ray flat panel detectors, scientific research and the like are increasingly increased. Since the size of the photolithographic reticle in CMOS process production is typically less than 3cm x 3cm, the target surface requirements of the image sensor are limited by the reticle size.
The existing large-area array CMOS image sensor needs to be further improved.
Disclosure of Invention
The invention provides a method for forming a CMOS image sensor, which aims to improve the performance of the formed CMOS image sensor.
In order to solve the above technical problem, a technical solution of the present invention provides a method for forming a CMOS image sensor, including: providing a first wafer; forming one or more first chips on a first wafer, wherein the first chips have a first specification size; providing a second wafer; forming one or more second chips on a second wafer, wherein the second chips have a second specification size, and the second specification size is different from the first specification size; cutting the first wafer to form a plurality of independent first chips; cutting the second wafer to form a plurality of independent second chips; and splicing the plurality of first chips and the plurality of second chips to form a third chip.
Optionally, the first chip includes a first pixel region and a first functional region adjacent to the first pixel region.
Optionally, the method for forming the first chip includes: providing a first mask, wherein the first mask comprises a first pixel exposure area and a first function exposure area; performing first graphical processing on the surface of the first wafer by using the first mask, wherein the first graphical processing comprises forming a first pixel area by using a first pixel exposure area; and carrying out second graphical processing on the surface of the first wafer by adopting the first mask, wherein the second graphical processing comprises forming the first functional area by adopting the first functional exposure area.
Optionally, the first chip further includes a first protection region located at a periphery of the first pixel region, and the first protection region is adjacent to the first functional region.
Optionally, the second chip includes a second pixel region and a second functional region adjacent to the second pixel region.
Optionally, the second chip further includes a second protection region located at a periphery of the second pixel region, and the second protection region is adjacent to the second functional region.
Optionally, the forming method of the second chip includes: providing a second mask, wherein the second mask comprises a second pixel exposure area and a second function exposure area; performing third graphical processing on the surface of the second wafer by using the second mask, wherein the third graphical processing comprises forming a second pixel area by using a second pixel exposure area; and performing fourth graphical processing on the surface of the second wafer by using the second mask, wherein the fourth graphical processing comprises forming the second functional area by using the second functional exposure area.
Optionally, the splicing method includes: the first pixel region and the second pixel region are adjacent.
Optionally, the splicing method includes: providing a bearing substrate; and fixing a plurality of first chips and a plurality of second chips on the substrate, wherein the edges of the first chips and the second chips are adjacent.
Optionally, the method further includes: forming one or more fourth chips on the first wafer, wherein the fourth chips have a third specification size; cutting the first wafer to form a plurality of independent fourth chips; the third chip also comprises a plurality of fourth chips, a plurality of first chips and a plurality of second chips which are spliced to form the third chip.
Optionally, the splicing method further includes: and fixing a plurality of fourth chips on the substrate, wherein the fourth chips are adjacent to the edges of the first chips and the second chips.
Optionally, the method further includes: forming one or more fifth chips on the second wafer, the fifth chips having a fourth form factor; cutting the second wafer to form a plurality of independent fifth chips; the third chip also comprises a plurality of fifth chips, a plurality of fourth chips, a plurality of first chips and a plurality of second chips which are spliced to form the third chip.
Optionally, the splicing method further includes: and fixing a plurality of fourth chips and a plurality of fifth chips on the substrate, wherein the fourth chips and the fifth chips are adjacent to the edges of the first chips and the second chips.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the CMOS image sensor provided by the technical scheme of the invention, the plurality of first chips and the plurality of second chips are spliced to form a third chip. On one hand, the specification sizes of the first chip and the second chip are not limited, the first chip and the second chip with two different specification sizes can be spliced together, and the limitation caused by splicing only two image sensors with the same specification size is avoided; on the other hand, the specification size and the number of the first chips formed on the first wafer can be adjusted according to the relative size of the first wafer and the first chips, and the specification size and the number of the second chips formed on the second wafer can be adjusted according to the relative size of the second wafer and the second chips, so that the utilization rate of the wafer is improved, and the production flexibility of the image sensor chips is improved.
Further, splicing a plurality of fourth chips with a plurality of first chips and a plurality of second chips; and the fifth chips are spliced with the fourth chips, the first chips and the second chips, so that the splicing quantity of the chips is flexible, and the image sensor chips with more photosensitive surfaces can be obtained.
Drawings
FIG. 1 is a diagram illustrating an exemplary layout of an image sensor;
FIG. 2 is a schematic diagram of the layout of an image sensor in another embodiment;
fig. 3 to 5 are schematic structural diagrams of steps of a method for forming a CMOS image sensor according to an embodiment of the invention;
fig. 6 to 8 are schematic structural diagrams of steps of a method for forming a CMOS image sensor according to another embodiment of the present invention.
Detailed Description
As described in the background art, the performance of a CMOS image sensor formed by using the existing CMOS image sensor technology needs to be improved. The analysis will now be described with reference to specific examples.
In order to manufacture a large-area array CMOS image sensor, a modular stitching design method is adopted in the prior art, a photosensitive chip is divided into a plurality of modules with repeated functions, and a stitched pattern is formed on a wafer through stitching exposure.
FIG. 1 is a diagram illustrating an exemplary layout of an image sensor.
Referring to fig. 1, the image sensor is rectangular and includes a photosensitive area, a protection area and a functional area, where the protection area includes a first protection edge, a second protection edge, a third protection edge and a protection corner, where:
the photosensitive area comprises a plurality of pixels E distributed along a first direction X in an array mode, each pixel E is rectangular, the photosensitive area is provided with four splicing edges, the photosensitive area is provided with a first splicing edge and a second splicing edge opposite to the first splicing edge along the first direction, the first direction is perpendicular to the second direction along the second direction, and the photosensitive area is provided with a third splicing edge and a fourth splicing edge opposite to the third splicing edge;
the functional area and the photosensitive area are spliced through the first splicing edge, the functional area comprises a plurality of functional modules, and one functional module is correspondingly spliced with one pixel;
the first protective edge and the photosensitive area are spliced through the second splicing edge, the first protective edge comprises a plurality of first protective edge modules, the first protective edge modules are distributed along the second direction in an arrayed mode, and each first protective edge module is correspondingly spliced with one pixel;
the photosensitive regions of the second protective edge are spliced through the third splicing edge, the second protective edge comprises a plurality of second protective edge modules, the second protective edge modules are distributed along the first direction in an arrayed manner, and each second protective edge module is correspondingly spliced with one pixel;
the photosensitive regions of the third protective edge are spliced by the fourth splicing edge, the third protective edge comprises a plurality of third protective edge modules, the third protective edge modules are distributed along the first direction in an arrayed manner, and each third protective edge module is correspondingly spliced with one pixel;
the protection angle comprises four protection angle modules, wherein the first protection edge is spliced with the second protection edge, the first protection edge is spliced with the third protection edge, the second protection edge is spliced with the functional area, and the functional area is spliced with the third protection edge through one protection angle module.
The image sensor adopts the mask with the modular design, namely, one mask is provided with the patterns for forming each module of the image sensor. The wafer-level image sensor can be formed by splicing multiple exposures on one wafer. The wafer level image sensor refers to an image sensor which can be produced on a wafer to the maximum. As image sensors have been developed, it is necessary to manufacture image sensors of larger sizes.
Fig. 2 is a schematic layout diagram of an image sensor in another embodiment.
Referring to fig. 2, four wafer level image sensors, including sensor Chip1, sensor Chip2, sensor Chip3, and sensor Chip4, are spliced on a substrate to form a larger sensor 10.
Referring to fig. 1, fig. 2 is a schematic diagram of an image sensor with a protection area omitted, and each image sensor includes a photosensitive area 102 and a functional area 101 located at one side of the photosensitive area. In order to facilitate reading of data signals of the image sensors, the image sensors can only be spliced with each other through three sides outside the side where the functional area 101 is located, and according to the characteristic that pixels in the photosensitive area 102 of the image sensors need to be arrayed, the splicing mode can only produce a large target surface with a photosensitive surface 2N (N is an integer) times as large as that of a single wafer-level image sensor chip.
However, the actual target surface is not necessarily 2N (N is an integer) times the photosensitive surface of the single wafer level image sensor, and thus the conventional stitching method cannot meet the actual requirement.
In order to solve the above problem, in the method for forming a CMOS image sensor according to the present invention, a plurality of first chips and a plurality of second chips are spliced to form a third chip. On one hand, the specification sizes of the first chip and the second chip are not limited, the first chip and the second chip with two different specification sizes can be spliced together, and the limitation caused by splicing only two image sensors with the same specification size is avoided; on the other hand, the specification size and the number of the first chips formed on the first wafer can be adjusted according to the relative size of the first wafer and the first chips, and the specification size and the number of the second chips formed on the second wafer can be adjusted according to the relative size of the second wafer and the second chips, so that the utilization rate of the wafer is improved, and the production flexibility of the image sensor chips is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 8 are schematic structural diagrams of steps of a method for forming a CMOS image sensor according to an embodiment of the invention.
Referring to fig. 3, a first wafer 300 is provided; one or more first chips 301 are formed on the first wafer 300, and the first chips 301 have a first specification size.
In this embodiment, a first chip 301 is formed on the first wafer 300, and the first chip 301 is a wafer-level image sensor.
The first chip 301 is used to form a third chip, and subsequently, for convenience of description, the first chip 301, the second chip, and the like required for forming a target chip (i.e., the third chip) are referred to as a spliced chip.
In another embodiment, one or more fourth chips are further formed on the first wafer, and the fourth chips have a third specification size. In other embodiments, the number of the spliced chips formed on the second wafer 400 is not limited to one, and the number and the specification size of the spliced chips may be designed according to actual requirements (such as size requirements). Meanwhile, in order to save the wafer, the spliced chips required for forming the third chip can be arranged on the wafer as reasonably as possible.
The first chip 301 includes a first pixel region 301a and a first functional region 301b adjacent to the first pixel region 301. Specifically, the first functional region 301b is located on one side of the first pixel region 301a in the second direction Y. The first functional area 301b is used for readout of image sensor data signals.
The first pixel area 301a is composed of a plurality of pixel arrays, and the photosensitive area of the first chip 301 is determined by the size of the first pixel area 301 a.
In this embodiment, the pixels of the first pixel region 301a are distributed in an array along a first direction X, where the first direction X is perpendicular to the second direction Y.
In this embodiment, the first pixel region 301a is a 6 × 6 pixel array, and each pixel has a size n along the first direction X and a size m along the second direction Y. In other embodiments, the first pixel region is not limited to a 6 × 6 array arrangement, and may be in any array form that can be implemented, and the size of each pixel may be designed according to actual requirements.
It should be noted that, for convenience of description, the size of each pixel in fig. 3 to 8 is represented by a size of m × n, i.e., a size n in the first direction X and a size m in the second direction Y. However, the size of each pixel can be designed according to practical requirements, and is not limited thereto.
The method for forming the first chip 301 comprises the following steps: providing a first mask (not shown) including a first pixel exposure area (not shown), a first functional exposure area (not shown); performing first patterning processing on the surface of the first wafer 300 by using the first mask, wherein the first patterning processing includes forming a first pixel region 301 by using a first pixel exposure region; and performing second patterning processing on the surface of the first wafer 300 by using the first mask, wherein the second patterning processing comprises forming the first functional region 301b by using the first functional exposure region. The sizes of the first chips 301 with different specification sizes can be realized by the design of the first mask with different specification sizes (such as the second pixel exposure areas with different sizes).
The first chip 301 further includes a first protection region 301c located at the periphery of the first pixel region 301a, and the first protection region 301c is adjacent to the first functional region 301 b.
Referring to fig. 4, a second wafer 400 is provided; one or more second chips 401 are formed on the second wafer 400, and the second chips 401 have a second dimension different from the first dimension.
In other embodiments, one or more fifth chips are also formed on the second wafer, the fifth chips having a fourth gauge size.
In this embodiment, two second chips 401 with the same specification and size are formed on the second wafer 400. In other embodiments, the number of chips formed on the second wafer 400 is not limited to two, and the number and the specification size of the chips may be designed according to actual requirements (such as size requirements).
The second chip 401 includes a second pixel region 401a and a second functional region 401b adjacent to the second pixel region 401 a. The second functional area 401b is used for reading out image sensor data signals.
The second pixel area 401a is composed of a plurality of pixel arrays, the photosensitive area of the second chip 401 depends on the size of the second pixel area 401a, and the size of the second pixel area 401a is determined by the size of each pixel and the number of the pixel arrays.
In this embodiment, the pixels of the second pixel region 401a are distributed in an array along a first direction X, where the first direction X is perpendicular to the second direction Y.
In this embodiment, the second pixel region 401a is a 2 × 6 pixel array. In other embodiments, the first pixel region is not limited to a 2 × 6 array arrangement, and may be in any array form that can be implemented.
The method for forming the second chip 401 includes: providing a second mask (not shown) including a second pixel exposure area (not shown), a second functional exposure area (not shown); performing third patterning on the surface of the second wafer 400 by using the second mask, where the third patterning includes forming a second pixel region 401a by using a second pixel exposure region; and performing fourth patterning processing on the surface of the second wafer 400 by using the second mask, wherein the fourth patterning processing includes forming the second functional region 401b by using the second functional exposure region. The size of the second chip 401 with different specification sizes can be realized through the design of the second mask with different specification sizes (such as the second pixel exposure area with different sizes).
In this embodiment, the first mask and the second mask are the same mask. Subsequently, the image sensor chips with more photosensitive surface sizes can be obtained only by flexibly assembling a plurality of spliced chips without increasing a mask plate, so that the cost of the mask plate is saved.
The second chip 401 further includes a second protection region 401c located at the periphery of the second pixel region 401a, and the second protection region 401c is adjacent to the second functional region 401 b.
Referring to fig. 5, the first wafer 300 is diced to form a plurality of independent first chips 301; cutting the second wafer 400 to form a plurality of independent second chips 401; and splicing the plurality of first chips 301 and the plurality of second chips 401 to form a third chip 20.
In another embodiment, the first wafer is cut to form a plurality of independent fourth chips; the third chip further includes: and splicing the plurality of fourth chips with the plurality of first chips and the plurality of second chips to form the third chip.
In another embodiment, the second wafer is diced to form a plurality of independent fifth chips; the third chip further includes: and splicing the fifth chips with the fourth chips, the first chips and the second chips to form the third chip.
In this embodiment, two first chips 301 and two second chips 401 are used for splicing, that is, two first wafers 300 and one second wafer 400 are required to obtain two first chips 301 and two second chips 401. Specifically, first chip 301 is wafer level image sensor, and the photosensitive area of second chip 401 is the 1/3 size of first chip, two first chip 301 and two second chip 401 splices and forms third chip 20, what formed the photosensitive area of third chip 20 is the photosensitive area of nx 4/3 wafer level image sensor. In this embodiment, N is 2, and in other embodiments, N may be any integer.
The splicing method comprises the following steps: the first pixel region 301a and the second pixel region 401b are adjacent. Specifically, a first protection region 301c at the periphery of the first pixel region 301a and a second protection region 401c at the periphery of the second pixel region 401a are adjacent.
The splicing method further comprises the following steps: providing a carrier substrate (not shown); fixing a plurality of the first chips 301 and a plurality of the second chips 401 on the substrate, and making the edges of the plurality of the first chips 301 and the plurality of the second chips 401 adjacent.
In another embodiment, the splicing method further includes: and fixing a plurality of fourth chips on the substrate, wherein the fourth chips are adjacent to the edges of the first chips and the second chips. And the fourth chips are spliced with the first chips and the second chips, so that the splicing quantity of the chips is flexible, and the image sensor chips with more photosensitive surface sizes can be obtained.
In another embodiment, the splicing method further includes: and fixing a plurality of fourth chips and a plurality of fifth chips on the substrate, wherein the fourth chips and the fifth chips are adjacent to the edges of the first chips and the second chips. And the fourth chips are spliced with the first chips and the second chips, so that the splicing quantity of the chips is flexible, and the image sensor chips with more photosensitive surface sizes can be obtained.
To this end, a plurality of the first chips 301 and a plurality of the second chips 401 are spliced to form a third chip 20. On one hand, the specification sizes of the first chip 301 and the second chip 401 are not limited, the first chip 301 and the second chip 401 with two different specification sizes can be spliced together, and the limitation caused by splicing only two image sensors with the same specification size is avoided; on the other hand, the specification size and the number of the first chips 301 formed on the first wafer 300 can be adjusted according to the relative size of the first wafer 300 and the first chips 301, and the specification size and the number of the second chips 401 formed on the second wafer 400 can be adjusted according to the relative size of the second wafer 300 and the second chips 401, so that the utilization rate of the wafer is improved, and the production flexibility of the image sensor chips is improved.
Fig. 6 to 8 are schematic structural diagrams of steps of a method for forming a CMOS image sensor according to another embodiment of the present invention.
Referring to fig. 6, a first wafer 500 is provided; one or more first chips 501 are formed on the first wafer 500, and the first chips 501 have a first specification size.
In this embodiment, a first chip 501 is formed on a first wafer 500, and a fourth chip 502 is formed on the first wafer 500, where the fourth chip 502 has a third specification size.
The first chip 501 includes a first pixel region 501a and a first functional region 501b adjacent to the first pixel region 501. Specifically, the first functional region 501b is located on one side of the first pixel region 501a along the first direction X. The first functional area 501b is used for reading out image sensor data signals. In this embodiment, two first chips 501 are formed on the wafer 500, and can be used for assembling two third chips, so that the area of the wafer is fully utilized, and the wafer cost is saved.
The fourth chip 502 includes a fourth pixel region 502a and a fourth functional region 502b adjacent to the fourth pixel region 502 a. Specifically, the fourth functional region 502b is located on one side of the fourth pixel region 502a along the second direction Y. The fourth functional area 502b is used for reading out image sensor data signals.
The first pixel region 501a is formed by a plurality of pixel arrays, and the photosensitive area of the first chip 501 is determined by the size of the first pixel region 501 a.
The fourth pixel region 502a is composed of a plurality of pixel arrays, and the photosensitive area of the fourth chip 502 is determined by the size of the fourth pixel region 502 a.
Please refer to the method for forming the first chip 301 in the previous embodiment, which is not described herein again. In this embodiment, the first chip 501 and the fourth chip 502 are formed by using the same mask, which is beneficial to saving the cost of the mask.
In this embodiment, the pixels of the first pixel region 501a are distributed in an array along a first direction X, where the first direction X is perpendicular to the second direction Y; the first pixel region 501a is a 3 × 3 pixel array.
In this embodiment, the pixels of the fourth pixel region 502a are distributed in an array along a first direction X, where the first direction X is perpendicular to the second direction Y; the fourth pixel region 502a is a 3 × 4 pixel array.
The first chip 501 further includes a first protection region 501c located at the periphery of the first pixel region 501a, and the first protection region 501c is adjacent to the first functional region 501 b.
The fourth chip 502 further includes a fourth protection region 502c located at the periphery of the fourth pixel region 502a, and the fourth protection region 502c is adjacent to the fourth functional region 502 b.
Referring to fig. 7, a second wafer 600 is provided; one or more second chips 601 are formed on the second wafer 600, and the second chips 601 have a second dimension different from the first dimension.
In this embodiment, a second chip 601 is formed on a second wafer 600, and a fifth chip 602 is further formed on the second wafer 600, where the fifth chip 602 has a fourth specification size.
The second chip 601 includes a second pixel region 601a and a second functional region 601b adjacent to the second pixel region 601 a. The second functional area 601b is used for reading out image sensor data signals.
The second pixel area 601a is composed of a plurality of pixel arrays, the photosensitive area of the second chip 601 depends on the size of the second pixel area 601a, and the size of the second pixel area 601a is determined by the size of each pixel and the number of the pixel arrays.
Please refer to the method for forming the second chip 601 in the previous embodiment, which is not described herein again. In this embodiment, the first chip 501, the fourth chip 502, the second chip 601, and the fifth chip 602 are all formed by using the same mask, which is beneficial to saving the cost of the mask.
In this embodiment, the pixels of the second pixel area 601a are distributed in an array along the first direction X, and the second pixel area 601a is a 4 × 3 pixel array.
In this embodiment, the pixels of the fifth pixel area 602a are distributed in an array along the first direction X, and the second pixel area 602a is a 4 × 4 pixel array.
The second chip 601 further includes a second protection region 601c located at the periphery of the second pixel region 601a, and the second protection region 601c is adjacent to the second functional region 601 b.
The fifth chip 602 further includes a fifth protection region 602c located at the periphery of the fifth pixel region 602a, and the fifth protection region 602c is adjacent to the fifth functional region 602 b.
Referring to fig. 8, the first wafer 500 is diced to form a plurality of independent first chips 501; cutting the second wafer 600 to form a plurality of independent second chips 601; the plurality of first chips 501 and the plurality of second chips 601 are spliced to form a third chip 30.
In this embodiment, the first wafer 500 is diced to form a plurality of independent fourth chips 502.
In this embodiment, the second wafer 600 is cut to form a plurality of independent fifth chips 602; the third chip 30 further includes: and splicing the fifth chips 602 with the fourth chips 601, the first chips 501 and the second chips 502 to form the third chip.
The splicing method comprises the following steps: the first pixel region 501a and the second pixel region 601a are adjacent. Specifically, a first protection region 501c at the periphery of the first pixel region 501a and a second protection region 601c at the periphery of the second pixel region 601a are adjacent.
The splicing method further comprises the following steps: providing a carrier substrate (not shown); fixing a plurality of the first chips 501 and a plurality of the second chips 601 on the substrate, and making the edges of the plurality of the first chips 501 and the plurality of the second chips 601 adjacent.
In this embodiment, the splicing method further includes: fixing a plurality of fourth chips 502 and a plurality of fifth chips 602 on the substrate, and making the plurality of fourth chips 502 and the plurality of fifth chips 602 adjacent to the edges of the plurality of first chips 501 and the plurality of second chips 601. The fourth chips 502 are spliced with the first chip 501 and the second chips 601, so that the splicing quantity of the chips is flexible, and image sensor chips with more photosensitive surface sizes can be obtained. Specifically, the first chip 501, the fourth chip 502, the second chip 601, and the fifth chip 602 are all one. In other embodiments, none of the first chip 501, the fourth chip 502, the second chip 601, and the fifth chip 602 is limited to one.
In this embodiment, the fifth chip 602, the fourth chip 601, the first chip 501 and the second chip 502 are respectively adopted to be spliced to form an image sensor with a 7 × 7 pixel array. In other embodiments, the specification size and the number of the first chips and the fifth chips formed on the first wafer may be adjusted according to the relative sizes of the first wafer and the first chips and the fifth chips; and adjusting the specification size and the number of the second chips and the fifth chips formed on the second wafer according to the relative sizes of the second wafer and the second chips and the fifth chips.
The method of forming the image sensor is not limited to the above description. The first chip, the second chip, the fourth chip and the fifth chip are used as splicing chips, the specification size of the splicing chips formed on a single wafer is not limited to one or two specification sizes listed in the embodiment, the number of the splicing chips is not limited to the number of the chips described in the embodiment, the number of chips with more specification sizes can be formed on more wafers, the specification size of each splicing chip can be designed according to actual requirements, the requirement for splicing to form the third chip with various specification sizes is met, and therefore the production flexibility of the image sensor chip is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A method of forming a CMOS image sensor, comprising:
providing a first wafer;
forming one or more first chips on a first wafer, wherein the first chips have a first specification size;
providing a second wafer;
forming one or more second chips on a second wafer, wherein the second chips have a second specification size, and the second specification size is different from the first specification size;
cutting the first wafer to form a plurality of independent first chips;
cutting the second wafer to form a plurality of independent second chips;
and splicing the plurality of first chips and the plurality of second chips to form a third chip.
2. The method of forming a CMOS image sensor according to claim 1, wherein the first chip includes a first pixel region and a first functional region adjacent to the first pixel region.
3. The method of forming a CMOS image sensor as claimed in claim 2, wherein the method of forming the first chip comprises: providing a first mask, wherein the first mask comprises a first pixel exposure area and a first function exposure area; performing first graphical processing on the surface of the first wafer by using the first mask, wherein the first graphical processing comprises forming a first pixel area by using a first pixel exposure area; and carrying out second graphical processing on the surface of the first wafer by adopting the first mask, wherein the second graphical processing comprises forming the first functional area by adopting the first functional exposure area.
4. The method of claim 2, wherein the first chip further comprises a first protection region located at a periphery of the first pixel region, the first protection region being adjacent to the first functional region.
5. The method of forming a CMOS image sensor according to claim 2, wherein the second chip includes a second pixel region and a second functional region adjacent to the second pixel region.
6. The method of forming a CMOS image sensor according to claim 5, wherein the second chip further includes a second protective region located at a periphery of the second pixel region, the second protective region being adjacent to the second functional region.
7. The method of forming a CMOS image sensor as claimed in claim 5, wherein the method of forming the second chip comprises: providing a second mask, wherein the second mask comprises a second pixel exposure area and a second function exposure area; performing third graphical processing on the surface of the second wafer by using the second mask, wherein the third graphical processing comprises forming a second pixel area by using a second pixel exposure area; and performing fourth graphical processing on the surface of the second wafer by using the second mask, wherein the fourth graphical processing comprises forming the second functional area by using the second functional exposure area.
8. The method of forming a CMOS image sensor of claim 5, wherein the stitching method comprises: the first pixel region and the second pixel region are adjacent.
9. The method of forming a CMOS image sensor of claim 1, wherein the stitching method comprises: providing a bearing substrate; and fixing a plurality of first chips and a plurality of second chips on the substrate, wherein the edges of the first chips and the second chips are adjacent.
10. The method of forming a CMOS image sensor of claim 9, further comprising: forming one or more fourth chips on the first wafer, wherein the fourth chips have a third specification size; cutting the first wafer to form a plurality of independent fourth chips; the third chip also comprises a plurality of fourth chips, a plurality of first chips and a plurality of second chips which are spliced to form the third chip.
11. The method of forming a CMOS image sensor of claim 10, wherein the stitching method further comprises: and fixing a plurality of fourth chips on the substrate, wherein the fourth chips are adjacent to the edges of the first chips and the second chips.
12. The method of forming a CMOS image sensor of claim 10, further comprising: forming one or more fifth chips on the second wafer, the fifth chips having a fourth form factor; cutting the second wafer to form a plurality of independent fifth chips; the third chip also comprises a plurality of fifth chips, a plurality of fourth chips, a plurality of first chips and a plurality of second chips which are spliced to form the third chip.
13. The method of forming a CMOS image sensor of claim 12, wherein the stitching method further comprises: and fixing a plurality of fourth chips and a plurality of fifth chips on the substrate, wherein the fourth chips and the fifth chips are adjacent to the edges of the first chips and the second chips.
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