JP6256562B2 - Solid-state imaging device and electronic device - Google Patents

Description

  The present invention relates to a solid-state imaging device and an electronic apparatus including the solid-state imaging device.

  As a solid-state imaging device, an amplification-type solid-state imaging device represented by a MOS type image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) is known. In addition, a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor is known. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors are often used as solid-state imaging devices mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) from the viewpoint of low power supply voltage and power consumption.

  The MOS type solid-state imaging device has a pixel array (pixel area) in which a unit pixel is formed by a photodiode that serves as a photoelectric conversion unit and a plurality of pixel transistors, and the plurality of unit pixels are arranged in a two-dimensional array. It has a circuit area. The plurality of pixel transistors are formed of MOS transistors, and include transfer transistors, reset transistors, three transistors of amplification and transistors, or four transistors including a selection transistor.

  Conventionally, in such a MOS type solid-state imaging device, a semiconductor chip in which a pixel region in which a plurality of pixels are arranged is formed and a semiconductor chip in which a logic circuit for performing signal processing is electrically connected to each other. Various solid-state imaging devices configured as devices have been proposed. For example, Patent Document 1 discloses a semiconductor module in which a back-illuminated image sensor chip having a micropad for each pixel cell and a signal processing chip in which a signal processing circuit is formed and having a micropad are connected by microbumps. Has been.

  In Patent Document 2, a sensor chip, which is a back-illuminated MOS solid-state imaging device provided with an imaging pixel unit, and a signal processing chip provided with a peripheral circuit for signal processing are mounted on an interposer (intermediate substrate). A device is disclosed. Patent Document 3 has a configuration including an image sensor chip, a thin circuit board, and a logic circuit chip that performs signal processing. A configuration is disclosed in which the thin film circuit board and the logic circuit chip are electrically connected, and the thin film circuit board is electrically connected from the back surface of the image sensor chip through a through-hole via.

  Patent Document 4 discloses a solid-state imaging device in which a through-electrode is provided in a solid-state imaging device supported by a transparent substrate, and the solid-state imaging device is electrically connected to a flexible circuit board via the through-electrode. Furthermore, Patent Document 5 discloses a configuration in which an electrode penetrating a support substrate is provided in a back-illuminated solid-state imaging device.

  As shown in Patent Documents 1 to 3, various techniques for mounting different types of circuit chips such as an image sensor chip and a logic circuit have been proposed. In the conventional technique, a functional chip is almost completed, a through-connection hole is formed, and a chip is formed on one chip in a state where interconnection between chips stacked vertically is possible. Is a feature.

JP 2006-49361 A JP 2007-13089 A JP 2008-130603 A Japanese Patent No. 40000507 JP 2003-31785 A

  As seen in the above-described conventional solid-state imaging device, it has been known as an idea to configure a semiconductor device by connecting different chips stacked by a connection conductor that penetrates a substrate. However, it is necessary to open a connection hole while ensuring insulation on a deep substrate, and it has been difficult to put it to practical use because of the cost efficiency of the manufacturing process required for processing the connection hole and embedding the connection conductor.

  On the other hand, in order to form a small contact hole of about 1 μm, for example, it is necessary to make the upper chip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning and an increase in cost are caused. Moreover, in order to fill the connection hole with a high aspect ratio with the connection conductor, it is necessary to use a CVD film having good coverage such as tungsten (W) as the connection conductor, and the connection conductor material is restricted.

  In order to have economic efficiency that can be easily applied in mass production, the aspect ratio of this connection hole is dramatically reduced to make it easier to form, and it is processed within the conventional wafer manufacturing process without using special connection hole processing. It is desirable to be able to select a technology that can be used. At this time, the contact hole connecting to the upper chip and the contact hole reaching the lower chip through the upper chip have different depths, but it is required that they can be formed in the same etching process or metal filling process as much as possible. ing.

Further, in a solid-state imaging device or the like, it is desired that an image region and a logic circuit that performs signal processing are formed so as to sufficiently exhibit their respective performances, thereby improving performance.
It is desired that not only the solid-state imaging device but also a semiconductor device having another semiconductor integrated circuit be formed so that the performance of each semiconductor integrated circuit can be sufficiently exerted to improve the performance.

  However, if the design including the necessary functions is performed in the upper and lower chips, the circuit area of the portion having the common function is overlapped, so that the chip size is increased and it is difficult to reduce the cost. For this reason, at least in order to reduce costs, it is expected that the design is such that the area of the portion having the same function in the upper and lower chips can be used as much as possible.

In view of the above-described points, the present invention provides a solid-state imaging device and a solid-state imaging device that achieve high performance by fully exhibiting the performance of each of the semiconductor substrates to be stacked, and that achieve mass production and cost reduction. The electronic device provided is provided.

In the solid-state imaging device according to the present invention, a pixel array including a photoelectric conversion unit that generates a signal charge according to the amount of received light and a plurality of pixel transistors is formed, and the first is provided on the side opposite to the light incident surface. A first semiconductor substrate provided with a wiring layer, a second wiring layer formed thereon, a second semiconductor substrate bonded to the first semiconductor substrate, a first semiconductor substrate penetrating the first semiconductor substrate, A through-connection hole that reaches the second wiring layer, a groove and a light shielding film groove provided on the light incident surface side in the first semiconductor substrate, and a connection provided on the light incident surface side in the first semiconductor substrate A hole, a region including the through-connection hole, the connection hole, and the groove portion, and a conductive material formed in the light-shielding film groove portion . The groove portion is formed in a region in contact with the through-connection hole and the connection hole. The conductive material is formed integrally with the through-hole and the conductive material in the connection hole, The light shielding film is formed of a conductive material of the optical film for the groove, the conductive material of the conductive material and the light-shielding film for the groove of the groove, the surface is formed on the same plane, the conductive material and the first wiring layer The second wiring layer is electrically connected.
An electronic apparatus according to the present invention includes the solid-state imaging device according to the present invention.

According to the present invention, a plurality of semiconductor substrates on which a circuit capable of sufficiently exhibiting the respective performances is formed by an optimum process technology is configured so that a plurality of semiconductor substrates are stacked. A solid-state imaging device with high performance can be obtained.

It is a schematic block diagram which shows an example of the MOS solid-state imaging device applied to this invention. It is a schematic diagram of the conventional solid-state imaging device. B and C are schematic views of a solid-state imaging device according to an embodiment of the present invention. It is a figure which shows an example of the circuit of the pixel structure of the MOS solid-state imaging device applied to this invention. It is a schematic block diagram of the principal part which shows the solid-state imaging device which concerns on 1st Embodiment. FIG. 6 is a manufacturing process diagram (part 1) illustrating an example of a manufacturing method of the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 2) illustrating the example of the method for manufacturing the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 3) illustrating the example of the manufacturing method of the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 4) illustrating an example of a manufacturing method of the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 5) illustrating an example of a manufacturing method of the solid-state imaging device according to the first embodiment; It is a manufacturing process figure (the 6) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 7) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 8) which shows the solid-state imaging device which concerns on 1st Embodiment, and its manufacturing method. It is a manufacturing process figure (the 9) which shows the manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 10) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 11) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 12) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 13) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 14) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 15) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a schematic sectional block diagram of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. FIG. 10 is a manufacturing process diagram (part 1) illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 10 is a manufacturing process diagram (part 2) illustrating the manufacturing method of the semiconductor device according to the second embodiment; FIG. 10 is a manufacturing process diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment; FIG. 6D is a manufacturing process diagram (part 4) illustrating the manufacturing method of the semiconductor device according to the second embodiment; It is a manufacturing process figure (the 5) which shows the manufacturing method of the semiconductor device concerning a 2nd embodiment. FIG. 10 is a manufacturing process diagram (part 6) illustrating the manufacturing method of the semiconductor device according to the second embodiment; It is a schematic sectional block diagram of the principal part of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. A, B An example in which a back surface wiring is used on the back surface side of the first semiconductor substrate and an example in which the back surface wiring is not used. A and B are a configuration example of a planar layout when wirings having a common potential are connected between stacked chips, and a configuration example of a planar layout when wirings having a common potential are not connected. It is a flow which shows the design method of the solid-state imaging device of this invention. A and B are manufacturing process diagrams of an upper chip and a lower chip according to the design method of the present invention. A and B are manufacturing process diagrams of an upper chip and a lower chip according to the design method of the present invention. A and B are manufacturing process diagrams of an upper chip and a lower chip according to the design method of the present invention. A and B are manufacturing process diagrams of an upper chip and a lower chip according to the design method of the present invention. It is a schematic block diagram which shows the electronic device which concerns on the 4th Embodiment of this invention.

Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. Schematic configuration example of MOS type solid-state imaging device First Embodiment (Configuration Example of Back-illuminated Solid-State Imaging Device and Method for Manufacturing the Same)
3. Second Embodiment (Structural Example of Semiconductor Device and Manufacturing Method Thereof)
4). Third embodiment (configuration example of solid-state imaging device and design method thereof)
5. Fourth Embodiment (Configuration Example of Electronic Device)

<1. Example of schematic configuration of MOS solid-state imaging device>
FIG. 1 shows a schematic configuration of a MOS type solid-state imaging device applied to the semiconductor device of the present invention. This MOS type solid-state imaging device is applied to the solid-state imaging device of each embodiment. The solid-state imaging device 1 of this example includes a pixel region (so-called pixel array) 3 in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate (not shown) such as a silicon substrate, and a peripheral circuit. And is configured. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor may be added to configure the transistor with four transistors. An equivalent circuit of the unit pixel will be described later. The pixel 2 can be configured as one unit pixel, and can also have a shared pixel structure in which a plurality of pixels share a transistor. This shared pixel structure is a structure in which a plurality of photodiodes share a floating diffusion that constitutes a transfer transistor and a transistor other than the transfer transistor.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 receives an input clock and data for instructing an operation mode, and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8 generates a clock signal and a control signal that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 in the vertical direction sequentially in units of rows, and according to the amount of light received in, for example, a photodiode serving as a photoelectric conversion unit of each pixel 2 through the vertical signal line 9. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2, and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. That is, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise unique to the pixel 2, signal amplification, and AD conversion. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, only buffering may be performed, or black level adjustment, column variation correction, various digital signal processing, and the like may be performed. The input / output terminal 12 exchanges signals with the outside.

  Next, the structure of the MOS type solid-state imaging device according to this embodiment will be described. 2A is a schematic configuration diagram illustrating a structure of a conventional MOS solid-state imaging device, and FIGS. 2B and 2C are schematic configuration diagrams illustrating a structure of a MOS solid-state imaging device according to the present embodiment.

  As shown in FIG. 2A, a conventional MOS solid-state imaging device 151 is configured by mounting a pixel region 153, a control circuit 154, and a logic circuit 155 for signal processing in one semiconductor chip 152. The Normally, the image sensor 156 is configured by the pixel region 153 and the control circuit 154.

  On the other hand, as shown in FIG. 2B, the MOS type solid-state imaging device 21 of the present embodiment has the pixel region 23 and the control region 24 mounted on the first semiconductor chip portion 22, and the second semiconductor chip portion. 26 includes a logic circuit 25 including a signal processing circuit for signal processing. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to constitute the MOS type solid-state imaging device 21 as one semiconductor chip.

  As shown in FIG. 2C, a MOS type solid-state imaging device 27 according to another embodiment of the present invention includes a pixel region 23 mounted on the first semiconductor chip unit 22 and a control region connected to the second semiconductor chip unit 26. 24. A logic circuit 25 including a signal processing circuit is mounted. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to constitute a MOS solid-state imaging device 27 as one semiconductor chip.

  FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 2. The unit pixel 2 according to this circuit example includes a photoelectric conversion unit, such as a photodiode PD, and four pixel transistors. The four pixel transistors are, for example, a transfer transistor 11, a reset transistor 13, an amplification transistor 14, and a selection transistor 15. These pixel transistors are, for example, n-channel MOS transistors.

  The transfer transistor 11 is connected between the cathode of the photodiode PD and the floating diffusion portion 16. Signal charges (here, electrons) that have been photoelectrically converted by the photodiode PD and stored therein are transferred to the floating diffusion section 16 by being given a transfer pulse φTRG to the gate.

  The reset transistor 13 has a drain connected to the power supply VDD and a source connected to the floating diffusion portion 16. Prior to the transfer of signal charges from the photodiode PD to the floating diffusion portion 16, the potential of the floating diffusion portion 16 is reset by applying a reset pulse φRST to the gate.

  For example, the drain of the selection transistor 15 is connected to the power supply VDD, and the source thereof is connected to the drain of the amplification transistor 14. When the selection pulse φSEL is applied to the gate of the selection transistor 15, the pixel 2 can be selected by supplying the power supply VDD to the amplification transistor 14. The selection transistor 15 may be configured to be connected between the source of the amplification transistor 14 and the vertical signal line 9.

  The amplification transistor 14 has a source follower configuration in which a gate is connected to the floating diffusion portion 16, a drain is connected to the source of the selection transistor 15, and a source is connected to the vertical signal line 9. The amplification transistor 14 outputs the potential of the floating diffusion portion 16 after being reset by the reset transistor 13 to the vertical signal line 9 as a reset level. Further, the amplification transistor 14 outputs the potential of the floating diffusion portion 16 after the signal charge is transferred by the transfer transistor 11 to the vertical signal line 9 as a signal level.

  In the solid-state imaging device 1 of the present embodiment, for example, elements such as a photodiode and a plurality of MOS transistors are formed in the first semiconductor chip portion 22 of FIG. 2B or FIG. 2C. Further, the transfer pulse, reset pulse, selection pulse, and power supply voltage are supplied from the control region 24 of FIG. 2B or 2C. Further, the elements after the vertical signal line 9 connected to the drain of the selection transistor are configured in the logic circuit 25 of FIG. 2B or FIG. 2C and are formed in the second semiconductor chip portion 26.

The MOS type solid-state imaging device according to the above-described embodiment has a structure in which different types of semiconductor chips are stacked. As will be described later, the manufacturing method and the structure obtained based on the manufacturing method are characterized. have.
In the embodiment described below, the solid-state imaging device of the present invention and the manufacturing method thereof will be described.

<2. First Embodiment>
[Configuration Example of Solid-State Imaging Device and Method for Manufacturing the Same]
A backside illumination type MOS solid-state imaging device will be described together with its manufacturing method as a semiconductor device according to the first embodiment of the present invention, with reference to FIGS.

FIG. 4 is a schematic cross-sectional configuration diagram (complete drawing) including the electrode pad portion 78 of the solid-state imaging device 81 of the present embodiment. The solid-state imaging device 81 according to the present embodiment includes a first semiconductor chip unit 22 including a pixel array (hereinafter referred to as a pixel region) 23 and a control region 24, and a second semiconductor chip unit on which a logic circuit 25 is mounted. 26 are stacked one above the other in an electrically connected state.
A method for manufacturing the solid-state imaging device 81 according to the present embodiment will be described with reference to FIGS.

  In the first embodiment, first, as shown in FIG. 5, an image sensor in a semi-finished state is formed in each chip portion of a first semiconductor wafer (hereinafter referred to as a first semiconductor substrate) 31. That is, the pixel region 23 and the control region 24 are formed. That is, a photodiode (PD) serving as a photoelectric conversion unit of each pixel is formed in a region serving as each chip portion of the first semiconductor substrate 31 formed of a silicon substrate, and the source / source of each pixel transistor is formed in the semiconductor well region 32. A drain region 33 is formed. The semiconductor well region 32 is formed by introducing a first conductivity type, for example, a p-type impurity, and the source / drain region 33 is formed by introducing a second conductivity type, for example, an n-type impurity. The photodiode (PD) and the source / drain region 33 of each pixel transistor are formed by ion implantation from the substrate surface.

  The photodiode (PD) is formed having an n-type semiconductor region 34 and a p-type semiconductor region 35 on the substrate surface side. A gate electrode is formed on the surface of the substrate constituting the pixel via a gate insulating film, and pixel transistors Tr1 and Tr2 are formed by the source / drain regions 33 paired with the gate electrode. In FIG. 5, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. A pixel transistor Tr1 adjacent to the photodiode (PD) corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD). Each unit pixel 30 is separated by an element isolation region 38.

  On the other hand, on the control region 24 side, a MOS transistor constituting a control circuit is formed on the first semiconductor substrate 31. In FIG. 4, MOS transistors constituting the control region 24 are shown as representatives of the MOS transistors Tr3 and Tr4. Each of the MOS transistors Tr3 and Tr4 is formed by an n-type source / drain region 33 and a gate electrode 36 formed through a gate insulating film.

Next, a first interlayer insulating film 39 is formed on the surface of the first semiconductor substrate 31, and then a contact hole is formed in the interlayer insulating film 39 to form a connection conductor 44 connected to a required transistor. . When forming the connection conductors 44 having different heights, the first insulating thin film 43a is formed of, for example, a silicon oxide film on the entire surface including the upper surface of the transistor, and the second insulating thin film 43b serving as an etching stopper is formed of, for example, a silicon nitride film. And laminate. A first interlayer insulating film 39 is formed on the second insulating thin film 43b. As the first interlayer insulating film 39, for example, a P-SiO film (plasma oxide film) is formed at 10 to 150 nm, and then an NSG (non-doped silicate glass) film or a PSG film (phosphosilicate glass) is formed at 50 nm to 1000 nm. Form with. Then, after forming a dTEOS film with a thickness of 100 to 1000 nm, a P-SiH ₄ film (plasma oxide film) can be formed with a thickness of 50 to 200 nm.

  Thereafter, contact holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched in each part so as to be continuous with the contact holes, thereby forming contact holes. Then, the connection conductor 44 is embedded in each contact hole.

  In addition, after the formation of the second insulating thin film 43b, an insulating spacer layer 42 that separates a desired region in the semiconductor well region 32 of the first semiconductor substrate 31 is formed. The insulating spacer layer 42 is formed by opening a desired position of the first semiconductor substrate 31 from the surface side and embedding an insulating material after forming the second insulating thin film 43b. The insulating spacer layer 42 is formed in a region surrounding the inter-substrate wiring 68 in FIG.

  Next, a plurality of layers, in this example, three layers of copper wirings 40 are formed via the interlayer insulating film 39 so as to connect to the respective connection conductors 44 to form a first multilayer wiring layer 41. Usually, each copper wiring 40 is covered with a barrier metal layer (not shown) to prevent Cu diffusion. The barrier metal layer can be formed, for example, by forming a SiN film or a SiC film at 10 to 150 nm. The interlayer insulating film 39 from the second layer can be formed by forming a dTEOS film (a silicon oxide film formed by a plasma CVD (Chemical Vapor Deposition) method) with a thickness of 100 to 1000 nm. By alternately forming the interlayer insulating film 39 and the copper wiring 40 formed via the barrier metal layer, the first multilayer wiring layer 41 is formed. In the present embodiment example, the first multilayer wiring layer 41 is formed of the copper wiring 40, but it is also possible to use a metal wiring made of other metal materials.

  Through the steps so far, the first semiconductor substrate 31 having the first multilayer wiring layer 41 on the upper part and having the semi-finished pixel region 23 and the control region 24 is formed.

  On the other hand, as shown in FIG. 6, a logic circuit 25 including a signal processing circuit for signal processing in a semi-finished product state is provided in each chip portion of a second semiconductor substrate (semiconductor wafer) 45 made of, for example, silicon. Form. That is, a plurality of MOS transistors constituting the logic circuit 25 are formed in the p-type semiconductor well region 46 on the surface side of the second semiconductor substrate 45 so as to be isolated by the element isolation region 50. Here, the plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, Tr8. Each of the MOS transistors Tr6, Tr7, Tr8 is formed having a pair of n-type source / drain regions 47 and a gate electrode 48 formed through a gate insulating film. The logic circuit 25 can be composed of a CMOS transistor.

  Next, a first interlayer insulating film 49 is formed on the surface of the second semiconductor substrate 45, and then a contact hole is formed in the interlayer insulating film 49, and a connection conductor 54 connected to a required transistor is formed. . When the connection conductors 54 having different heights are formed, the first insulating thin film 43a, for example, a silicon oxide film, and the second insulating thin film 43b, for example, a silicon nitride film serving as an etching stopper are formed on the entire surface including the upper surface of the transistor, as described above. Laminate. A first interlayer insulating film 49 is formed on the second insulating thin film 43b. Then, contact holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched in each part so as to be continuous with the contact holes, thereby forming contact holes. Then, the connection conductor 54 is embedded in each contact hole.

  Thereafter, the second multilayer wiring layer 55 is formed by repeating the formation of the interlayer insulating film 49 and the formation of a plurality of layers of metal wiring. In this embodiment, after forming a three-layer copper wiring 53 in the same manner as the first multilayer wiring layer 41 forming process on the first semiconductor substrate 31, an aluminum wiring is formed on the uppermost layer. As an example of forming 57. The aluminum wiring 57 is formed by first forming the interlayer insulating film 49 on the uppermost copper wiring 53 and then etching away the interlayer insulating film 49 so that a desired position on the uppermost copper wiring 53 is exposed. A contact hole is formed. Then, in a region including the inside of the contact hole, a laminated film made of TiN (lower layer) / Ti (upper layer) to be the barrier metal layer 56 is 5 to 10 nm, or a laminated film made of TaN (lower layer) / Ta (upper layer) is 10 to 10 nm. The film is formed at 100 nm. Thereafter, the contact hole is covered and an aluminum film is formed at a thickness of 500 to 2000 nm, and then an aluminum wiring 57 is formed by patterning into a desired shape. Further, a barrier metal layer 58 required in a later process is formed on the aluminum wiring 57. The barrier metal layer 58 can also have the same configuration as the barrier metal layer 56 formed under the aluminum wiring 57.

  Subsequently, an interlayer insulating film 49 is formed so as to cover the aluminum wiring 57 having the barrier metal layer 58 formed thereon. As the interlayer insulating film 49 on the aluminum wiring 57, for example, an HDP film (high density plasma oxide film) or a P-SiO film (plasma oxide film) is formed with a thickness of 500 to 2000 nm, and then a P-SiO film is further formed thereon. It can be formed by forming a film with a thickness of 100 to 2000 nm. As a result, the second multilayer wiring layer 55 is formed which includes the three-layer copper wiring 53 formed through the interlayer insulating film 49 and the aluminum wiring 57 formed in the uppermost layer.

  A warp correction film 59 is formed on the second multilayer wiring layer 55 to reduce the warp when the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded together. The warp correction film 59 can be formed, for example, by forming a P-SiN film or a P-SiON film (plasma oxynitride film) at 100 to 2000 nm.

  Through the steps so far, the second semiconductor substrate 45 having the second multilayer wiring layer 55 on the upper part and having a semi-finished logic circuit is formed.

  Next, as shown in FIG. 7, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded together so that the first multilayer wiring layer 41 and the second multilayer wiring layer 55 face each other. The bonding is performed with an adhesive, for example. In the case of bonding with an adhesive, an adhesive layer 60 is formed on one side of the bonding surface of the first semiconductor substrate 31 or the second semiconductor substrate 45, and the adhesive layer 60 is overlapped via the adhesive layer 60. Join them together. In the present embodiment example, the first semiconductor substrate 31 in which the pixel region is configured is disposed in the upper layer, and the second semiconductor substrate 45 is disposed in the lower layer and bonded together.

  In this embodiment, the first multilayer wiring layer 41 above the first semiconductor substrate 31 and the second multilayer wiring layer 55 above the second semiconductor substrate 45 are bonded together via the adhesive layer 60. As an example, in addition to this, an example of bonding by plasma bonding may be used. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55, respectively. To do. The joining surface on which this film is formed is overlapped by plasma treatment, and then annealed to join them together. The bonding process is preferably performed by a low-temperature process of 400 ° C. or lower that does not affect the wiring or the like.

  Then, the first semiconductor substrate 31 and the second semiconductor substrate 45 having a multilayer wiring layer on the top are stacked and bonded together, thereby forming a stacked body 81a composed of two different substrates.

  Next, as shown in FIG. 8, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface side of the first semiconductor substrate 31. This thinning is performed so that the photodiode (PD) faces. As the first semiconductor substrate 31, for example, a semiconductor substrate formed using a p-type high-concentration impurity layer as an etching stopper layer (not shown) is used. Can be After thinning, a p-type semiconductor layer (not shown) for suppressing dark current is formed on the back surface of the photodiode (PD). The thickness of the first semiconductor substrate 31 is, for example, about 600 μm, but the thickness is reduced to, for example, about 3-5 μm.

  Conventionally, such thinning has been performed by attaching a separately prepared support substrate to the first multilayer wiring layer 41 formed on the first semiconductor substrate 31. However, in the present embodiment, the thickness of the first semiconductor substrate 31 is reduced by using the second semiconductor substrate 45 on which the logic circuit 25 is formed as a support substrate. The back surface of the first semiconductor substrate 31 is a light incident surface when configured as a back-illuminated solid-state imaging device.

Next, as shown in FIG. 9, an antireflection film 61 is formed on the back surface of the first semiconductor substrate 31. The antireflection film 61 can be added with an effect of suppressing dark current by forming, for example, TaO ₂ or HfO ₂ at 5 to 100 nm and performing necessary heat treatment. Thereafter, an insulating film 62 is formed on the antireflection film 61 by forming a plasma SiO film with a thickness of 100 to 1500 nm.

  Next, as shown in FIG. 10, a groove portion 64 is formed in a desired region inside the insulating spacer layer 42, and a light shielding film groove portion 82 is formed in a light shielding region where light shielding is necessary. The groove portion 64 and the light shielding film groove portion 82 are formed by forming an opening by etching from the upper surface of the insulating film 62 formed on the back surface side of the first semiconductor substrate 31, and do not reach, for example, the first semiconductor substrate 31. Form to depth.

  Next, as shown in FIG. 11, the copper wiring from the desired bottom region of the groove 64 formed inside the insulating spacer layer 42 to the lowermost layer (uppermost in FIG. 11) of the first multilayer wiring layer 41. The hole is opened to a depth just before reaching 40 and a connection hole 66 is formed.

  Similarly, a through-connection hole 65 penetrating the bonding surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55 from a desired bottom region of the groove 64 formed inside the insulating spacer layer 42 is formed. Form. The through-hole 65 is formed by opening to a depth just before reaching the uppermost aluminum wiring 57 of the second multilayer wiring layer 55 formed on the second semiconductor substrate 45. At this time, the diameter of the through-connection hole 65 is about 1.5 to 10 times larger than the diameter of the connection hole 66, more preferably about 3 to 4 times larger.

  When the diameter of the through-hole 65 is smaller than 1.5 times the diameter of the through-hole 66, the aspect ratio of the through-hole 65 is increased, and voids are generated when the conductive material is embedded in the hole in a later process. There is a risk. Moreover, when the diameter of the through-connection hole 65 is larger than 10 times that of the connection hole 66, there is a problem that the area occupied by the through-connection hole 65 becomes large and the apparatus cannot be downsized. Therefore, by increasing the diameter of the through-hole 65 by about 1.5 to 10 times the diameter of the connection hole 66, it is possible to obtain a hole having an optimal aspect ratio for embedding a conductive material and having a small layout space. it can.

  Since the connection hole 66 and the through-connection hole 65 are formed after the first semiconductor substrate 31 is thinned (step of FIG. 8), the aspect ratio becomes small and can be formed as a fine hole. Further, the connection hole 66 is opened until just before reaching the lowermost layer, that is, the copper wiring 40 closest to the first semiconductor substrate 31 in the first multilayer wiring layer 41 on the first semiconductor substrate 31. Therefore, the opening depth becomes shallower, which is advantageous for forming fine holes.

Next, an insulating layer 67 made of, for example, a SiO ₂ film is formed in the region including the side wall and the bottom of the connection hole 66 and the through connection hole 65, and then etched back. Thus, the insulating layer 67 is left only on the side walls of the connection hole 66 and the through-connection hole 65 as shown in FIG. Thereafter, the bottoms of the connection hole 66 and the through connection hole 65 are further etched away. As a result, the lowermost copper wiring 40 of the first multilayer wiring layer 41 is connected to the connection hole 66, and the uppermost aluminum wiring 57 (strictly speaking, the second multilayer wiring layer 55 is connected to the through-connection hole 65. The barrier metal layer 58) above the aluminum wiring is exposed.

  As a result, the connection hole 66 reaches the copper wiring 40 of the first multilayer wiring layer 41. The through-connection hole 65 passes through the bonding surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55 and reaches the aluminum wiring 57 formed in the second multilayer wiring layer 55.

  At this point in time, the pixel array manufacturing process has not undergone the processing steps of the on-chip color filter and the on-chip lens, and is incomplete. At the same time, the connection hole 66 formed on the copper wiring 40 and the through connection hole 65 formed on the aluminum wiring 57 can be processed and formed by extension of the conventional wafer process. On the other hand, the logic circuit 25 is a process up to the uppermost metal wiring that is optimal as a circuit technology, and is not completed. In this manner, since the different types of substrates, which are semi-finished products, are bonded together, the manufacturing cost can be reduced as compared with the case where the different types of finished substrates are bonded.

  Thereafter, as shown in FIG. 13, a conductive material such as copper is formed in a region including the groove 64, the light shielding film groove 82, the connection hole 66, and the through-connection hole 65, and a CMP (Chemical Mechanical Polising) method is used. Polish the surface. Thereby, only the conductive material of the groove portion 64, the light shielding film groove portion 82, the connection hole 66, and the through-connection hole 65 is left. Thereby, the inter-substrate wiring 68 is formed in the region in the insulating spacer layer 42, and the light shielding film 63 is formed in the light shielding region. In the present embodiment, the inter-substrate wiring 68 formed in the connection hole 66 and the inter-substrate wiring 68 formed in the through-connection hole 65 are electrically connected by the connection wiring 68 a made of damascene wiring formed in the groove portion 64. Connected. The light shielding film 63 is also formed by the damascene method. Then, the copper wiring 40 and the second multilayer wiring layer formed in the first multilayer wiring layer 41 are formed by embedding the groove 64, the light shielding film groove 82, the connection hole 66, and the through-connection hole 65 with a conductive material. The aluminum wiring 57 formed in 55 is electrically connected.

  At this time, since the barrier metal layer 58 is formed on the aluminum wiring 57 formed in the second multilayer wiring layer 55 on the second semiconductor substrate 45, the inter-substrate wiring 68 is formed of copper. However, copper diffusion is prevented. In addition, an insulating layer 67 is formed on the side wall penetrating the first semiconductor substrate 31 in the connection hole 66 and the through connection hole 65. For this reason, the inter-substrate wiring 68 and the first semiconductor substrate 31 are electrically separated and are not connected. Further, in the present embodiment example, the inter-substrate wiring 68 is formed in the region of the insulating spacer layer 42 formed on the first semiconductor substrate 31, so that the inter-substrate wiring 68 and the first semiconductor are also formed. The substrate 31 is prevented from being electrically connected.

  In the formation process of the inter-substrate wiring 68 of the present embodiment example, the damascene method in which the groove portion 64, the light shielding film groove portion 82, the connection hole 66, and the through connection hole 65 are formed in three stages and copper is embedded is used. It is not limited to this. Between the substrates to which the copper wiring 40 of the first multilayer wiring layer 41 above the first semiconductor substrate 31 and the aluminum wiring 57 of the second multilayer wiring layer 55 above the second semiconductor substrate 45 are electrically connected Various modifications are possible as long as the wiring 68 is formed.

  For example, the inter-substrate wiring 68 can be formed by a CVD method, a sputtering method, or the like, and can be formed by normal lithography and dry etching. However, it is difficult to tolerate deterioration of sensitivity by stacking wiring layers. For this reason, it is desirable to apply a damascene wiring structure in which the accumulation of insulating films is small.

  In this embodiment, the light shielding film groove 82 for forming the light shielding film 63 is processed simultaneously with the groove 64 for forming the inter-substrate wiring 68. However, the groove 64, the connection hole 66, You may form after formation of the through-connection hole 65 and the insulating spacer layer 42. Also in this case, the light shielding film groove 82 is formed in the same layer as the groove 64, and the conductive material is embedded in the light shielding film groove 82 in order to conduct the conductive to the groove 64, the connection hole 66, and the through connection hole 65. Simultaneous with material embedding. Processing the light shielding film groove 82 simultaneously with the groove 64, the connection hole 66, and the through connection hole 65 simplifies the process. However, in this case, when the insulating spacer layer 42 is formed, the insulating spacer layer 42 is also formed in the light shielding film groove 82, and a desired line width of the light shielding film 63 may not be obtained. . When the pixel is miniaturized, it is more preferable to form the light shielding film groove 82 in a separate process from the groove 64, the connection hole 66, and the through connection hole 65.

  Conventionally, the light shielding film 63 is separately formed of tungsten, aluminum, or the like in the step before the formation of the inter-substrate wiring 68. However, the light shielding film 63 is formed by a damascene method at the same time as the formation of the inter-substrate wiring 68. Can be simplified. At the same time, the insulating film thickness on the light receiving part side (back side) of the first semiconductor substrate 31 can be reduced, which contributes to improvement in sensitivity.

  Further, since the through-connection hole 65 becomes deep within a range of 1.5 to 10 times the depth of the connection hole 66, even if the connection hole 66 is embedded with a conductive material, the through-connection is the same. Voids may occur in the conductive material in the holes 65.

  In the present embodiment, by opening the through-connection hole 65 and the connection hole 66 having different opening sizes according to the depth, holes having an aspect ratio that is optimal for embedding a conductive material and that does not increase the layout space are provided. It is possible to form. Thereby, even in the deep through-hole 65, it is possible to prevent the generation of voids when the conductive material is embedded.

  In the present embodiment, the connection hole 66 is connected to the lowermost copper wiring 40 of the first multilayer wiring layer 41 on the first semiconductor substrate 31, so that the periphery of the connection hole 66 or directly below it. Can be used as an effective space through which wiring can pass. For this reason, it works advantageously for chip reduction.

  In this embodiment, the insulation between the inter-substrate wiring 68 and the first semiconductor substrate 31 is performed by the insulating layer 67 and the insulating spacer layer 42. However, an example in which one of them is configured may be used. . When the insulating spacer layer 42 is not formed, a region corresponding to the insulating spacer layer 42 is not necessary, so that the pixel area can be reduced and the photodiode (PD) area can be increased.

  Next, as shown in FIG. 14, a cap film 72 is formed so as to cover the upper portion of the inter-substrate wiring 68 and the light shielding film 63. The cap film 72 can be formed, for example, by forming a SiN film or a SiCN film with a thickness of 10 to 150 nm. Thereafter, an opening is formed in the insulating film 62 above the photodiode (PD), and a waveguide material film 69 is formed in a desired region including the opening. For example, SiN can be used as the waveguide material film 69, and the waveguide material 70 is formed by the waveguide material film 69 formed in the opening. By forming the waveguide 70, the light incident from the back side of the first semiconductor substrate 31 is efficiently condensed on the photodiode (PD). Thereafter, a planarizing film 71 is formed on the entire surface including the waveguide material film 69.

  In this embodiment, the cap film 72 and the waveguide material film 69 on the cap film 72 are separately formed in separate steps. However, the waveguide material film 69 may be used as the cap film 72. In this embodiment, the waveguide 70 is formed on the light incident surface side of the photodiode (PD). However, the waveguide 70 may not be formed.

  Next, as shown in FIG. 15, on-chip color filters 73 of, for example, red (R), green (G), and blue (B) are formed on the planarizing film 71 corresponding to each pixel. The on-chip color filter 73 can be formed on a photodiode (PD) constituting a desired pixel array by depositing and patterning an organic film containing a pigment or dye of a desired color. Thereafter, an on-chip lens material 74 a is formed on the pixel array region including the upper part of the on-chip color filter 73. As the on-chip lens material 74a, for example, an organic film or an inorganic film such as SiO, SiN, or SiON can be used, and the film is formed to 3000 nm to 4500 nm.

Next, as shown in FIG. 16, an on-chip lens resist film 75 is formed in a region corresponding to each pixel above the on-chip lens material 74a to a thickness of, for example, 300 nm to 1000 nm, and an etching process is performed. Thereby, the shape of the resist film 75 for the on-chip lens is transferred to the on-chip lens material 74a, and the on-chip lens 74 is formed above each pixel as shown in FIG. Thereafter, an oxide film such as the insulating film 62 formed on the first semiconductor substrate 31 is etched by CF ₄ gas (flow rate: 10 to 200 sccm) to expose the first semiconductor substrate 31.

  Next, as shown in FIG. 18, a resist film 76 in which the electrode pad portion 78 of FIG. 3 is opened is formed on the on-chip lens 74. As shown in FIG. 18, the resist film 76 is formed so that the opening end portion is closer to the pixel side than the end portion of the on-chip lens 74.

Next, an etching process is performed under desired etching conditions using the resist film 76 as a mask. As a result, as shown in FIG. 19, a through-opening that is etched from the first semiconductor substrate 31 side, which is the uppermost substrate, and penetrates the bonding surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55. A portion 77 is formed. Then, the through opening 77 is formed until the aluminum wiring 57 formed in the second multilayer wiring layer 55 formed on the second semiconductor substrate 45 which is the lowermost substrate is exposed. In this etching step, for example, SF ₆ / O ₂ -based gas (flow rates are SF ₆ : 50 to 500 sccm, O ₂ : 10 to 300 sccm) and etching is performed for 1 to 60 minutes, whereby the first semiconductor is processed. The substrate 31 can be removed by etching. After that, the oxide film or the like up to the aluminum wiring 57 can be removed by etching using a CF ₄ gas (flow rate: 10 to 150 sccm) for 1 to 100 minutes.

  The aluminum wiring 57 exposed in this way is used as an electrode pad portion 78 used when connecting to an external wiring. Hereinafter, the exposed aluminum wiring 57 is referred to as an electrode pad portion 78. It is preferable that a plurality of electrode pad portions 78 are formed on three or four sides outside the pixel region formed on each chip.

  And the laminated body 81a formed by laminating | stacking two semiconductor substrates as shown in FIG. 19 is divided | segmented into each chip | tip part by carrying out dicing process after that. Thereby, as shown in FIG. 4, the solid-state imaging device 81 which consists of the 1st semiconductor chip part 22 and the 2nd semiconductor chip part 26 is completed.

  As shown in FIG. 4, the solid-state imaging device 81 formed in this way can connect a bonding wire 79 to the electrode pad portion 78, and can be connected to an external wiring of the mounting substrate by the bonding wire 79. Then, the external wiring is electrically connected to the electrode pad portion 78 so that the wirings of the first multilayer wiring layer 41 and the second multilayer wiring layer 55 connected by the inter-substrate wiring 68 are also electrically connected. Connected to.

  In the solid-state imaging device 81 of the first embodiment, the bonding wire 79 is connected to the electrode pad portion 78. However, the solder pad can be used to connect the electrode pad portion 78 and the external wiring. A bonding wire or a solder bump can be selected according to the user's request.

  In the first embodiment, the inspection for the solid-state imaging device 81 on the semiconductor wafer is performed using the electrode pad portion 78. The inspection is performed twice, that is, inspection in a wafer state and inspection in a final module state after cutting into chips.

  According to the solid-state imaging device 81 and the manufacturing method thereof according to the first embodiment, the pixel region 23 and the control region 24 are formed in the chip portion on the first semiconductor substrate 31 side, and the chip on the second semiconductor substrate 45 side. A logic circuit 25 for signal processing is formed in the part. As described above, since the pixel array function and the logic function are formed in different chip portions, an optimum process forming technique can be used for each of the pixel array and the logic circuit. Therefore, the performance of each of the pixel array and the logic circuit can be sufficiently exhibited, and a high-performance solid-state imaging device can be provided.

  If the configuration of FIG. 2C is adopted, it is only necessary to form a pixel region 23 for receiving light on the first semiconductor chip unit 22 side, and the control region 24 and the logic circuit 25 are separated to form the second semiconductor chip unit. 26 can be formed. As a result, the optimum process technology for each functional chip can be selected independently, and the area of the product module can be reduced.

  Since the pixel array and the logic circuit can be mixedly mounted by the conventional wafer process technology, manufacturing is also easy.

  In this embodiment, the first semiconductor substrate 31 having the pixel region 23 and the control region 24 and the second semiconductor substrate 45 having the logic circuit 25 are bonded together in a semi-finished state, and the first semiconductor substrate 31 is thinned. That is, the second semiconductor substrate 45 is used as a support substrate when the first semiconductor substrate 31 is thinned. As a result, the members can be saved and the manufacturing process can be saved. Furthermore, since the through-connection hole 65 and the connection hole 66 are formed after the thinning, the aspect ratio of the hole is reduced, and a highly accurate connection hole can be formed.

  The inter-substrate wiring 68 can be formed by embedding a conductive material in the low aspect ratio through-connection hole 65 and connection hole 66, so that the metal material such as tungsten (W) having good coverage is of course covered. For example, a metal material such as copper (Cu) can be used. That is, there is no restriction on the conductor material constituting the inter-substrate wiring 68. Thereby, the electrical connection between the pixel region and the control circuit and the logic circuit can be performed with high accuracy. Therefore, it is possible to manufacture a high-performance solid-state imaging device while achieving mass productivity, suppressing manufacturing costs.

  Furthermore, in the present embodiment example, the through opening 77 formed to open the electrode pad portion 78 is formed so as to penetrate the bonding surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. The electrode pad portion 78 is composed of the wiring of the second multilayer wiring layer 55 below the bonding surface. As a result, the electrode pad portion 78 is formed in a lower layer than the bonding surface which is a fragile surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. For this reason, for example, when the bonding wire 79 is pressed against the electrode pad portion 78, it is possible to reduce the bonding stress applied to the bonding surface which is a fragile surface. Thereby, it can prevent that a crack generate | occur | produces from a weak joint surface at the time of wire bonding.

  In the present embodiment, an example in which two layers of semiconductor wafers are stacked is used, but the present invention can be applied to a configuration in which two or more layers are stacked. In that case, a through opening is formed so that the wiring constituting the wiring layer of the lowermost semiconductor wafer is exposed, and the exposed wiring is used as a wiring pad portion. Thereby, when connecting an external wiring and an electrode pad part, it can reduce that a stress generate | occur | produces on the weak joint surface between board | substrates.

  Further, as in the present embodiment example, in the backside illumination type solid-state imaging device, it is necessary to bring the photodiode serving as the light receiving portion closer to the circuit, and thus the semiconductor layer as described above must be thinned. Yes. Further, it is preferable that the opening for exposing the wiring below the bonding surface is shallower. Accordingly, when the upper semiconductor substrate (in this embodiment example, the first semiconductor substrate) is a solid-state imaging device having a pixel array as in this embodiment example, the first semiconductor layer is thinned. It is preferable to open the electrode pad portion from the semiconductor substrate side.

  In the solid-state imaging device according to the above-described embodiment, the signal charge is an electron, the first conductivity type is a p-type, and the second conductivity type is an n-type, but the signal charge is a hole. It can also be applied to. In this case, the conductivity type of each semiconductor substrate, semiconductor well region or semiconductor region is reversed, n-type being the first conductivity type and p-type being the second conductivity type.

  In the first embodiment described above, the MOS type solid-state imaging device is taken as an example, but the present invention can also be applied to a semiconductor device. Next, a semiconductor device having a structure in which different types of chips are stacked will be described as a second embodiment of the present invention.

<3. Second Embodiment>
[Configuration example of semiconductor device and manufacturing method thereof]
A semiconductor device according to the second embodiment of the present invention will be described together with a manufacturing method thereof with reference to FIGS. The semiconductor device 140 according to the present embodiment is configured by stacking a first semiconductor substrate 101 on which a first semiconductor integrated circuit is formed and a second semiconductor substrate 102 on which a second semiconductor integrated circuit is formed. It is a semiconductor device. 20, parts corresponding to those in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

  In the second embodiment, first, as shown in FIG. 21, the first semiconductor integrated circuit in a semi-finished state, in this example, is formed in each chip portion of the first semiconductor substrate (semiconductor wafer) 101. A logic circuit is formed. That is, a plurality of MOS transistors Tr9, Tr10, and Tr11 are formed in regions to be the chip portions of the semiconductor well region 108 formed on the first semiconductor substrate 101 made of a silicon substrate. Each of the MOS transistors Tr9 to Tr11 includes a pair of source / drain regions 105 and a gate electrode 106 formed via a gate insulating film. The MOS transistors Tr9 to Tr11 are isolated by the element isolation region 100.

  Although a plurality of MOS transistors are formed, in FIG. 21, the MOS transistors Tr9 to Tr11 are shown as representatives. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors Tr9 to Tr11 can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when an n-channel MOS transistor is formed, n-type source / drain regions are formed in the p-type semiconductor well region 108. When a p-channel MOS transistor is formed, p-type source / drain regions are formed in an n-type semiconductor well region.

  The first semiconductor integrated circuit may be a semiconductor memory circuit, for example, instead of the logic circuit. In this case, a logic circuit serving as a second semiconductor integrated circuit described later is used for signal processing of the semiconductor memory circuit.

In addition, after the formation of the second insulating thin film 43b, an insulating spacer layer 113 that separates a desired region in the semiconductor well region 108 of the first semiconductor substrate 101 is formed as in the first embodiment. The insulating spacer layer 113 is formed by opening a desired position of the first semiconductor substrate 101 from the back surface side and embedding an insulating material after the second insulating thin film 43b is formed. The insulating spacer layer 113 is formed in a region surrounding the inter-substrate wiring 115 in FIG.

  Next, a first multilayer wiring layer 107 in which a plurality of layers, in this example, three layers of copper wirings 104 are stacked is formed on the first semiconductor substrate 101 with an interlayer insulating film 103 interposed therebetween. In the present embodiment, the wiring constituting the first multilayer wiring layer 107 is made of copper, but the metal wiring can be made of other metal materials. These first multilayer wiring layers 107 can be formed in the same manner as in the first embodiment. Each MOS transistor Tr9 to Tr11 is connected to a required first-layer copper wiring 104 via a connection conductor 112. Further, the three layers of copper wiring 104 are connected to each other through a connection conductor 112.

  On the other hand, as shown in FIG. 22, a second semiconductor integrated circuit in a semi-finished state, in this example, a logic circuit is formed in a region to be each chip portion of the second semiconductor substrate (semiconductor wafer) 102. That is, similarly to FIG. 20, a plurality of MOS transistors Tr12, Tr13, and Tr14 are formed in the regions to be the chip portions of the semiconductor well region 116 formed in the second semiconductor substrate 102 made of silicon. Each of the MOS transistors Tr12 to Tr14 includes a pair of source / drain regions 117 and a gate electrode 118 formed through a gate insulating film. Further, the MOS transistors Tr12 to Tr14 are separated by an element isolation region 127.

  Although a plurality of MOS transistors are formed, in FIG. 24, the MOS transistors Tr12 to Tr14 are shown as representatives. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when an n-channel MOS transistor is formed, n-type source / drain regions are formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, p-type source / drain regions are formed in the n-type semiconductor well region.

  Next, a second multilayer wiring layer 124 in which a plurality of layers, in this example, four layers of metal wirings are stacked is formed on the second semiconductor substrate 102 with an interlayer insulating film 119 interposed therebetween. In this embodiment, an example in which three layers of copper wiring 120 and one layer of aluminum wiring 121 formed in the uppermost layer is formed. Each MOS transistor Tr12 to Tr14 is connected to a required first-layer copper wiring 120 via a connection conductor 126. Further, the three-layer copper wiring 120 and the aluminum wiring 121 are connected to each other by a connection conductor 126. Furthermore, also in this embodiment, barrier metal layers 129 and 130 are formed above and below the aluminum wiring 121, and the aluminum wiring 121 is connected to the lower copper wiring 120 through the lower barrier metal layer 129. Has been. The second multilayer wiring layer 124 can be formed in the same manner as the multilayer wiring layer of the first embodiment.

  Then, a warp correction film 123 is formed on the second multilayer wiring layer 124 to reduce the warp when the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded together. The warp correction film 123 can also be formed in the same manner as in the first embodiment.

  Next, as shown in FIG. 23, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded together so that the first multilayer wiring layer 107 and the second multilayer wiring layer 124 face each other. . The bonding is performed with an adhesive, for example. In the case of bonding with an adhesive, an adhesive layer 125 is formed on one side of the bonding surface of the first semiconductor substrate 101 or the second semiconductor substrate 102, and the adhesive layer 125 is overlapped via the adhesive layer 125. Join them together. In the present embodiment example, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded to each other via the adhesive layer 125, but other examples may be bonded by plasma bonding. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surface between the first semiconductor substrate 101 and the second semiconductor substrate 102, respectively. The joining surface on which this film is formed is overlapped by plasma treatment, and then annealed to join them together. The bonding process is preferably performed by a low-temperature process of 400 ° C. or lower that does not affect the wiring or the like. Then, the first semiconductor substrate 101 and the second semiconductor substrate 102 are stacked and bonded to each other, so that a stacked body 140a including two different substrates is formed.

  Next, as shown in FIG. 24, one first semiconductor substrate 101 is thinned by grinding and polishing from the back surface side. When the thickness of the first semiconductor substrate 101 is, for example, about 600 μm, the first semiconductor substrate 101 is thinned so that the film thickness is, for example, about 5-10 μm.

  Next, as shown in FIG. 25, after thinning, the groove 164, the through-connection hole 165, and the connection hole 166 are formed in the insulating spacer layer 113 in the same process as in FIGS. 10 to 13 in the first embodiment. Form. Thereafter, the inter-substrate wiring 115 is formed in the groove 164, the through-connection hole 165 and the connection hole 166 with the insulating layer 114 interposed therebetween. Although illustration is omitted, a light shielding film is formed in the light shielding region as necessary, as in the first embodiment. Also in the present embodiment example, the through-connection hole 165 and the connection hole 166 are formed after the first semiconductor substrate 101 is thinned, so that the aspect ratio becomes small and can be formed as fine holes. Also in the present embodiment example, by separately opening the through connection holes 165 and the connection holes 166 having different opening sizes according to the depth, the aspect ratio is optimum for embedding the conductive material and the layout space is also provided. It is possible to form a hole that does not become large. Thereby, even in the deep through-hole 165, generation of voids when the conductive material is embedded can be prevented.

  The circuit formed on the first semiconductor substrate 101 and the circuit formed on the second semiconductor substrate 102 are electrically connected by the inter-substrate wiring 115. Thereafter, as in the first embodiment, a cap film 72 is formed on the entire surface including the upper portion of the inter-substrate wiring 115.

Next, by using a mask (not shown) in which a desired region is opened, etching is performed as shown in FIG. 26 to form a through opening 132 penetrating the first semiconductor substrate 101, and the aluminum wiring 121. To expose. As a result, an electrode pad portion 142 made of the exposed aluminum wiring 121 is formed.
Thereafter, the semiconductor device 140 according to the present embodiment shown in FIG. 20 is completed by dicing to divide each chip portion.

  As shown in FIG. 20, each of the divided chips can be connected to an electrode pad 142 with a bonding wire 131, and can be connected to an external wiring of the mounting substrate by the bonding wire 131. Then, the external wiring is electrically connected to the electrode pad portion 142, whereby each wiring (circuit) formed on the first semiconductor substrate 101 and the second semiconductor substrate 102 connected by the inter-substrate wiring 115. Are also electrically connected.

  According to the semiconductor device 140 and the manufacturing method thereof according to the second embodiment, the first semiconductor integrated circuit and the second semiconductor integrated circuit are respectively formed on different chip portions by the optimum process technology as described above. And a high-performance semiconductor integrated circuit can be provided. In addition, the first and second semiconductor wafers are bonded and thinned in the semi-finished product state, and after the electrical connection of the first and second semiconductor integrated circuits, the finished product state is formed into a chip, thereby reducing the manufacturing cost. Reduction can be achieved.

  In addition, the same effects as those of the first embodiment can be obtained.

In the first embodiment and the second embodiment described above, the inter-substrate wiring includes the first semiconductor integrated circuit formed on the first semiconductor substrate and the second semiconductor formed on the second semiconductor substrate. An example of using only as wiring for electrically connecting a body integrated circuit is shown. However, the present invention is not limited to this. For example, by using inter-substrate wiring, wiring of the same potential that is separately formed in the first semiconductor substrate and the second semiconductor substrate (for example, power supply wiring or A part of the ground wiring) can be used in common for each substrate.
Hereinafter, an example in which the inter-substrate wiring is formed as a power supply wiring and a ground wiring that are commonly used for the first semiconductor substrate and the second semiconductor substrate will be described.

<4. Third Embodiment>
FIG. 27 shows a schematic configuration diagram of a solid-state imaging apparatus according to the third embodiment of the present invention. In FIG. 27, parts corresponding to those in FIG.

  FIG. 27 shows a region including the pixel region 23 and the control region 24 of the solid-state imaging device, and illustration of transistors and photodiodes is omitted for simplification.

  As shown in FIG. 27, in the pixel region 23, the copper wiring 40 a that outputs the pixel signal formed on the first semiconductor substrate 31 is the uppermost layer of the second multilayer wiring layer 55 through the inter-substrate wiring 68. It is connected to a signal wiring 57a formed by wiring. In this case, in the circuit configuration shown in FIG. 3, the inter-substrate wiring is formed between the wiring connected to the drain of the selection transistor formed in the first semiconductor substrate 31 and the signal wiring. Processing subsequent to the signal wiring 57 a is performed in the logic circuit 25 configured by the second semiconductor substrate 45.

  In this embodiment, the power supply wiring 57b and the ground wiring 57c formed by the uppermost wiring of the second multilayer wiring layer 55 and the copper wiring 40b formed by the uppermost wiring of the first multilayer wiring layer 41 are used. , 40 c are connected via inter-substrate wiring 68. As a result, the power supply wiring 57 b and the ground wiring 57 c are shared between the first semiconductor substrate 31 and the second semiconductor substrate 45.

  In a three-dimensional device in which two semiconductor substrates are bonded and connected by inter-substrate wiring, a wiring layer (in FIG. 27, the first multilayer wiring layer 41 and the second multilayer wiring layer are used to reduce the level difference on the bonding surface of the substrates. The multilayer wiring layer 55) cannot be formed thick. For this reason, in the conventional three-dimensional device, the distance between the wirings becomes short, and the resistance between the wirings cannot be lowered. If power supply wirings and grounding wirings are separately formed on the two semiconductor substrates, a large resistance cannot be obtained. This may cause noise due to enlargement of elements or power supply drop.

  In the solid-state imaging device according to the present embodiment, the power supply wiring 57b and the ground wiring 57c are shared between the first semiconductor substrate 31 and the second semiconductor substrate 45 formed above and below via the inter-substrate wiring 68. By doing so, it is possible to effectively form a low-resistance wiring. Further, by forming a back surface wiring connected to the inter-substrate wiring 68 on the back surface side of the thinned first semiconductor substrate 31, it is possible to straddle elements and different potential wirings.

  Hereinafter, a wiring layout in a stacked chip in which a first semiconductor chip (hereinafter referred to as an upper chip) and a second semiconductor chip (hereinafter referred to as a lower chip) are stacked, and a design method thereof will be described.

  FIG. 28A shows a schematic configuration diagram of the multilayer chip 90 when a part of the power supply circuit 92 in which the power supply wiring 57 b is formed is formed by the back surface wiring 99 in the solid-state imaging device of the present embodiment example. FIG. 28B shows a schematic configuration diagram of the multilayer chip 91 when the power supply circuit 92 in which the power supply wiring 57 b is formed is formed in the second multilayer wiring layer 55 as a comparative example.

  As shown in FIG. 28A, the power supply wiring between the chips is shared between the first semiconductor substrate 31 and the second semiconductor substrate 45 via the inter-substrate wiring 68. The terminals connected to the power supply wiring of the power supply circuit 92 are connected to the mounting board through the power supply wiring 57 b on the uppermost layer of the second multilayer wiring layer 55. Further, a part of the power supply circuit 92 formed by the first multilayer wiring layer 41 is interrupted at a position where the overlapping of the layout can be minimized, and is configured by the back surface wiring 99 through the inter-substrate wiring 68. That is, a part of the power supply circuit 92 (region a surrounded by a broken line) in the configuration of FIG. 28B shown as a comparative example is replaced with a back surface wiring 99 formed on the back surface side of the first semiconductor substrate 31 in this embodiment. Consists of. In this case, the back surface wiring 99 can be formed by the damascene method in the same manner as the connection wiring 68 a formed on the inter-substrate wiring 68.

  In this way, in the example of FIG. 28A, a part of the power supply circuit 92 is moved to the back side of the first semiconductor substrate 31 and is constituted by the back side wiring 99, whereby the wirings can be stacked vertically. Therefore, the area of the power supply circuit 92 can be reduced as compared with the configuration of FIG. 28B.

  FIG. 29A is a block diagram showing the connection from the power supply wiring to the power supply terminal and the connection from the ground wiring to the ground terminal of the multilayer chip 90 in this embodiment. FIG. 29B is a block diagram showing the connection from the power supply wiring to the power supply terminal and the connection from the ground wiring to the ground terminal of the circuit portion in the laminated chip 91 in the comparative example.

  29A and 29B are schematic configuration diagrams of the main part when the laminated chips 90 and 91 in which the upper chip and the lower chip are laminated are viewed from the upper surface. The circuit part 96 and the lower chip formed in the upper chip are shown in FIG. The formed circuit part 97 is typically shown.

  In the comparative example, as shown in FIG. 29B, the power supply wiring 40b and the ground wiring 40c of the circuit unit 96 of the upper chip, and the power supply wiring 57b and the ground wiring 57c of the circuit unit 97 of the lower chip are separately connected to each power supply terminal 95 and It is connected to the ground terminal 94. In this case, it is necessary to route the power supply wirings 40b and 57b and the ground wirings 40c and 57c in both the upper chip and the lower chip.

  In this way, in the design of the laminated chip, in order to operate the upper and lower chips independently, the connection to the input / output terminals such as the power supply wiring or the ground wiring, and the protection circuit for the input / output unit (not shown) Must be completed within each chip. However, in the laminated chip 91 as shown in FIG. 29B, the configuration in which the wiring of the shared potential such as the power supply wiring and the ground wiring and the protection circuit (not shown) are overlapped on both the chips is inferior in layout efficiency and increases the chip cost. Cause

  On the other hand, in the configuration of this embodiment, as shown in FIG. 29A, the power supply wirings 40b and 57b and the ground wirings 40c and 57c in the upper chip and the lower chip are connected to the connection hole 66 and the through-connection hole 65, respectively. They are connected via the formed inter-substrate wiring and back surface wiring 99. Connection to the ground terminal 94 and the power supply terminal 95 is performed by the power supply wiring 57b and the ground wiring 57c of the lower chip. For this reason, in the upper chip, after the power supply wiring 40b and the ground wiring 40c are connected to the inter-substrate wiring 68, it is not necessary to route the wiring. As a result, as compared with the example of FIG. 29B, a surplus space is formed in the region z surrounded by the broken line shown in FIG. 29A, so that a new circuit can be formed in this surplus space. As a result, it is possible to realize an optimal arrangement that makes maximum use of the chip area.

  In the present embodiment example, a part of the circuit is configured by the back surface wiring 99 formed on the back surface side of the first semiconductor substrate 31, but the substrate side where the surplus space is more in the site area of the wiring A common circuit may be formed between the two chips. As a result, the number of wiring layers and the layout area of the multilayer wiring layers can be suppressed.

By the way, when wiring of the same potential such as power supply wiring and ground wiring is originally formed on the same substrate, it can be easily realized by sharing between adjacent circuits and reducing the layout area. However, in a configuration in which two layers of chips are formed on different substrates, the wiring path of the mutual circuit is limited by the inter-substrate wiring, so that it is not easy to share the common potential wiring.
Hereinafter, a design method for realizing the design of the solid-state imaging device according to the present embodiment will be described.

  FIG. 30 shows a design method of the solid-state imaging device according to the present embodiment. FIGS. 31 to 34 show an upper chip (A in FIGS. 31 to 34) and a lower chip (FIGS. 31 to 34) according to the design process. 34B) shows a production process diagram.

  In the solid-state imaging device according to the present embodiment, in order to connect the upper chip 22 and the lower chip 26 to be stacked by inter-substrate wiring, it is important to arrange the inter-substrate wiring 68 at a position where the circuit and wiring are not batted. is there.

  First, the chip size is determined from the total circuit area (step S1). Next, the circuits to be placed in the upper chip 22 and the lower chip 26 are classified (step S2). In this embodiment, as shown in FIGS. 31A and 31B, the pixel region 23 and the control circuit 96 are formed in the upper chip 22, and the logic circuit 97 and the input / output terminal 12 are formed in the lower chip 26. To do.

  Next, the layout of the inter-substrate wiring is determined. The layout of the inter-substrate wiring is such that a large number of signal lines are directly connected between the upper chip 22 and the lower chip 26 (in the solid-state imaging device, a connection position between the pixel and the signal wiring). Then, it is determined from a custom designed area (designed by customer order) (step S2). Thereby, the layout area of the inter-board wiring by the custom design is determined in the area indicated by the area z1 in FIGS. 32A and 32B. As shown in FIGS. 32A and 32B, the circuit surface to be directly connected (that is, the position of the inter-board wiring in the custom design) must be at the same position in the upper chip 22 and the lower chip 26. Rough placement is limited.

  Next, a provisional external size of circuit components to be mounted on the upper chip 22 and the lower chip 26 is defined, a provisional layout is determined, and a gap area in which no circuit is arranged is determined. As a result, an area (interval z2 in FIG. 32A) for inter-substrate wiring other than the custom design is determined (step S4). With respect to the lower chip 26, if wiring for receiving wiring between substrates can be placed, a circuit can be placed immediately below the wiring. However, when the inter-substrate wiring is arranged on the upper chip 22, no circuit can be arranged immediately below and around the upper chip 22. Therefore, the area where the inter-substrate wiring is arranged is mainly limited by the circuit arrangement of the upper chip 22.

  Next, a wiring path (wiring 88 in FIG. 32B) for connection between the input / output terminal 12 and each circuit in the lower chip 26 is obtained by automatic wiring similar to normal circuit design (step S5). Thereby, as shown in FIG. 32B, the input / output terminal 12 and the logic circuit 97 in the lower chip 26 are connected by the wiring 88.

  Next, a wiring having the same potential to be connected between the upper chip 22 and the lower chip 26 is extracted (step S6). As a result, as shown in FIG. 33A, in the upper chip 22, the wiring 89 to be connected to the wiring 88 of the lower chip 26 is laid out. Next, as shown in FIGS. 34A and 34B, the distance between the wiring 89 of the upper chip 22 and the wiring 88 of the lower chip 26 is automatically changed to the backside wiring within the inter-substrate wiring arrangement area determined in step S4. The through-hole connection hole 65 and the connection position of the connection hole 66 are determined at the shortest position including Thereby, the arrangement position of the inter-substrate wiring is determined (step S7). That is, here, the wiring path of the back surface wiring 99 is also determined. Thereby, desired electrodes of the lower chip 26 and the upper chip 22 are connected by the inter-substrate wiring, and the inter-substrate wiring connected to the lower chip 26 and the inter-substrate wiring connected to the upper chip 22 are back surface wiring 99. Connected by.

  The solid-state imaging device designed and manufactured in this way is completed by performing connection verification, physical verification, timing verification, and the like, as in a general flow.

  As described above, in the solid-state imaging device according to the present embodiment, it is necessary to form the inter-substrate wiring at a position where the circuit and the wiring are not batted in order to form the inter-substrate wiring penetrating between the stacked chips. It is necessary to add processes that are not included in the design process.

  Then, according to the design method of the solid-state imaging device of the present embodiment example, the common potential wiring can be formed by connecting the inter-substrate wiring between the upper chip 22 and the lower chip 26, and the back surface. By using the wiring, a circuit formed in the chip can be simplified. As a result, the chip area can be used effectively, and the chip size can be reduced.

  In the present embodiment, the solid-state imaging device has been described as an example. However, the design method of the present embodiment can also be applied to the manufacture of the semiconductor device of the second embodiment.

  In the conventional semiconductor device design of a laminated chip, a circuit is divided into functional blocks, and each is divided into upper and lower chips. On the other hand, in the semiconductor device of the present invention, the pitch between the connection holes and the through-connection holes can be made sufficiently small (for example, up to 1 μm or less). The part can be moved to another substrate. This makes it possible to move a part of the circuit from a board with insufficient wiring layout area to a board with a lot of surplus area, or to use a part of the circuit in common. Layout is possible.

<5. Fourth Embodiment>
[Configuration example of electronic equipment]
The above-described solid-state imaging device of the present invention can be applied to electronic devices such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function.

  FIG. 35 shows a schematic configuration diagram of an electronic apparatus according to the fourth embodiment of the present invention. FIG. 35 shows a camera 200 as an example of the electronic apparatus of the present invention. The camera 200 according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 200 according to the present embodiment includes a solid-state imaging device 203, an optical system 201 that guides incident light to a photoelectric conversion unit that includes a photodiode of the solid-state imaging device 203, and a shutter device 202. Furthermore, the camera 200 includes a drive circuit 205 that drives the solid-state imaging device 203 and a signal processing circuit 204 that processes an output signal of the solid-state imaging device 203.

  As the solid-state imaging device 203, the solid-state imaging device according to the first embodiment described above is applied. The optical system (optical lens) 201 forms image light (incident light) from a subject on the imaging surface of the solid-state imaging device 203. Thereby, signal charges are accumulated in the solid-state imaging device 203 for a certain period. The optical system 201 may be an optical lens system including a plurality of optical lenses. The shutter device 202 controls a light irradiation period and a light shielding period for the solid-state imaging device 203. The drive circuit 205 supplies a drive signal that controls the transfer operation of the solid-state imaging device 203 and the shutter operation of the shutter device 202. Signal transfer of the solid-state imaging device 203 is performed by a drive signal (timing signal) supplied from the drive circuit 205. The signal processing circuit 204 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  According to the electronic apparatus such as the camera 200 according to the fourth embodiment, the solid-state imaging device 203 can be improved in performance and the manufacturing cost can be reduced. For this reason, in this embodiment, an inexpensive and highly reliable electronic device can be provided.

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Pixel, 3 ... Pixel area, 4 ... Vertical drive circuit, 5 ... Column signal processing circuit, 6 ... Horizontal drive circuit, 7 ... Output circuit 8 ... Control circuit 9 ... Vertical signal line 10 ... Horizontal signal line 11 ... Transfer transistor 12 ... Input / output terminal 13 ... Reset transistor 14 ... Amplifying transistor, 15 ... select transistor, 16 ... floating diffusion part, 21 ... MOS type solid-state imaging device, 22 ... first semiconductor chip part, 23 ... pixel region, 24 ..Control area, 25... Logic circuit, 26... Second semiconductor chip portion, 27... MOS type solid-state imaging device, 30... Unit pixel, 31. , 31b ... back surface, 32 ... semiconductor well 33, source / drain regions, 34 ... n-type semiconductor region, 35 ... p-type semiconductor region, 36 ... gate electrode, 38 ... element isolation region, 39 ... interlayer insulation 40, ... Copper wiring, 41 ... First multilayer wiring layer, 42 ... Insulating spacer layer, 43a ... First insulating thin film, 43b ... Second insulating thin film, 44 ... Connection conductor, 45 ... second semiconductor substrate, 46 ... semiconductor well region, 47 ... source / drain region, 48 ... gate electrode, 49 ... interlayer insulating film, 50 ... element Separation region, 53 ... copper wiring, 54 ... connection conductor, 55 ... second multilayer wiring layer, 56 ... barrier metal layer, 57 ... aluminum wiring, 57a ... signal wiring, 57b: power supply wiring, 57c: ground wiring, 58: barrier metal layer, 5 ... Warp correction film, 60 ... Adhesive layer, 61 ... Antireflection film, 62 ... Insulating film, 63 ... Light shielding film, 64 ... Groove, 65 ... Through-connection hole , 66 ... connection hole, 67 ... insulating layer, 68 ... inter-substrate wiring, 68a ... connection wiring, 69 ... waveguide material film, 70 ... waveguide, 71 ... Planarization film, 72 ... Cap film, 73 ... On-chip color filter, 74 ... On-chip lens, 74a ... On-chip lens material, 75 ... Resist film, 76 ... Resist film , 77... Through opening, 78... Electrode pad portion, 79... Bonding wire, 81... Solid imaging device, 81 a. Laminated body

Claims (20)

A first semiconductor including a first wiring layer formed on a side opposite to a light incident surface, in which a pixel array including a photoelectric conversion unit that generates a signal charge according to the amount of received light and a plurality of pixel transistors is formed. A substrate,
A second semiconductor substrate formed with a second wiring layer and bonded to the first semiconductor substrate;
A through-connection hole provided through the first semiconductor substrate and reaching the second wiring layer;
A groove portion and a light shielding film groove portion provided on the light incident surface side in the first semiconductor substrate;
A connection hole provided on the light incident surface side in the first semiconductor substrate;
A region including the through-hole, the connection hole, and the groove; and a conductive material formed in the light-shielding film groove;
With
The groove is formed in the through-connection hole and a region in contact with the connection hole, and the conductive material in the groove is formed integrally with the conductive material in the through-connection hole and in the connection hole,
A light shielding film is formed of the conductive material in the groove for the light shielding film,
The conductive material in the groove and the conductive material in the light shielding film groove are formed on the same plane.
The solid-state imaging device, wherein the conductive material electrically connects the first wiring layer and the second wiring layer. The solid-state imaging device according to claim 1,
The conductive material is a solid-state imaging device containing tungsten or copper. The solid-state imaging device according to claim 1 or 2,
A solid-state imaging device in which an insulating layer is formed on a side wall of the through-connection hole. The solid-state imaging device according to any one of claims 1 to 3,
The through-connection hole is a solid-state imaging device in contact with the barrier metal layer of the second wiring layer. The solid-state imaging device according to any one of claims 1 to 4,
A solid-state imaging device in which wiring having a common potential is connected to the first wiring layer and the second wiring layer by the conductive material. The solid-state imaging device according to claim 5,
A first semiconductor integrated circuit provided on the first semiconductor substrate by a back surface wiring formed on the light incident surface side of the first semiconductor substrate and electrically connected to the conductive material; A solid-state imaging device in which a part of a circuit used in common with a second semiconductor integrated circuit provided on a semiconductor substrate is formed. The solid-state imaging device according to claim 1,
The photoelectric conversion unit is a solid-state imaging device including a plurality of photodiodes. The solid-state imaging device according to claim 1,
The through-connection hole and the groove are solid-state imaging devices arranged in a pixel region. A solid-state imaging device according to any one of claims 1 to 8,
The solid-state imaging device in which the through-hole and the groove are arranged outside the pixel region. The solid-state imaging device according to claim 8,
A solid-state imaging device including a plurality of the through-connection holes and the groove portions in the pixel region. The solid-state imaging device according to claim 7,
The plurality of photodiodes are solid-state imaging devices that share a floating diffusion. The solid-state imaging device according to any one of claims 1 to 11,
The second semiconductor substrate is a solid-state imaging device including a signal processing circuit or a control circuit. A solid-state imaging device according to any one of claims 1 to 12,
A solid-state imaging device in which a power supply terminal and a ground terminal are formed at opposite corners of the rectangular chip. The solid-state imaging device according to claim 1,
A solid-state imaging device in which the pixel transistor includes a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor. The solid-state imaging device according to claim 1,
A solid-state imaging device containing copper in the first wiring layer. The solid-state imaging device according to any one of claims 1 to 15,
A solid-state imaging device including copper or aluminum in the second wiring layer. The solid-state imaging device according to any one of claims 1 to 16,
The diameter of the opening part of the said through-connection hole is a solid-state imaging device formed larger than the diameter of the opening part of the said connection hole. The solid-state imaging device according to any one of claims 1 to 16,
The depth of the through-connection hole is a solid-state imaging device formed deeper than the depth of the connection hole. A solid-state imaging device according to any one of claims 1 to 18,
A solid-state imaging device in which an insulating spacer layer for separating a desired region is formed in the first semiconductor substrate. A solid-state imaging device according to any one of claims 1 to 19,
An optical system for guiding incident light to the photoelectric conversion unit;
An electronic apparatus comprising: a signal processing circuit that processes an output signal of the solid-state imaging device.

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