JP7001120B2 - Solid-state image sensor and electronic equipment - Google Patents

Description

The present invention relates to a solid-state image sensor and an electronic device including the solid-state image sensor.

As a solid-state image sensor, an amplified solid-state image sensor represented by a MOS type image sensor such as CMOS (Complementary Metal Oxide Semiconductor) is known. Further, a charge transfer type solid-state image sensor represented by a CCD (Charge Coupled Device) image sensor is known. These solid-state image sensors are widely used in digital still cameras, digital video cameras, and the like. In recent years, as a solid-state imaging device mounted on a mobile device such as a camera-equipped mobile phone or a PDA (Personal Digital Assistant), a MOS type image sensor is often used from the viewpoint of low power supply voltage and power consumption.

The MOS type solid-state image sensor is formed of a photodiode whose unit pixel is a photoelectric conversion unit and a plurality of pixel transistors, and a pixel array (pixel area) in which the plurality of unit pixels are arranged in a two-dimensional array and a periphery. It has a circuit area and is configured. The plurality of pixel transistors are formed of MOS transistors, and are composed of a transfer transistor, a reset transistor, three transistors of amplification and a transistor, or four transistors including a selection transistor.

Conventionally, in such a MOS type solid-state image sensor, one semiconductor chip in which a pixel region in which a plurality of pixels are arranged is electrically connected and a semiconductor chip in which a logic circuit for performing signal processing is formed. Various solid-state image sensors configured as devices have been proposed. For example, Patent Document 1 discloses a semiconductor module in which a back-illuminated image sensor chip having a micro pad for each pixel cell and a signal processing chip having a signal processing circuit formed and having a micro pad are connected by a micro bump. Has been done.

In Patent Document 2, a sensor chip, which is a back-illuminated MOS solid-state image sensor provided with an image pickup pixel portion, and a signal processing chip provided with a peripheral circuit for signal processing are mounted on an interposer (intermediate substrate). The device is disclosed. Patent Document 3 includes an image sensor chip, a thin circuit board, and a logic circuit chip that performs signal processing. A configuration is disclosed in which the thin film circuit board and the logic circuit board are electrically connected, and the thin film circuit board is electrically connected from the back surface of the image sensor chip via a through-hole via.

Further, Patent Document 4 discloses a solid-state image pickup device in which a through electrode is provided on a solid-state image sensor supported by a transparent substrate, and the solid-state image sensor is electrically connected to a flexible circuit board via the through electrode. Further, Patent Document 5 discloses a configuration in which a back-illuminated solid-state image sensor is provided with an electrode that penetrates a support substrate.

As shown in Patent Documents 1 to 3, various techniques for mounting an image sensor chip and a different type of circuit chip such as a logic circuit in a mixed manner have been proposed. In the conventional technique, the functional chips are almost completed, and through connection holes are formed to form the chips on one chip in a state where interconnection between the vertically stacked chips is possible. Is a feature.

Japanese Unexamined Patent Publication No. 2006-49361 JP-A-2007-13089 Japanese Unexamined Patent Publication No. 2008-13603 Japanese Patent No. 4000507 Japanese Patent Application Laid-Open No. 2003-31785

As seen in the conventional solid-state image sensor described above, it has been known as an idea to connect different types of chips laminated by a connecting conductor penetrating a substrate to form a semiconductor device. However, it is necessary to make a connection hole while ensuring insulation in a deep substrate, and it is difficult to put it into practical use due to the cost economy of the manufacturing process required for processing the connection hole and embedding the connection conductor.

On the other hand, in order to form a small contact hole of, for example, about 1 μm, it is necessary to make the upper tip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning the thickness and an increase in cost are caused. Moreover, in order to fill the connection hole with a high aspect ratio with the connection conductor, it is inevitably required to use a CVD film having good coating properties such as tungsten (W) as the connection conductor, and the connection conductor material is restricted.

In order to have economic efficiency that can be easily applied in mass production, the aspect ratio of this connection hole is dramatically reduced to make it easier to form, and it is processed in the conventional wafer manufacturing process without using special connection hole processing. It is desirable to be able to select the technology that can be used. At this time, the contact hole connected to the upper chip and the contact hole that penetrates the upper chip and reaches the lower chip have different depths, but it is required that they can be formed by the same etching process or metal embedding process as much as possible. ing.

Further, in a solid-state image sensor or the like, it is desired that an image region and a logic circuit for performing signal processing are formed so as to sufficiently exhibit their respective performances, and high performance is achieved.
Not only solid-state image sensors but also semiconductor devices having other semiconductor integrated circuits are desired to be formed so that the performance of each semiconductor integrated circuit can be fully exhibited and the performance can be improved.

However, if the upper and lower chips are designed to incorporate the necessary functions, the circuit areas of the parts having the common functions overlap, so that the chip size becomes large and it becomes difficult to reduce the cost. Therefore, at least in order to reduce costs, it is necessary to design the upper and lower chips so that the areas of the parts having the same function can be used in common as much as possible.

In view of the above points, the present invention provides a solid-state image pickup device and a solid-state image pickup device in which the performance of each of the semiconductor wafers to be laminated is fully exhibited to improve the performance, and the mass productivity and cost are reduced. It provides electronic devices equipped with it.

In the solid-state imaging device according to the present invention, a pixel array is formed, a first semiconductor wafer including a first wiring layer provided on the side opposite to the light incident surface, and a second wiring layer are formed, and a second wiring layer is formed. A second semiconductor wafer bonded to the first semiconductor wafer, a through connection hole provided through the first semiconductor wafer and reaching the second wiring layer, and a light incident surface side in the first semiconductor wafer. A groove portion provided in the above, and a conductive material formed in a region including a through connection hole and the groove portion are provided, and the conductive material electrically connects the first wiring layer and the second wiring layer.
The electronic device according to the present invention includes the solid-state image pickup device according to the present invention.

According to the present invention, a plurality of semiconductor wafers on which circuits capable of fully exhibiting their respective performances are formed are laminated by the optimum process technology, so that they are excellent in mass productivity, low cost and high cost. A performance solid-state imaging device can be obtained.

It is a schematic block diagram which shows an example of the MOS solid-state image sensor applied to this invention. A It is a schematic diagram of a conventional solid-state image sensor. B, C It is a schematic diagram of the solid-state image pickup apparatus which concerns on embodiment of this invention. It is a figure which shows an example of the circuit of the pixel structure of the MOS solid-state image sensor applied to this invention. It is a schematic block diagram of the main part which shows the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (the 1) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (the 2) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (3) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (the 4) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (No. 5) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (No. 6) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (7) which shows the example of the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process drawing (the 8) which shows the solid-state image sensor and the manufacturing method thereof which concerns on 1st Embodiment. It is a manufacturing process diagram (9) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (No. 10) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (11) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (12) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (13) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (14) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a manufacturing process diagram (15) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment. It is a schematic cross-sectional block diagram of the solid-state image sensor which concerns on 2nd Embodiment of this invention. It is a manufacturing process drawing (the 1) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a manufacturing process drawing (the 2) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a manufacturing process drawing (the 3) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a manufacturing process drawing (the 4th) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a manufacturing process drawing (the 5) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a manufacturing process diagram (No. 6) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is schematic cross-sectional block diagram of the main part of the solid-state image sensor which concerns on 3rd Embodiment of this invention. A and B An example in which the back surface wiring is used on the back surface side of the first semiconductor substrate and an example in which the back surface wiring is not used. A and B are a configuration example of a plane layout when wiring of a common potential is connected between the stacked chips, and a configuration example of a plane layout when wiring of a common potential is not connected. It is a flow which shows the design method of the solid-state image sensor of this invention. A, B It is a manufacturing process diagram of the upper chip and the lower chip according to the design method of this invention. A, B It is a manufacturing process diagram of the upper chip and the lower chip according to the design method of this invention. A, B It is a manufacturing process diagram of the upper chip and the lower chip according to the design method of this invention. A, B It is a manufacturing process diagram of the upper chip and the lower chip according to the design method of this invention. It is a schematic block diagram which shows the electronic device which concerns on 4th Embodiment of this invention.

Hereinafter, embodiments for carrying out the invention (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. Schematic configuration example of MOS type solid-state image sensor 2. 1st Embodiment (Example of configuration of back-illuminated solid-state image sensor and example of manufacturing method thereof)
3. 3. Second Embodiment (Example of configuration of semiconductor device and example of manufacturing method thereof)
4. Third Embodiment (configuration example of a solid-state image sensor and its design method)
5. Fourth Embodiment (constituent example of an electronic device)

<1. Schematic configuration example of MOS type solid-state image sensor>
FIG. 1 shows a schematic configuration of a MOS type solid-state image sensor applied to the semiconductor device of the present invention. This MOS type solid-state image sensor is applied to the solid-state image sensor of each embodiment. The solid-state image sensor 1 of this example includes a pixel region (so-called pixel array) 3 in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate (for example, a silicon substrate) (not shown) and peripheral circuits. It is composed of a part. The pixel 2 includes, for example, a photodiode that serves as a photoelectric conversion unit, and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be composed of, for example, three transistors, a transfer transistor, a reset transistor, and an amplification transistor. In addition, it is possible to add a selection transistor and configure it with four transistors. The equivalent circuit of a unit pixel will be described later. The pixel 2 can be configured as one unit pixel, or can have a shared pixel structure in which a transistor is shared by a plurality of pixels. This shared pixel structure is a structure in which a plurality of photodiodes share a floating diffusion constituting a transfer transistor and a transistor other than the transfer transistor.

The peripheral circuit unit includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

The control circuit 8 receives an input clock and data instructing an operation mode and the like, and outputs data such as internal information of the solid-state image sensor. That is, the control circuit 8 generates a clock signal or a control signal that serves as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. do. Then, these signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

The vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixel in row units. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 in a row-by-row manner in the vertical direction, and passes through the vertical signal line 9 to be a photoelectric conversion unit of each pixel 2, for example, a photodiode according to the amount of light received. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

The column signal processing circuit 5 is arranged for each column of the pixel 2, for example, and performs signal processing such as noise removal for each pixel column of the signal output from the pixel 2 for one row. That is, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing the fixed pattern noise peculiar to the pixel 2 and signal amplification and AD conversion. A horizontal selection switch (not shown) is provided in the output stage of the column signal processing circuit 5 so as to be connected to the horizontal signal line 10.

The horizontal drive circuit 6 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, each of the column signal processing circuits 5 is sequentially selected, and a pixel signal is output from each of the column signal processing circuits 5 as a horizontal signal line. Output to 10.

The output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals. For example, there are cases where only buffering is performed, black level adjustment, column variation correction, various digital signal processing, and the like are performed. The input / output terminal 12 exchanges signals with the outside.

Next, the structure of the MOS type solid-state image sensor according to the present embodiment will be described. FIG. 2A is a schematic configuration diagram showing the structure of a conventional MOS type solid-state image sensor, and FIGS. 2B and 2C are schematic configuration diagrams showing the structure of the MOS type solid-state image sensor according to the present embodiment.

As shown in FIG. 2A, the conventional MOS type solid-state image sensor 151 is configured by mounting a pixel region 153, a control circuit 154, and a logic circuit 155 for signal processing in one semiconductor chip 152. To. Normally, the image sensor 156 is composed of the pixel area 153 and the control circuit 154.

On the other hand, in the MOS type solid-state image sensor 21 of the present embodiment, as shown in FIG. 2B, the pixel region 23 and the control region 24 are mounted on the first semiconductor chip portion 22, and the second semiconductor chip portion is provided. A logic circuit 25 including a signal processing circuit for signal processing is mounted on the 26. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to form a MOS type solid-state image sensor 21 as one semiconductor chip.

In the MOS type solid-state image sensor 27 according to another embodiment of the present invention, as shown in FIG. 2C, the pixel region 23 is mounted on the first semiconductor chip unit 22, and the control region is on the second semiconductor chip unit 26. 24, a logic circuit 25 including a signal processing circuit is mounted. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to form a MOS type solid-state image sensor 27 as one semiconductor chip.

FIG. 3 is a circuit diagram showing an example of the circuit configuration of the unit pixel 2. The unit pixel 2 according to this circuit example includes a photoelectric conversion unit, for example, a photodiode PD and four pixel transistors. The four pixel transistors are, for example, a transfer transistor 11, a reset transistor 13, an amplification transistor 14, and a selection transistor 15. For these pixel transistors, for example, n-channel MOS transistors are used.

The transfer transistor 11 is connected between the cathode of the photodiode PD and the floating diffusion unit 16. The signal charge (here, an electron) that has been photoelectrically converted by the photodiode PD and accumulated here is transferred to the floating diffusion unit 16 by applying a transfer pulse φTRG to the gate.

The reset transistor 13 has a drain connected to the power supply VDD and a source connected to the floating diffusion unit 16. Then, prior to the transfer of the signal charge from the photodiode PD to the floating diffusion unit 16, the potential of the floating diffusion unit 16 is reset by applying a reset pulse φRST to the gate.

The drain of the selection transistor 15 is connected to, for example, the power supply VDD, and the source of the selection transistor 15 is connected to the drain of the amplification transistor 14. Then, when the selection pulse φSEL is applied to the gate of the selection transistor 15, it is turned on, and the pixel 2 can be selected by supplying the power supply VDD to the amplification transistor 14. The selection transistor 15 may be configured to be connected between the source of the amplification transistor 14 and the vertical signal line 9.

The amplification transistor 14 has a source follower configuration in which a gate is connected to the floating diffusion portion 16, a drain is connected to the source of the selection transistor 15, and a source is connected to the vertical signal line 9. The amplification transistor 14 outputs the potential of the floating diffusion unit 16 after being reset by the reset transistor 13 as a reset level to the vertical signal line 9. Further, the amplification transistor 14 outputs the potential of the floating diffusion unit 16 after the signal charge is transferred by the transfer transistor 11 to the vertical signal line 9 as a signal level.

In the solid-state image sensor 1 of the present embodiment, for example, elements such as a photodiode and a plurality of MOS transistors are formed on the first semiconductor chip portion 22 of FIG. 2B or FIG. 2C. Further, the transfer pulse, the reset pulse, the selection pulse, and the power supply voltage are supplied from the control region 24 of FIG. 2B or FIG. 2C. Further, the element after the vertical signal line 9 connected to the drain of the selection transistor is configured in the logic circuit 25 of FIG. 2B or FIG. 2C, and is formed in the second semiconductor chip portion 26.

The MOS type solid-state image sensor according to the above-described embodiment has a structure in which different types of semiconductor chips are laminated, and is characterized by a manufacturing method thereof and a configuration obtained based on the manufacturing method, as will be described later. have.
In the embodiment described below, the solid-state image sensor of the present invention and a method for manufacturing the same will be described.

<2. First Embodiment>
[Example of configuration of solid-state image sensor and example of manufacturing method thereof]
A back-illuminated MOS-type solid-state image sensor will be described with reference to FIGS. 4 to 19 as a semiconductor device according to the first embodiment of the present invention together with a manufacturing method thereof.

FIG. 4 is a schematic cross-sectional configuration diagram (completed view) including the electrode pad portion 78 of the solid-state image sensor 81 of the present embodiment. The solid-state image sensor 81 of the present embodiment has a first semiconductor chip unit 22 including a pixel array (hereinafter referred to as a pixel region) 23 and a control region 24, and a second semiconductor chip unit on which a logic circuit 25 is mounted. 26 are stacked one above the other in a state of being electrically connected.
A method of manufacturing the solid-state image sensor 81 of the present embodiment will be described with reference to FIGS. 5 to 19.

In the first embodiment, first, as shown in FIG. 5, an image sensor in a semi-finished state is formed in a region to be a chip portion of a first semiconductor wafer (hereinafter referred to as a first semiconductor substrate) 31. That is, the pixel area 23 and the control area 24 are formed. That is, a photodiode (PD) to be a photoelectric conversion part of each pixel is formed in a region to be a chip part of the first semiconductor substrate 31 made of a silicon substrate, and a source / source of each pixel transistor is formed in the semiconductor well region 32. The drain region 33 is formed. The semiconductor well region 32 is formed by introducing a first conductive type, for example, p-type impurity, and the source / drain region 33 is formed by introducing a second conductive type, for example, n-type impurity. The photodiode (PD) and the source / drain region 33 of each pixel transistor are formed by ion implantation from the substrate surface.

The photodiode (PD) is formed to have an n-type semiconductor region 34 and a p-type semiconductor region 35 on the surface side of the substrate. A gate electrode 36 is formed on the surface of the substrate constituting the pixel via a gate insulating film, and pixel transistors Tr1 and Tr2 are formed by a source / drain region 33 paired with the gate electrode 36. In FIG. 5, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. The pixel transistor Tr1 adjacent to the photodiode (PD) corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD). Each unit pixel 30 is separated by the element separation region 38.

On the other hand, on the control region 24 side, a MOS transistor constituting a control circuit is formed on the first semiconductor substrate 31. FIG. 4 shows MOS transistors constituting the control region 24, represented by MOS transistors Tr3 and Tr4. Each MOS transistor Tr3 and Tr4 is formed by an n-type source / drain region 33 and a gate electrode 36 formed via a gate insulating film.

Next, a first layer of the interlayer insulating film 39 is formed on the surface of the first semiconductor substrate 31, a contact hole is formed in the interlayer insulating film 39, and a connecting conductor 44 to be connected to a required transistor is formed. .. When forming the connecting conductors 44 having different heights, the first insulating thin film 43a is formed of, for example, a silicon oxide film on the entire surface including the upper surface of the transistor, and the second insulating thin film 43b, which serves as an etching stopper, is formed of, for example, a silicon nitride film. And stack. The first interlayer insulating film 39 is formed on the second insulating thin film 43b. As the interlayer insulating film 39 of the first layer, for example, a P-SiO film (plasma oxide film) is formed at 10 to 150 nm, and then an NSG (non-doped silicate glass) film or a PSG film (phosphoric acid glass) is formed at 50 nm to 1000 nm. Formed with. Then, it can be formed by forming a dTEOS film at 100 to 1000 nm and then forming a P-SiH4 film (plasma oxide film) at 50 to 200 nm.

After that, contact holes having different depths are selectively formed in the interlayer insulating film 39 of the first layer up to the second insulating thin film 43b serving as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched in each part so as to be continuous with each contact hole to form a contact hole. Then, the connecting conductor 44 is embedded in each contact hole.

Further, after forming the second insulating thin film 43b, an insulating spacer layer 42 for separating a desired region in the semiconductor well region 32 of the first semiconductor substrate 31 is formed. After forming the second insulating thin film 43b, the insulating spacer layer 42 is formed by opening a desired position of the first semiconductor substrate 31 from the surface side and embedding an insulating material. The insulating spacer layer 42 is formed in a region surrounding the inter-board wiring 68 in FIG.

Next, a plurality of layers, in this example, three layers of copper wiring 40 are formed via the interlayer insulating film 39 so as to be connected to each connection conductor 44, and the first multilayer wiring layer 41 is formed. Normally, each copper wiring 40 is covered with a barrier metal layer (not shown) in order to prevent Cu diffusion. The barrier metal layer can be formed, for example, by forming a SiN film or a SiC film at 10 to 150 nm. Further, the interlayer insulating film 39 from the second layer can be formed by forming a dTEOS film (a silicon oxide film formed by a plasma CVD (Chemical Vapor Deposition) method) at 100 to 1000 nm. The first multilayer wiring layer 41 is formed by alternately forming the interlayer insulating film 39 and the copper wiring 40 formed via the barrier metal layer. In this embodiment, the first multilayer wiring layer 41 is formed of copper wiring 40, but metal wiring made of other metal materials is also possible.

In the steps so far, the first semiconductor substrate 31 having the first multilayer wiring layer 41 on the upper part and having the pixel region 23 and the control region 24 in the semi-finished state is formed.

On the other hand, as shown in FIG. 6, for example, a logic circuit 25 including a signal processing circuit for processing a signal in a semi-finished product state is provided in a region to be a chip portion of a second semiconductor substrate (semiconductor wafer) 45 made of silicon. Form. That is, a plurality of MOS transistors constituting the logic circuit 25 are formed in the p-type semiconductor well region 46 on the surface side of the second semiconductor substrate 45 so as to be separated by the element separation region 50. Here, a plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, and Tr8. Each MOS transistor Tr6, Tr7, and Tr8 is formed to have a pair of n-type source / drain regions 47 and a gate electrode 48 formed via a gate insulating film. The logic circuit 25 can be composed of CMOS transistors.

Next, a first layer of the interlayer insulating film 49 is formed on the surface of the second semiconductor substrate 45, and then a contact hole is formed in the interlayer insulating film 49 to form a connecting conductor 54 to be connected to a required transistor. .. When forming the connecting conductors 54 having different heights, the first insulating thin film 43a, for example, a silicon oxide film and the second insulating thin film 43b, which serves as an etching stopper, for example, a silicon nitride film are formed on the entire surface including the upper surface of the transistor, as described above. Laminate. The first interlayer insulating film 49 is formed on the second insulating thin film 43b. Then, contact holes having different depths are selectively formed in the interlayer insulating film 39 of the first layer up to the second insulating thin film 43b which serves as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched in each part so as to be continuous with each contact hole to form a contact hole. Then, the connecting conductor 54 is embedded in each contact hole.

After that, the second multilayer wiring layer 55 is formed by repeating the formation of the interlayer insulating film 49 and the formation of the plurality of layers of metal wiring. In the present embodiment, after forming the three-layer copper wiring 53 in the same process as the step of forming the first multilayer wiring layer 41 formed on the first semiconductor substrate 31, the aluminum wiring is on the uppermost layer. Take as an example of forming 57. To form the aluminum wiring 57, first, an interlayer insulating film 49 is formed on the upper portion of the copper wiring 53 in the uppermost layer, and then the interlayer insulating film 49 is etched and removed so that a desired position on the upper portion of the copper wiring 53 in the uppermost layer is exposed. , Form a contact hole. Then, in the region including the inside of the contact hole, a laminated film made of TiN (lower layer) / Ti (upper layer) serving as the barrier metal layer 56 is 5 to 10 nm, or a laminated film made of TaN (lower layer) / Ta (upper layer) is 10 to 10 to A film is formed at 100 nm. Then, the contact hole is covered to form an aluminum film at 500 to 2000 nm, and then the aluminum wiring 57 is formed by patterning it into a desired shape. Further, a barrier metal layer 58, which is required in a later process, is formed on the upper portion of the aluminum wiring 57. The barrier metal layer 58 can also have the same configuration as the barrier metal layer 56 formed on the lower layer of the aluminum wiring 57.

Subsequently, the aluminum wiring 57 having the barrier metal layer 58 formed on the upper portion is coated to form an interlayer insulating film 49. For the interlayer insulating film 49 on the upper part of the aluminum wiring 57, for example, an HDP film (high-density plasma oxide film) or a P-SiO film (plasma oxide film) is formed at 500 to 2000 nm, and then a P-SiO film is further formed on the film. It can be formed by forming a film with a thickness of 100 to 2000 nm. As a result, the second multilayer wiring layer 55 composed of the three layers of copper wiring 53 formed via the interlayer insulating film 49 and the aluminum wiring 57 formed in the uppermost layer is formed.

Then, a warp correction film 59 for reducing warpage when the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other is formed on the upper portion of the second multilayer wiring layer 55. The warp correction film 59 can be formed, for example, by forming a P—SiN film or a P—SiON film (plasma nitrogen oxide film) at 100 to 2000 nm.

In the steps so far, the second semiconductor substrate 45 having the second multilayer wiring layer 55 on the upper part and forming the logic circuit in the semi-finished state is formed.

Next, as shown in FIG. 7, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other so that the first multilayer wiring layer 41 and the second multilayer wiring layer 55 face each other. The bonding is performed with, for example, an adhesive. When bonding with an adhesive, an adhesive layer 60 is formed on one side of the bonding surface of the first semiconductor substrate 31 or the second semiconductor substrate 45, and the adhesive layer 60 is laminated via the adhesive layer 60. Join the two. In the present embodiment, the first semiconductor substrate 31 having the pixel region configured is arranged in the upper layer, and the second semiconductor substrate 45 is arranged in the lower layer and bonded.

Further, in the present embodiment, the first multilayer wiring layer 41 on the upper part of the first semiconductor substrate 31 and the second multilayer wiring layer 55 on the upper part of the second semiconductor substrate 45 are bonded to each other via the adhesive layer 60. Although it is used as an example, it may be used as an example of bonding by plasma bonding. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55, respectively. do. The bonding surfaces on which this film is formed are plasma-treated and superposed, and then annealed to bond the two. The bonding process is preferably performed by a low temperature process of 400 ° C. or lower, which does not affect wiring or the like.

Then, the first semiconductor substrate 31 having the multilayer wiring layer on the upper portion and the second semiconductor substrate 45 are laminated and laminated to form a laminated body 81a composed of two different types of substrates.

Next, as shown in FIG. 8, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface side of the first semiconductor substrate 31. This thinning is performed so that the photodiode (PD) faces. As the first semiconductor substrate 31, for example, by using a semiconductor substrate formed by forming a p-type high-concentration impurity layer as an etching stopper layer (not shown), the substrate is etched and removed to the etching stopper layer to make it flat and thin. Can be etched. After thinning, a p-type semiconductor layer (not shown) for suppressing dark current is formed on the back surface of the photodiode (PD). The thickness of the first semiconductor substrate 31 is, for example, about 600 μm, but the thickness is reduced to, for example, about 3 to 5 μm.

Conventionally, such thinning has been performed by laminating a separately prepared support substrate to the side of the first multilayer wiring layer 41 formed on the first semiconductor substrate 31. However, in the present embodiment, the second semiconductor substrate 45 on which the logic circuit 25 is formed is also used as the support substrate, and the thickness of the first semiconductor substrate 31 is thinned. The back surface of the first semiconductor substrate 31 is a light incident surface when configured as a back-illuminated solid-state image sensor.

Next, as shown in FIG. 9, the antireflection film 61 is formed on the back surface of the first semiconductor substrate 31. The antireflection film 61 can add the effect of suppressing dark current by forming, for example, TaO2 or HfO2 at 5 to 100 nm and performing a necessary heat treatment. Then, the insulating film 62 is formed by forming a plasma SiO film on the antireflection film 61 to a thickness of 100 to 1500 nm.

Next, as shown in FIG. 10, a groove 64 is formed in a desired region inside the insulating spacer layer 42, and a light-shielding film groove 82 is formed in a light-shielding region that requires light-shielding. The groove portion 64 and the light-shielding film groove portion 82 are formed by forming an opening by etching from the upper surface of the insulating film 62 formed on the back surface side of the first semiconductor substrate 31, and do not reach, for example, the first semiconductor substrate 31. Form to depth.

Next, as shown in FIG. 11, the copper wiring in the lowermost layer (uppermost in FIG. 11) of the first multilayer wiring layer 41 from the desired bottom region of the groove 64 formed inside the insulating spacer layer 42. It is opened to the depth just before reaching 40 to form the connection hole 66.

Similarly, a through connection hole 65 penetrating the bonding surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55 from a desired bottom region of the groove portion 64 formed inside the insulating spacer layer 42. Form. The through connection hole 65 is formed by opening to a depth immediately before reaching the aluminum wiring 57 of the uppermost layer of the second multilayer wiring layer 55 formed on the upper portion of the second semiconductor substrate 45. At this time, the diameter of the through connection hole 65 is formed to be about 1.5 to 10 times larger than the diameter of the connection hole 66, and more preferably about 3 to 4 times larger.

When the diameter of the through connection hole 65 is smaller than 1.5 times that of the connection hole 66, the aspect ratio of the through connection hole 65 becomes large, and voids are generated when the conductive material is embedded in the hole in a later step. There is a risk of Further, when the diameter of the through connection hole 65 is larger than 10 times the diameter of the connection hole 66, the area occupied by the through connection hole 65 becomes large, and there is a problem that the device cannot be miniaturized. Therefore, by increasing the diameter of the through connection hole 65 to about 1.5 to 10 times the diameter of the connection hole 66, it is possible to obtain a hole having an optimum aspect ratio for embedding a conductive material and not increasing the layout space. can.

Since the connection hole 66 and the through connection hole 65 are formed after the first semiconductor substrate 31 is thinned (step in FIG. 8), the aspect ratio is reduced and the connection hole 65 can be formed as fine holes. Further, the connection hole 66 is opened until just before reaching the lowest layer of the first multilayer wiring layer 41 above the first semiconductor substrate 31, that is, the copper wiring 40 on the side closest to the first semiconductor substrate 31. Therefore, the opening depth becomes shallower, which is advantageous for forming micropores.

Next, an insulating layer 67 made of, for example, a SiO2 film is formed in a region including the side wall and the bottom of the connection hole 66 and the through connection hole 65, and then etched back. As a result, as shown in FIG. 12, the insulating layer 67 is left only on the side walls of the connection hole 66 and the through connection hole 65. After that, the bottoms of the connection hole 66 and the through connection hole 65 are further etched and removed. As a result, in the connection hole 66, the copper wiring 40 in the lowermost layer of the first multilayer wiring layer 41 is used, and in the through connection hole 65, the aluminum wiring 57 in the uppermost layer of the second multilayer wiring layer 55 (strictly speaking). The barrier metal layer 58) above the aluminum wiring is exposed.

As a result, the connection hole 66 reaches the copper wiring 40 of the first multilayer wiring layer 41. Further, the through connection hole 65 penetrates the bonded surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55, and reaches the aluminum wiring 57 formed in the second multilayer wiring layer 55.

At this point, the process of manufacturing the pixel array has not yet undergone the on-chip color filter and on-chip lens processing processes, and is incomplete. At the same time, the connection hole 66 formed on the copper wiring 40 and the through connection hole 65 formed on the aluminum wiring 57 can be processed and formed by extending the conventional wafer process. On the other hand, even in the logic circuit 25, the process up to the metal wiring of the uppermost layer, which is optimal as a circuit technology, is not completed. In this way, since different types of substrates, which are semi-finished products, are bonded together, it is possible to reduce the manufacturing cost as compared with the case where different types of substrates, which are finished products, are bonded together.

After that, as shown in FIG. 13, a conductive material such as copper is formed in the region including the groove portion 64, the groove portion for light-shielding film 82, the connection hole 66, and the through connection hole 65, and a conductive material such as copper is formed by a CMP (Chemical Mechanical Polising) method. Polish the surface. As a result, only the conductive material of the groove portion 64, the groove portion for the light-shielding film 82, the connection hole 66, and the through connection hole 65 remains. As a result, the inter-board wiring 68 is formed in the region inside the insulating spacer layer 42, and the light-shielding film 63 is formed in the light-shielding region. In the present embodiment, the inter-board wiring 68 formed in the connection hole 66 and the inter-board wiring 68 formed in the through connection hole 65 are electrically connected by the connection wiring 68a made of damascene wiring formed in the groove portion 64. Is connected. The light-shielding film 63 is also formed by the damascene method. Then, the copper wiring 40 and the second multilayer wiring layer formed in the first multilayer wiring layer 41 are formed by embedding the groove portion 64, the groove portion 82 for the light-shielding film, the connection hole 66, and the through connection hole 65 with the conductive material. The aluminum wiring 57 formed in 55 is electrically connected.

At this time, since the barrier metal layer 58 is formed on the upper portion of the aluminum wiring 57 formed on the second multilayer wiring layer 55 on the second semiconductor substrate 45, the case where the inter-board wiring 68 is made of copper. However, the diffusion of copper is prevented. Further, an insulating layer 67 is formed on the side wall penetrating the first semiconductor substrate 31 in the holes of the connection hole 66 and the through connection hole 65. Therefore, the inter-board wiring 68 and the first semiconductor substrate 31 are electrically separated and are not connected. Further, in the present embodiment, the inter-board wiring 68 is formed in the region of the insulating spacer layer 42 formed on the first semiconductor substrate 31, so that the inter-board wiring 68 and the first semiconductor are also formed by this. It is prevented that the substrate 31 is electrically connected.

In the step of forming the inter-board wiring 68 of the present embodiment, a damascene method is used in which the groove portion 64, the groove portion 82 for a light-shielding film, the connection hole 66, and the through connection hole 65 are formed in three stages and copper is embedded. It is not limited to this. Between the boards to which the copper wiring 40 of the first multilayer wiring layer 41 on the upper part of the first semiconductor substrate 31 and the aluminum wiring 57 of the second multilayer wiring layer 55 on the upper part of the second semiconductor substrate 45 are electrically connected. Various changes can be made as long as the wiring 68 is formed.

For example, the inter-board wiring 68 can be formed by a CVD method, a sputtering method, or the like, and can be formed by ordinary lithography and dry etching, but the deterioration of sensitivity becomes difficult to tolerate by stacking the wiring layers. Therefore, it is desirable to apply a damascene wiring structure with less additional insulating film.

Further, in the present embodiment, the light-shielding film groove portion 82 for forming the light-shielding film 63 is processed at the same time as the groove portion 64 for forming the inter-board wiring 68, but the groove portion 64, the connection hole 66, It may be formed after the formation of the through connection hole 65 and the insulating spacer layer 42. Also in this case, the light-shielding film groove portion 82 is formed in the same layer as the groove portion 64, and the conductive material is embedded in the light-shielding film groove portion 82 by conducting the conductive material in the groove portion 64, the connection hole 66, and the through connection hole 65. Perform at the same time as embedding the material. It is a simpler process to process the light-shielding film groove portion 82 at the same time as the groove portion 64, the connection hole 66, and the through connection hole 65. However, in this case, when the insulating spacer layer 42 is formed, the insulating spacer layer 42 is also formed in the light-shielding film groove 82, and there is a possibility that the desired line width of the light-shielding film 63 cannot be obtained. .. When the pixel miniaturization progresses, it is more desirable to form the light-shielding film groove portion 82 in a separate process from the groove portion 64, the connection hole 66, and the through connection hole 65.

Conventionally, the light-shielding film 63 was separately formed of tungsten, aluminum, or the like in the step before forming the inter-board wiring 68, but by forming the light-shielding film 63 by the damascene method at the same time as forming the inter-board wiring 68, the step Can be simplified. At the same time, the insulating film thickness on the light receiving portion side (back surface side) of the first semiconductor substrate 31 can be reduced, which can contribute to the improvement of sensitivity.

Further, since the through connection hole 65 becomes deeper in the range of 1.5 to 10 times the depth of the connection hole 66, even if the connection hole 66 is embedded with a conductive material with the same opening size, the through connection is made. Voids can occur in the conductive material in the holes 65.

In the present embodiment, by opening through connection holes 65 and connection holes 66 having different opening sizes according to the depth, a hole having an optimum aspect ratio for embedding a conductive material and not increasing the layout space is provided. It is possible to form. As a result, it is possible to prevent the generation of voids when the conductive material is embedded even in the deep through connection hole 65.

Further, in the present embodiment, since the connection hole 66 is configured to be connected to the copper wiring 40 in the lowermost layer of the first multilayer wiring layer 41 on the upper part of the first semiconductor substrate 31, the periphery of the connection hole 66 and immediately below the connection hole 66. Space can be used as an effective space through which wiring can be passed. Therefore, it is advantageous for reducing the size of the chip.

In the example of the present embodiment, the insulation between the inter-board wiring 68 and the first semiconductor substrate 31 is performed by the insulating layer 67 and the insulating spacer layer 42, but it may be configured by either one. .. When the insulating spacer layer 42 is not formed, the area for the insulating spacer layer 42 is not required, so that the pixel area can be reduced and the area of the photodiode (PD) can be expanded.

Next, as shown in FIG. 14, the cap film 72 is formed so as to cover the upper part of the inter-board wiring 68 and the light-shielding film 63. The cap film 72 can be formed, for example, by forming a SiN film or a SiCN film at 10 to 150 nm. After that, an opening is formed in the insulating film 62 on the upper part of the photodiode (PD), and the waveguide material film 69 is formed in a desired region including the opening. As the waveguide material film 69, for example, SiN can be used, and the waveguide 70 is configured by the waveguide material film 69 formed in the opening. By forming the waveguide 70, the light incident from the back surface side of the first semiconductor substrate 31 is efficiently focused on the photodiode (PD). After that, the flattening film 71 is formed on the entire surface including the waveguide material film 69.

In the present embodiment, the cap film 72 and the waveguide material film 69 above the cap film 72 are separately formed in different steps, but the waveguide material film 69 may also be used as the cap film 72. Further, in the present embodiment, the waveguide 70 is formed on the light incident surface side of the photodiode (PD), but the waveguide 70 may not be formed.

Next, as shown in FIG. 15, for example, red (R), green (G), and blue (B) on-chip color filters 73 are formed on the flattening film 71 corresponding to each pixel. The on-chip color filter 73 can be formed on the upper part of a photodiode (PD) constituting a desired pixel array by forming an organic film containing a pigment or dye of a desired color and patterning the film. After that, the on-chip lens material 74a is formed in the pixel array region including the upper part of the on-chip color filter 73. As the on-chip lens material 74a, for example, an organic film or an inorganic film such as SiO, SiN, or SiON can be used, and a film is formed at 3000 nm to 4500 nm.

Next, as shown in FIG. 16, a resist film 75 for an on-chip lens is formed in a region corresponding to each pixel on the upper part of the on-chip lens material 74a to a thickness of, for example, 300 nm to 1000 nm, and an etching process is performed. As a result, the shape of the resist film 75 for the on-chip lens is transferred to the on-chip lens material 74a, and the on-chip lens 74 is formed on the upper part of each pixel as shown in FIG. After that, an oxide film such as an insulating film 62 formed on the upper part of the first semiconductor substrate 31 is etched with a CF4 gas (flow rate 10 to 200 sccm) to expose the first semiconductor substrate 31.

Next, as shown in FIG. 18, a resist film 76 in which the electrode pad portion 78 of FIG. 3 is opened is formed on the upper portion of the on-chip lens 74. As shown in FIG. 18, the resist film 76 is formed so that the open end portion is closer to the pixel side than the end portion of the on-chip lens 74.

Next, the resist film 76 is used as a mask for etching under desired etching conditions. As a result, as shown in FIG. 19, a through opening that is etched from the side of the first semiconductor substrate 31, which is the uppermost substrate, and penetrates the joint surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. Part 77 is formed. Then, the through opening 77 is formed until the aluminum wiring 57 formed in the second multilayer wiring layer 55 formed on the upper portion of the second semiconductor substrate 45, which is the lowest layer substrate, is exposed. In this etching step, for example, the first semiconductor substrate 31 is etched by etching with SF6 / O2 gas (flow rate is SF6: 50 to 500 sccm, O2: 10 to 300 sccm) for 1 to 60 minutes. Can be removed. After that, the oxide film or the like up to the aluminum wiring 57 can be removed by etching by etching with a CF4 gas (flow rate 10 to 150 sccm) for 1 to 100 minutes.

The aluminum wiring 57 exposed in this way is an electrode pad portion 78 used when connecting to the external wiring. Hereinafter, the exposed aluminum wiring 57 is referred to as an electrode pad portion 78. It is preferable that the electrode pad portions 78 are formed on three or four sides outside the pixel region formed on each chip.

Then, the laminated body 81a formed by laminating two semiconductor substrates as shown in FIG. 19 is then divided into chip portions by dicing. As a result, as shown in FIG. 4, the solid-state image sensor 81 including the first semiconductor chip portion 22 and the second semiconductor chip portion 26 is completed.

As shown in FIG. 4, the solid-state image pickup apparatus 81 thus formed can connect the bonding wire 79 to the electrode pad portion 78 and can be connected to the external wiring of the mounting board by the bonding wire 79. Then, by electrically connecting the external wiring to the electrode pad portion 78, the wirings of the first multilayer wiring layer 41 and the second multilayer wiring layer 55 connected by the inter-board wiring 68 are also electrically connected. Connected to.

In the solid-state image sensor 81 of the first embodiment, the bonding wire 79 is connected to the electrode pad portion 78 as an example, but the electrode pad portion 78 and the external wiring can be connected by using a solder bump. Bonding wires or solder bumps can be selected as desired by the user.

In the first embodiment, the inspection of the solid-state image sensor 81 on the semiconductor wafer is performed using the electrode pad portion 78. In addition, there are two inspections, one in the wafer state and the other in the final module state after cutting into chips.

According to the solid-state image sensor 81 and the manufacturing method thereof according to the first embodiment, the pixel region 23 and the control region 24 are formed in the chip portion on the first semiconductor substrate 31 side, and the chip on the second semiconductor substrate 45 side. A logic circuit 25 for signal processing is formed in the unit. Since the pixel array function and the logic function are formed on different chip portions in this way, it is possible to use the optimum process forming technique for each of the pixel array and the logic circuit. Therefore, the performance of each of the pixel array and the logic circuit can be fully exhibited, and a high-performance solid-state image pickup device can be provided.

If the configuration of FIG. 2C is adopted, it is only necessary to form a pixel region 23 that receives light on the first semiconductor chip portion 22 side, and the control region 24 and the logic circuit 25 are separated from each other to form a second semiconductor chip portion. It can be formed at 26. As a result, the optimum process technology for each functional chip can be independently selected, and the area of the product module can be reduced.

Since the conventional wafer process technology enables mixed mounting of a pixel array and a logic circuit, it is easy to manufacture.

Further, in the present embodiment, the first semiconductor substrate 31 having the pixel region 23 and the control region 24 and the second semiconductor substrate 45 having the logic circuit 25 are both bonded together in a semi-finished state, and the first semiconductor substrate is attached. 31 is thinned. That is, the second semiconductor substrate 45 is used as a support substrate when the first semiconductor substrate 31 is thinned. As a result, it is possible to save parts and reduce the manufacturing process. Further, since the through connection hole 65 and the connection hole 66 are formed after the wall thickness is reduced, the aspect ratio of the holes is reduced, and the connection holes can be formed with high accuracy.

Further, since the inter-board wiring 68 can be formed by embedding a conductive material in the through connection hole 65 and the connection hole 66 having a low aspect ratio, not only a metal material such as tungsten (W) having good coating property but also a covering property can be formed. A bad metal material such as copper (Cu) can be used. That is, the conductor material constituting the inter-board wiring 68 is not restricted. As a result, the pixel area and the control circuit can be electrically connected to the logic circuit with high accuracy. Therefore, it is possible to achieve mass productivity, reduce the manufacturing cost, and manufacture a high-performance solid-state image sensor.

Further, in the present embodiment, the through opening 77 formed for opening the electrode pad portion 78 is formed so as to penetrate the joint surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. The electrode pad portion 78 is composed of wiring of a second multilayer wiring layer 55 below the joint surface. As a result, the electrode pad portion 78 is formed below the joint surface, which is a fragile surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. Therefore, for example, when the bonding wire 79 is pressed against the electrode pad portion 78, the bonding stress applied to the bonding surface, which is a fragile surface, can be reduced. This makes it possible to prevent cracks from being generated from the fragile bonding surface during wire bonding.

In the present embodiment, an example in which two layers of semiconductor wafers are laminated is used, but the present invention can be applied to a configuration in which two or more layers are laminated. In that case, a through opening is formed so that the wiring constituting the wiring layer of the lowermost semiconductor wafer is exposed, and the exposed wiring is used as a wiring pad portion. As a result, it is possible to reduce the occurrence of stress on the fragile joint surface between the substrates when the external wiring and the electrode pad portion are connected.

Further, as in the example of the present embodiment, in the back-illuminated solid-state image sensor, it is necessary to bring the photodiode, which is the light receiving portion, closer to the circuit, so that it is essential to thin the semiconductor layer as described above. There is. Further, it is preferable that the opening for exposing the wiring below the joint surface is shallower. Therefore, when the upper semiconductor substrate (in the present embodiment, the first semiconductor substrate) is a solid-state image sensor provided with a pixel array as in the present embodiment, the first semiconductor layer is thinned. It is preferable to open the electrode pad portion from the semiconductor substrate side of the above.

In the solid-state imaging device according to the above-described embodiment, the signal charge is an electron, the first conductive type is a p-type, and the second conductive type is an n-type. Can also be applied to. In this case, the conductive type of each semiconductor substrate, semiconductor well region or semiconductor region is reversed, and the n-type is the first conductive type and the p-type is the second conductive type.

In the above-mentioned first embodiment, the MOS type solid-state image sensor is taken as an example, but the present invention can also be applied to a semiconductor device. Next, as a second embodiment of the present invention, a semiconductor device having a structure in which different types of chips are laminated will be described.

<3. Second embodiment>
[Semiconductor device configuration example and its manufacturing method example]
20 to 26 will be used to describe the semiconductor device according to the second embodiment of the present invention together with the manufacturing method thereof. The semiconductor device 140 of the present embodiment is configured by laminating a first semiconductor substrate 101 on which a first semiconductor integrated circuit is formed and a second semiconductor substrate 102 on which a second semiconductor integrated circuit is formed. It is a semiconductor device. In FIG. 20, the parts corresponding to FIG. 4 are designated by the same reference numerals, and duplicate description will be omitted.

In the second embodiment, first, as shown in FIG. 21, a semi-finished first semiconductor integrated circuit, in this example, is provided in a region to be a chip portion of the first semiconductor substrate (semiconductor wafer) 101. Form a logic circuit. That is, a plurality of MOS transistors Tr9, Tr10, and Tr11 are formed in each chip portion of the semiconductor well region 108 formed on the first semiconductor substrate 101 made of a silicon substrate. Each of the MOS transistors Tr9 to Tr11 is configured to have a pair of source / drain regions 105 and a gate electrode 106 formed via a gate insulating film. Each MOS transistor Tr9 to Tr11 is separated by the element separation region 100.

Although a plurality of MOS transistors are formed, in FIG. 21, MOS transistors Tr9 to Tr11 are shown as representatives thereof. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors Tr9 to Tr11 can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when forming an n-channel MOS transistor, an n-type source / drain region is formed in the p-type semiconductor well region 108. When forming a p-channel MOS transistor, a p-type source / drain region is formed in the n-type semiconductor well region.

As the first semiconductor integrated circuit, for example, a semiconductor memory circuit may be used instead of the logic circuit. In this case, the logic circuit, which is the second semiconductor integrated circuit described later, is used for signal processing of the semiconductor memory circuit.

Further, after the formation of the second insulating thin film 43b, the insulating spacer layer 113 for separating the desired region in the semiconductor well region 108 of the first semiconductor substrate 101 is formed as in the first embodiment. After forming the second insulating thin film 43b, the insulating spacer layer 113 is formed by opening a desired position of the first semiconductor substrate 101 from the back surface side and embedding an insulating material. The insulating spacer layer 113 is formed in a region surrounding the inter-board wiring 115 in FIG. 20.

Next, a first multilayer wiring layer 107 is formed by laminating a plurality of layers, in this example, three layers of copper wiring 104 on the first semiconductor substrate 101 via an interlayer insulating film 103. In the present embodiment, the wiring constituting the first multilayer wiring layer 107 is made of copper, but the metal wiring may be made of other metal materials. These first multilayer wiring layers 107 can be formed in the same manner as in the first embodiment. The MOS transistors Tr9 to Tr11 are connected to the required first layer copper wiring 104 via the connecting conductor 112. Further, the three-layer copper wiring 104 is connected to each other via the connecting conductor 112.

On the other hand, as shown in FIG. 22, a second semiconductor integrated circuit in a semi-finished state, in this example, a logic circuit is formed in a region to be a chip portion of the second semiconductor substrate (semiconductor wafer) 102. That is, similarly to FIG. 20, a plurality of MOS transistors Tr12, Tr13, and Tr14 are formed in each chip portion of the semiconductor well region 116 formed on the second semiconductor substrate 102 made of silicon. Each of the MOS transistors Tr12 to Tr14 is configured to have a pair of source / drain regions 117 and a gate electrode 118 formed via a gate insulating film. Further, each MOS transistor Tr12 to Tr14 is separated by the element separation region 127.

Although a plurality of MOS transistors are formed, in FIG. 24, MOS transistors Tr12 to Tr14 are shown as representatives. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when forming an n-channel MOS transistor, an n-type source / drain region is formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, a p-type source / drain region is formed in the n-type semiconductor well region.

Next, a second multilayer wiring layer 124 in which a plurality of layers, in this example, four layers of metal wiring are laminated via an interlayer insulating film 119 is formed on the second semiconductor substrate 102. In this embodiment, an example is used in which a three-layer copper wiring 120 and a one-layer aluminum wiring 121 formed on the uppermost layer are formed. The MOS transistors Tr12 to Tr14 are connected to the required first layer copper wiring 120 via the connecting conductor 126. Further, the three-layer copper wiring 120 and the aluminum wiring 121 are connected to each other by a connecting conductor 126. Further, also in the present embodiment, barrier metal layers 129 and 130 are formed above and below the aluminum wiring 121, and the aluminum wiring 121 is connected to the lower copper wiring 120 via the lower barrier metal layer 129. Has been done. The second multilayer wiring layer 124 can be formed in the same manner as the multilayer wiring layer of the first embodiment.

Then, a warp correction film 123 for reducing warpage when the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded to each other is formed on the upper portion of the second multilayer wiring layer 124. The warp correction film 123 can also be formed in the same manner as in the first embodiment.

Next, as shown in FIG. 23, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded to each other so that the first multilayer wiring layer 107 and the second multilayer wiring layer 124 face each other. .. The bonding is performed with, for example, an adhesive. When bonding with an adhesive, an adhesive layer 125 is formed on one side of the bonding surface of the first semiconductor substrate 101 or the second semiconductor substrate 102, and the adhesive layer 125 is laminated via the adhesive layer 125. Join the two. In the present embodiment, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded to each other via the adhesive layer 125, but another example may be used in which they are bonded by plasma bonding. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surface of the first semiconductor substrate 101 and the second semiconductor substrate 102, respectively. The bonding surfaces on which this film is formed are plasma-treated and superposed, and then annealed to bond the two. The bonding process is preferably performed by a low temperature process of 400 ° C. or lower, which does not affect wiring or the like. Then, the first semiconductor substrate 101 and the second semiconductor substrate 102 are laminated and laminated to form a laminated body 140a composed of two different types of substrates.

Next, as shown in FIG. 24, one of the first semiconductor substrates 101 is ground and polished from the back surface side to make it thinner. When the thickness of the first semiconductor substrate 101 is, for example, about 600 μm, the thickness is reduced so that the film thickness is, for example, about 5 to 10 μm.

Next, as shown in FIG. 25, after thinning, in the same process as in FIGS. 10 to 13 in the first embodiment, the groove portion 164, the through connection hole 165, and the connection hole 166 are formed in the insulating spacer layer 113. To form. After that, the inter-board wiring 115 is formed in the groove portion 164, the through connection hole 165, and the connection hole 166 via the insulating layer 114. Further, although not shown, if necessary, a light-shielding film is formed in the light-shielding region as in the first embodiment. Also in the present embodiment, since the through connection hole 165 and the connection hole 166 are formed after the first semiconductor substrate 101 is thinned, the aspect ratio is reduced and the connection holes 166 can be formed as fine holes. Further, also in the present embodiment, the through connection holes 165 and the connection holes 166 having different opening sizes are opened separately according to the depth, so that the aspect ratio is optimal for embedding the conductive material and the layout space. It is possible to form a hole that does not grow. As a result, it is possible to prevent the generation of voids when the conductive material is embedded even in the deep through connection hole 165.

Then, the circuit formed on the first semiconductor substrate 101 and the circuit formed on the second semiconductor substrate 102 are electrically connected by the inter-board wiring 115. Then, in the same manner as in the first embodiment, the cap film 72 is formed on the entire surface including the upper part of the inter-board wiring 115.

Next, a through opening 132 penetrating the first semiconductor substrate 101 is formed by etching as shown in FIG. 26 using a mask (not shown) in which a desired region is opened, and the aluminum wiring 121 is formed. To expose. As a result, the electrode pad portion 142 made of the exposed aluminum wiring 121 is formed.
After that, the semiconductor device 140 of the present embodiment shown in FIG. 20 is completed by dividing into each chip portion by dicing.

As shown in FIG. 20, each of the divided chips has a bonding wire 131 connected to the electrode pad portion 142, and can be connected to the external wiring of the mounting board by the bonding wire 131. Then, by electrically connecting the external wiring to the electrode pad portion 142, between the wirings (circuits) formed on the first semiconductor substrate 101 and the second semiconductor substrate 102 connected by the inter-board wiring 115. Between) are also electrically connected.

According to the semiconductor device 140 and the manufacturing method thereof according to the second embodiment, the first semiconductor integrated circuit and the second semiconductor integrated circuit are formed on different chip portions by the optimum process technology, respectively, as described above. It is possible to provide a high-performance semiconductor integrated circuit. In addition, the manufacturing cost is reduced by laminating the first and second semiconductor wafers in a semi-finished state, thinning them, and after electrical connection of the first and second semiconductor integrated circuits, making them into chips as a finished product. It can be reduced.

Other than that, the same effect as that of the first embodiment can be obtained.

In the first embodiment and the second embodiment described above, the wiring between the substrates is the first semiconductor integrated circuit formed on the first semiconductor substrate and the second semiconductor formed on the second semiconductor substrate. An example of using it only as a wiring for electrically connecting to a body integrated circuit is shown. However, the present invention is not limited to this, and for example, by using wiring between substrates, wiring having the same potential formed separately between the first semiconductor substrate and the second semiconductor substrate (for example, power supply wiring or wiring) A part of the ground wiring) can be used in common for each board.
An example of forming the wiring between the substrates as the power supply wiring and the ground wiring commonly used for the first semiconductor substrate and the second semiconductor substrate will be described below.

<4. Third Embodiment>
FIG. 27 shows a schematic configuration diagram of the solid-state image sensor according to the third embodiment of the present invention. In FIG. 27, the parts corresponding to FIG. 4 are designated by the same reference numerals, and duplicate description will be omitted.

FIG. 27 shows a region including a pixel region 23 and a control region 24 of the solid-state image sensor, and the transistor and the photodiode are not shown for simplification.

As shown in FIG. 27, in the pixel region 23, the copper wiring 40a for outputting the pixel signal formed on the first semiconductor substrate 31 is the uppermost layer of the second multilayer wiring layer 55 via the inter-board wiring 68. It is connected to a signal wiring 57a formed of wiring. In this case, in the circuit configuration shown in FIG. 3, the wiring between the substrates is formed between the wiring connected to the drain of the selection transistor formed on the first semiconductor substrate 31 and the signal wiring. Then, the processing after the signal wiring 57a is performed in the logic circuit 25 configured by the second semiconductor substrate 45.

In the present embodiment, the power supply wiring 57b and the ground wiring 57c formed by the wiring of the uppermost layer of the second multilayer wiring layer 55 and the copper wiring 40b formed by the wiring of the uppermost layer of the first multilayer wiring layer 41 , 40c are connected to each other via the inter-board wiring 68. As a result, the power supply wiring 57b and the ground wiring 57c are shared between the first semiconductor substrate 31 and the second semiconductor substrate 45.

In a three-dimensional device in which two semiconductor substrates are bonded and connected by wiring between boards, a wiring layer (in FIG. 27, a first multilayer wiring layer 41 and a second layer wiring layer 41 and a second layer) is used to reduce a step on the bonded surface of the boards. There is a problem that the multilayer wiring layer 55) cannot be formed thickly. For this reason, in the conventional 3D device, the distance between the wirings becomes short, and the resistance between the wirings cannot be reduced. It causes an enlargement of the element or noise due to a power drop.

In the solid-state imaging device of the present embodiment, the power supply wiring 57b and the ground wiring 57c are shared between the first semiconductor substrate 31 and the second semiconductor substrate 45 formed vertically via the inter-board wiring 68. By doing so, it is possible to effectively form low resistance wiring. Further, by forming the back surface wiring connected to the inter-board wiring 68 on the back surface side of the thinned first semiconductor substrate 31, it is possible to straddle the element or the different potential wiring.

Hereinafter, a wiring layout in a laminated chip in which a first semiconductor chip (hereinafter, upper chip) and a second semiconductor chip (hereinafter, lower chip) are laminated, and a design method thereof will be described.

FIG. 28A shows a schematic configuration diagram of the laminated chip 90 when a part of the power supply circuit 92 in which the power supply wiring 57b is formed is formed by the back surface wiring 99 in the solid-state image sensor of the present embodiment. Further, FIG. 28B shows, as a comparative example, a schematic configuration diagram of the laminated chip 91 in the case where all the power supply circuits 92 in which the power supply wiring 57b is formed are formed in the second multilayer wiring layer 55.

As shown in FIG. 28A, the power supply wiring between the chips is shared between the first semiconductor substrate 31 and the second semiconductor substrate 45 via the inter-board wiring 68. Then, the terminal connected to the power supply wiring of the power supply circuit 92 is connected to the mounting board via the power supply wiring 57b of the uppermost layer of the second multilayer wiring layer 55. Further, a part of the power supply circuit 92 formed by the first multilayer wiring layer 41 is interrupted at a position where the overlap of layouts can be minimized, and is composed of the back surface wiring 99 via the inter-board wiring 68. That is, in the present embodiment, the back surface wiring 99 formed on the back surface side of the first semiconductor substrate 31 is a part of the power supply circuit 92 (region a surrounded by the broken line) in the configuration of FIG. 28B shown as a comparative example. Consists of. In this case, the back surface wiring 99 can be formed by the damascene method in the same manner as the connection wiring 68a formed on the upper portion of the inter-board wiring 68.

As described above, in the example of FIG. 28A, a part of the power supply circuit 92 is moved to the back surface side of the first semiconductor substrate 31 and is configured by the back surface wiring 99, so that the wiring can be vertically laminated. Therefore, the area of the power supply circuit 92 can be reduced as compared with the configuration of FIG. 28B.

FIG. 29A shows a block diagram showing the connection of the laminated chip 90 in the present embodiment from the power supply wiring to the power supply terminal and the connection from the ground wiring to the ground terminal. Further, FIG. 29B shows a block diagram showing a connection from the power supply wiring to the power supply terminal and a connection from the ground wiring to the ground terminal of the circuit portion of the laminated chip 91 in the comparative example.

29A and 29B are schematic configuration diagrams of the main parts when the laminated chips 90 and 91 in which the upper chip and the lower chip are laminated are viewed from the upper surface, and the circuit portion 96 and the lower chip formed on the upper chip are formed. The formed circuit part 97 is schematically shown.

In the comparative example, as shown in FIG. 29B, the power supply wiring 40b and the grounding wiring 40b of the circuit portion 96 of the upper chip and the power supply wiring 57b and the grounding wiring 57c of the circuit portion 97 of the lower chip are separately connected to the power supply terminal 95 and the grounding wiring. It is connected to the ground terminal 94. In this case, it is necessary to route the power supply wirings 40b and 57b and the ground wirings 40c and 57c on both the upper chip and the lower chip.

In this way, in the design of laminated chips, in order to operate the upper and lower chips independently, the connection to the input / output terminals such as power supply wiring or ground wiring, and the protection circuit of the input / output section (not shown). Must be completed within each chip. However, in the laminated chip 91 as shown in FIG. 29B, the layout efficiency is poor and the chip cost is increased due to the configuration in which the wiring of the shared potential such as the power supply wiring and the grounding wiring and the protection circuit (not shown) are overlapped on both chips. Be a factor

On the other hand, in the configuration of the present embodiment, as shown in FIG. 29A, the power supply wirings 40b and 57b and the ground wirings 40c and 57c in the upper chip and the lower chip are connected to the connection hole 66 and the through connection hole 65, respectively. It is connected via the formed board-to-board wiring and backside wiring 99. The connection to the ground terminal 94 and the power terminal 95 is made by the power supply wiring 57b and the ground wiring 57c of the lower chip. Therefore, in the upper chip, after the power supply wiring 40b and the ground wiring 40c are connected to the inter-board wiring 68, it is not necessary to route the wiring. As a result, as compared with the example of FIG. 29B, a surplus space is created in the region z surrounded by the broken line shown in FIG. 29A, so that a new circuit can be formed in this surplus space. As a result, the optimum arrangement that maximizes the chip area can be realized.

In the present embodiment, a part of the circuit is configured by the back surface wiring 99 formed on the back surface side of the first semiconductor substrate 31, but the substrate side has more extra space in the site area of the wiring. A common circuit may be formed between the two chips. This makes it possible to reduce the number of wiring layers and the layout area of each other's multilayer wiring layers.

By the way, when wirings having the same potential such as power supply wirings and grounding wirings are originally formed on the same substrate, it can be easily realized to be shared between adjacent circuits and reduce the layout area. However, in the configuration in which the two-layer chips are formed on separate substrates, it is not easy to share the wiring of the common potential because the connection path of the mutual circuit is limited by the wiring between the substrates.
Hereinafter, a design method for realizing the design of the solid-state image sensor of the present embodiment will be described.

FIG. 30 shows a design method of the solid-state imaging device of the present embodiment, and FIGS. 31 to 34 show an upper chip (A in FIGS. 31 to 34) and a lower chip (FIGS. 31 to 34) according to the design process. 34 B) The manufacturing process diagram is shown.

In the solid-state imaging device of the present embodiment, in order to connect the upper chip 22 and the lower chip 26 to be stacked by the inter-board wiring, it is important to arrange the inter-board wiring 68 at a position that does not batting with the circuit or the wiring. be.

First, the chip size is determined from the total circuit area (step S1). Next, the circuits to be inserted into the upper chip 22 and the lower chip 26 are classified (step S2). In this embodiment, as shown in FIGS. 31A and 31B, a pixel region 23 and a control circuit 96 are formed on the upper chip 22, and a logic circuit 97 and an input / output terminal 12 are formed on the lower chip 26. do.

Next, the layout of the wiring between the boards is determined. The layout of the wiring between the boards is such that many signal lines are directly connected between the upper chip 22 and the lower chip 26 (in a solid-state image sensor, the connection point between the pixel and the signal wiring). In addition, it is determined from the area of custom design (designed by the customer's order) (step S2). As a result, the arrangement area of the inter-board wiring by the custom design is determined in the area shown by the area z1 of FIGS. 32A and 32B. As shown in FIGS. 32A and 32B, the directly connected circuit surface (that is, the position of the inter-board wiring in the custom design) must come to the same position on the upper chip 22 and the lower chip 26, and when this is determined, the circuit Rough placement is limited.

Next, the temporary outer size of the circuit components mounted on the upper chip 22 and the lower chip 26 is defined, the temporary layout is determined, and the area of the gap where the circuit is not arranged is determined. As a result, the area where the wiring between the boards can be arranged (the area z2 in FIG. 32A) other than the custom design is determined (step S4). Regarding the lower chip 26, if the wiring for receiving the wiring between the boards can be placed, the circuit can be placed directly under the wiring. However, when the upper chip 22 is arranged with the inter-board wiring, the circuit cannot be arranged directly under and around the upper chip 22, so that the area for arranging the inter-board wiring is mainly limited by the circuit arrangement of the upper chip 22.

Next, the wiring path (wiring 88 in FIG. 32B) of the connection connection between the input / output terminal 12 and each circuit in the lower chip 26 is obtained by the same automatic wiring as in the normal circuit design (step S5). As a result, as shown in FIG. 32B, the input / output terminal 12 in the lower chip 26 and the logic circuit 97 are connected by the wiring 88.

Next, the wiring having the same potential to be connected between the upper chip 22 and the lower chip 26 is extracted (step S6). As a result, as shown in FIG. 33A, in the upper chip 22, the wiring 89 to be connected to the wiring 88 of the lower chip 26 is laid out. Next, as shown in FIGS. 34A and 34B, the distance between the wiring 89 of the upper chip 22 and the wiring 88 of the lower chip 26 is the backside wiring by automatic arrangement within the arrangementable area of the wiring between the boards determined in step S4. The placement position of the through connection hole 65 and the connection hole 66 is determined at the position that is the shortest including the above. As a result, the arrangement position of the wiring between the boards is determined (step S7). That is, here, the wiring path of the back surface wiring 99 is also determined. As a result, the desired electrodes of the lower chip 26 and the upper chip 22 are connected by inter-board wiring, and the inter-board wiring connected to the lower chip 26 and the inter-board wiring connected to the upper chip 22 are connected to the back surface wiring 99. Connected by.

The solid-state image sensor designed and manufactured in this way is completed by performing connection verification, physical verification, timing verification, and the like in the same manner as a general flow.

As described above, in the solid-state imaging device of the present embodiment, in order to form the inter-board wiring that penetrates between the stacked chips, it is necessary to form the inter-board wiring at a position that does not batting with the circuit or the wiring. It is necessary to add a process that is not in the design process of.

According to the design method of the solid-state imaging device of the present embodiment, wiring of a common potential can be connected between the upper chip 22 and the lower chip 26 by wiring between the substrates, and the back surface thereof can be formed. By using wiring, the circuit formed in the chip can be simplified. As a result, the chip area can be effectively used, and the chip size can be reduced.

Although the solid-state image pickup device has been described as an example in this embodiment, the design method of this embodiment can also be applied to the manufacture of the semiconductor device of the second embodiment.

In the conventional design of a semiconductor device with a laminated chip, the circuit is divided into functional blocks, and each is divided into upper and lower chips. On the other hand, in the semiconductor device of the present invention, since the pitch of the connection hole and the through connection hole can be made sufficiently small (for example, up to 1 μm or less), one of the functional blocks can be used without increasing the arrangement area of the wiring between the substrates. It becomes possible to move the part to another board. As a result, a part of the circuit can be moved from a board with an insufficient wiring arrangement area to a board with a large surplus area, or a part of the circuit can be used in common, and the optimum with a small surplus area as a whole. Layout is possible.

<5. Fourth Embodiment>
[Example of electronic device configuration]
The solid-state image sensor of the present invention described above can be applied to electronic devices such as camera systems such as digital cameras and video cameras, mobile phones having an image pickup function, and other devices having an image pickup function.

FIG. 35 shows a schematic configuration diagram of an electronic device according to a fourth embodiment of the present invention. FIG. 35 shows a camera 200 as an example of the electronic device of the present invention. The camera 200 according to the present embodiment is, for example, a video camera capable of shooting a still image or a moving image. The camera 200 of the present embodiment includes a solid-state image pickup device 203, an optical system 201 that guides incident light to a photoelectric conversion unit composed of a photodiode of the solid-state image pickup device 203, and a shutter device 202. Further, the camera 200 has a drive circuit 205 for driving the solid-state image pickup device 203 and a signal processing circuit 204 for processing the output signal of the solid-state image pickup device 203.

As the solid-state image sensor 203, the solid-state image sensor according to the first embodiment described above is applied. The optical system (optical lens) 201 forms an image of image light (incident light) from the subject on the image pickup surface of the solid-state image pickup device 203. As a result, the signal charge is accumulated in the solid-state image sensor 203 for a certain period of time. The optical system 201 may be an optical lens system composed of a plurality of optical lenses. The shutter device 202 controls a light irradiation period and a light blocking period for the solid-state image pickup device 203. The drive circuit 205 supplies a drive signal that controls the transfer operation of the solid-state image sensor 203 and the shutter operation of the shutter device 202. The signal transfer of the solid-state image sensor 203 is performed by the drive signal (timing signal) supplied from the drive circuit 205. The signal processing circuit 204 performs various signal processing. The video signal that has undergone signal processing is stored in a storage medium such as a memory, or is output to a monitor.

According to the electronic device such as the camera 200 according to the fourth embodiment, the solid-state image sensor 203 can be improved in performance and the manufacturing cost can be reduced. Therefore, in the present embodiment, it is possible to provide an inexpensive and highly reliable electronic device.

1 ... Solid image pickup device, 2 ... Pixel, 3 ... Pixel region, 4 ... Vertical drive circuit, 5 ... Column signal processing circuit, 6 ... Horizontal drive circuit, 7 ... Output circuit, 8 ... control circuit, 9 ... vertical signal line, 10 ... horizontal signal line, 11 ... transfer transistor, 12 ... input / output terminal, 13 ... reset transistor, 14 ... Amplification transistor, 15 ... selection transistor, 16 ... floating diffusion unit, 21 ... MOS type solid-state imaging device, 22 ... first semiconductor chip unit, 23 ... pixel region, 24. .. Control area, 25 ... Logic circuit, 26 ... Second semiconductor chip unit, 27 ... MOS type solid-state imaging device, 30 ... Unit pixel, 31 ... First semiconductor substrate , 31b ... Back surface, 32 ... Semiconductor well region, 33 ... Source / drain region, 34 ... n-type semiconductor region, 35 ... p-type semiconductor region, 36 ... Gate electrode, 38 ... element separation region, 39 ... interlayer insulating film, 40 ... copper wiring, 41 ... first multilayer wiring layer, 42 ... insulating spacer layer, 43a ... first insulating thin film, ... 43b ... second insulating thin film, 44 ... connecting conductor, 45 ... second semiconductor substrate, 46 ... semiconductor well region, 47 ... source / drain region, 48 ... gate electrode, 49 ... interlayer insulating film, 50 ... element separation region, 53 ... copper wiring, 54 ... connection conductor, 55 ... second multilayer wiring layer, 56 ... barrier metal layer, 57 ... Aluminum wiring, 57a ... Signal wiring, 57b ... Power supply wiring, 57c ... Ground wiring, 58 ... Barrier metal layer, 59 ... Warp correction film, 60 ... Adhesive layer , 61 ... Antireflection film, 62 ... Insulation film, 63 ... Light-shielding film, 64 ... Groove, 65 ... Through connection hole, 66 ... Connection hole, 67 ... Insulation layer , 68 ... Substrate-to-board wiring, 68a ... Connection wiring, 69 ... waveguide material film, 70 ... waveguide, 71 ... flattening film, 72 ... cap film, 73 ... -On-chip color filter, 74 ... on-chip lens, 74a ... on-chip lens material, 75 ... resist film, 76 ... resist film, 77 ... through opening, 78 ... electrode Pad unit, 79 ... Bonding wire, 81 ... Solid image pickup device, 81a ... Laminated body, 140 ... Semiconductor device, 140a ... Laminated body

Claims (21)

A photodiode, at least one of a transfer transistor, a reset transistor, and an amplifier transistor, and a first semiconductor substrate including a first wiring layer.
A second semiconductor substrate containing a logic circuit and a second wiring layer,
Inter-board wiring that electrically connects the first wiring layer and the second wiring layer, and
An insulating spacer layer formed on the first semiconductor substrate and surrounding the wiring between the substrates,
It is provided with an element separation region formed on the first semiconductor substrate.
The first semiconductor substrate and the second semiconductor substrate are bonded together so that the first wiring layer and the second wiring layer face each other.
The insulating spacer layer extends in a direction perpendicular to the light incident surface of the photodiode.
A part of the insulating spacer layer and a part of the element separation region are provided so as to be in contact with each other .
A through connection hole provided through the first semiconductor substrate and reaching the second wiring layer,
A groove portion and a light-shielding film groove portion provided on the light incident surface side in the first semiconductor substrate,
A connection hole provided on the light incident surface side in the first semiconductor substrate,
A region including the through connection hole, the connection hole, and the groove portion, and a conductive material formed in the light-shielding film groove portion.
Equipped with
The groove portion is formed in the through connection hole and the region in contact with the connection hole, and the conductive material in the groove portion is integrally formed with the conductive material in the through connection hole and the connection hole.
A light-shielding film is formed by the conductive material in the light-shielding film groove, and the light-shielding film is formed.
The surfaces of the conductive material in the groove and the conductive material in the light-shielding film groove are formed in the same plane.
Solid-state image sensor. The solid-state image sensor according to claim 1, wherein the insulating spacer layer has a first depth in a direction perpendicular to the light incident surface, and the first depth is at least the same depth as the photodiode. A light-shielding film provided on the light incident surface side in the first semiconductor substrate is provided, and the surfaces of the conductive material contained in the light-shielding film and the conductive material contained in the wiring between the substrates are formed on the same plane. The solid-state imaging device according to claim 1 or 2. The solid-state image sensor according to claim 3, wherein the conductive material electrically connects the first wiring layer and the second wiring layer. The solid-state image sensor according to claim 3 or 4, wherein the conductive material contains tungsten or copper. The solid-state image sensor according to any one of claims 3 to 5, wherein wiring having a common potential is connected to the first wiring layer and the second wiring layer by the conductive material. The first semiconductor integrated circuit and the second semiconductor integrated circuit formed on the light incident surface side of the first semiconductor substrate and provided on the first semiconductor substrate by backside wiring electrically connected to the conductive material. The solid-state imaging device according to claim 6, wherein a part of a circuit commonly used with a second semiconductor integrated circuit provided on a semiconductor substrate is formed. The solid-state image sensor according to any one of claims 1 to 7, wherein an insulating layer is formed on the side wall of the through connection hole. The solid-state image sensor according to any one of claims 1 to 8 , wherein the through connection hole is in contact with the barrier metal layer of the second wiring layer. The solid-state image sensor according to any one of claims 1 to 9 , wherein the through connection hole and the groove portion are arranged in a pixel region. The solid-state image sensor according to any one of claims 1 to 10 , wherein the through connection hole and the groove portion are arranged outside the pixel region. The solid-state image sensor according to claim 10 , further comprising the plurality of the through connection holes and the groove portion in the pixel region. The solid-state image pickup device according to claim 10 , wherein a plurality of the photodiodes are provided in the pixel region, and the plurality of photodiodes share a floating diffusion. The solid-state image sensor according to any one of claims 1 to 13 , wherein the diameter of the opening of the through connection hole is formed to be larger than the diameter of the opening of the connection hole. The solid-state image sensor according to any one of claims 1 to 14 , wherein the depth of the through connection hole is formed deeper than the depth of the connection hole. The solid-state image pickup device according to any one of claims 1 to 15 , wherein the second semiconductor substrate includes a signal processing circuit or a control circuit. The solid-state image sensor according to any one of claims 1 to 16 , wherein the power supply terminal and the ground terminal are formed at opposite corners of a substantially quadrangular chip. The solid-state image sensor according to any one of claims 1 to 17 , further comprising the transfer transistor, the reset transistor, the amplifier transistor, and the selection transistor in the pixel region. The solid-state image pickup device according to any one of claims 1 to 18 , wherein the first wiring layer contains copper. The solid-state image sensor according to any one of claims 1 to 19 , wherein the second wiring layer contains copper or aluminum. The solid-state image sensor according to any one of claims 1 to 20 and the solid-state image sensor.
An optical system that guides incident light to the light incident surface of the photodiode,
An electronic device including a signal processing circuit that processes an output signal of the solid-state image sensor.

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