JP5915636B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device such as a solid-state imaging device and a manufacturing method thereof.

  As a solid-state imaging device, an amplification-type solid-state imaging device represented by a MOS type image sensor such as a CMOS (Complementary Metal Oxide Semiconductor) is known. In addition, a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor is known. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, MOS image sensors are often used as solid-state imaging devices mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants) from the viewpoint of low power supply voltage and power consumption.

  The MOS type solid-state imaging device includes a pixel array (pixel region) in which unit pixels are formed by a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors, and the unit pixels are arranged in a two-dimensional array, and a peripheral area. It has a circuit area. The plurality of pixel transistors are formed of MOS transistors, and include transfer transistors, reset transistors, three transistors of amplification and transistors, or four transistors including a selection transistor.

  Conventionally, in such a MOS type solid-state imaging device, a semiconductor chip in which a pixel region in which a plurality of pixels are arranged is formed and a semiconductor chip in which a logic circuit for performing signal processing is electrically connected to each other. Various solid-state imaging devices configured as devices have been proposed. For example, Patent Document 1 discloses a semiconductor module in which a back-illuminated image sensor chip having a micropad for each pixel cell and a signal processing chip in which a signal processing circuit is formed and having a micropad are connected by microbumps. Has been. In Patent Document 2, a sensor chip, which is a back-illuminated MOS solid-state imaging device provided with an imaging pixel unit, and a signal processing chip provided with a peripheral circuit for signal processing are mounted on an interposer (intermediate substrate). A device is disclosed. Patent Document 3 has a configuration including an image sensor chip, a thin circuit board, and a logic circuit chip that performs signal processing. A configuration is disclosed in which the thin film circuit board and the logic circuit chip are electrically connected, and the thin film circuit board is electrically connected from the back surface of the image sensor chip through a through-hole via.

  Patent Document 4 discloses a solid-state imaging device in which a through-electrode is provided in a solid-state imaging device supported by a transparent substrate, and the solid-state imaging device is electrically connected to a flexible circuit board via the through-electrode. Furthermore, Patent Document 5 discloses a configuration in which an electrode penetrating a support substrate is provided in a back-illuminated solid-state imaging device.

  As shown in Patent Documents 1 to 3, various techniques for mounting different types of circuit chips such as an image sensor chip and a logic circuit have been proposed. The conventional technique is characterized in that the functional chips are almost completed, and through-holes are formed so that the chips can be interconnected on one chip. Yes.

JP 2006-49361 A JP 2007-13089 A JP 2008-130603 A Japanese Patent No. 40000507 JP 2003-31785 A

  As seen in the above-described conventional solid-state imaging device, it has been known as an idea to configure a semiconductor device by connecting different types of chips with a connection conductor penetrating the substrate. However, it is necessary to open a connection hole while ensuring insulation on a deep substrate, and it has been difficult to put it to practical use because of the cost efficiency of the manufacturing process required for processing the connection hole and embedding the connection conductor.

  On the other hand, in order to form a small contact hole of about 1 μm, for example, it is necessary to make the upper chip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning and an increase in cost are caused. Moreover, in order to fill the connection hole with a high aspect ratio with the connection conductor, it is necessary to use a CVD film having good coverage such as tungsten (W) as the connection conductor, and the connection conductor material is restricted.

  In order to have economic efficiency that can be easily applied in mass production, the aspect ratio of this connection hole is dramatically reduced to make it easier to form, and it is processed within the conventional wafer manufacturing process without using special connection hole processing. It is desirable to be able to select a technology that can be used.

Further, in a solid-state imaging device or the like, it is desired that an image region and a logic circuit that performs signal processing are formed so as to sufficiently exhibit their respective performances, thereby improving performance.
It is desired that not only the solid-state imaging device but also a semiconductor device having another semiconductor integrated circuit be formed so that the performance of each semiconductor integrated circuit can be sufficiently exerted to improve the performance.

  Furthermore, in a device in which chips are bonded to each other by bonding substrates on the circuit surfaces, an opening to the bonding pad and the pad needs to be formed in the vicinity of the bonding interface for mounting connection. However, when the substrate is as thick as several hundred microns, an expensive mounting process such as opening of deep holes and formation of extraction electrodes and formation of solder balls must be performed.

  In addition, since the bonding surface is a fragile structure compared to other interlayer boundaries, if the bonding surface boundary exists under the bonding pad, the stress generated during bonding is concentrated on the fragile part, Cracks may occur from the bonded surface.

  Further, when the semiconductor wafer is divided by dicing, cracks may be generated from the bonded surfaces of the substrates.

  In view of the above points, the present invention provides a semiconductor device, such as a solid-state imaging device, which achieves high performance by fully exhibiting the performance of each of the semiconductor wafers to be stacked, mass production, and cost reduction. A manufacturing method is provided.

In the semiconductor device according to the present invention, a first semiconductor integrated circuit is formed, a first semiconductor substrate having a first wiring layer, a second semiconductor integrated circuit is formed, and a second wiring layer is provided. 2 semiconductor substrates. Then, an inter-substrate wiring is provided penetrating from the upper part of the first semiconductor substrate to the second wiring layer and electrically connecting the first semiconductor substrate and the second semiconductor substrate.
In addition, a through opening formed through the first semiconductor substrate is provided so that the electrode pad formed in the second wiring layer is exposed from the first semiconductor substrate. Furthermore, it has a groove portion that is formed in at least the first semiconductor substrate and serves as a crack stop that prevents cracks from occurring in the chip portion when the chip is divided. Then, the first semiconductor substrate and the second semiconductor substrate are bonded so that the first wiring layer side and the second wiring layer side face each other, and the groove portion serving as a crack stop is formed on the first semiconductor substrate. It is formed to penetrate.

  In the semiconductor device of the present invention, the electrode pad portion is constituted by the wiring exposed in the through opening that reaches the wiring formed on the second semiconductor substrate in the lowermost layer from the upper first semiconductor substrate side. As a result, the wiring pad portion is formed below the bonding surface of the stacked semiconductor substrates. For this reason, it is possible to reduce stress applied to a fragile joint surface when wire bonding or the like is performed on the wiring pad portion, and the semiconductor device is a high-performance and highly reliable semiconductor device.

In the method for manufacturing a semiconductor device according to the present invention, a first semiconductor integrated circuit is formed, a first semiconductor substrate having a first wiring layer, a second semiconductor integrated circuit is formed, and a second wiring layer is formed. The first semiconductor substrate and the second semiconductor substrate are bonded to each other so that the first wiring layer side and the second wiring layer side face each other. Next, a through hole penetrating from the upper part of the first semiconductor substrate to the second wiring layer is formed, and a metal material is embedded in the through hole, thereby electrically connecting the first semiconductor substrate and the second semiconductor substrate. The inter-substrate wiring connected to the first semiconductor substrate is formed, and at least the first semiconductor substrate is formed with a groove portion that penetrates the first semiconductor substrate to prevent cracks from occurring in the chip portion when the chip is divided. To do. Then, a through opening that penetrates the first semiconductor substrate is formed so that the electrode pad portion formed in the second wiring layer is exposed.

  In the method for manufacturing a semiconductor device of the present invention, the electrode pad portion is formed with a through opening formed so as to reach the electrode pad portion formed on the second semiconductor substrate from the first semiconductor substrate side. Exposed. For this reason, when wire bonding is performed on the wiring pad portion, for example, stress applied to a fragile joint surface can be reduced.

  According to the present invention, a plurality of semiconductor wafers on which a circuit capable of sufficiently exhibiting the respective performances is formed by an optimum process technology is configured to be laminated, so that it is excellent in mass productivity, low in cost and high in cost. A semiconductor device with high performance can be obtained.

It is a schematic block diagram which shows an example of the MOS solid-state imaging device applied to this invention. It is a schematic diagram of the conventional solid-state imaging device. B and C are schematic views of a solid-state imaging device according to an embodiment of the present invention. It is a schematic block diagram of the principal part which shows the solid-state imaging device which concerns on 1st Embodiment. FIG. 6 is a manufacturing process diagram (part 1) illustrating an example of a manufacturing method of the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 2) illustrating the example of the method for manufacturing the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 3) illustrating the example of the manufacturing method of the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 4) illustrating an example of a manufacturing method of the solid-state imaging device according to the first embodiment; FIG. 6 is a manufacturing process diagram (part 5) illustrating an example of a manufacturing method of the solid-state imaging device according to the first embodiment; It is a manufacturing process figure (the 6) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 7) which shows the example of a manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 8) which shows the solid-state imaging device which concerns on 1st Embodiment, and its manufacturing method. It is a manufacturing process figure (the 9) which shows the manufacturing method of the solid-state imaging device concerning a 1st embodiment. It is a manufacturing process figure (the 10) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 11) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 12) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 13) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 14) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. It is a manufacturing process figure (the 15) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. 1A and 1B are a schematic configuration diagram showing the entire semiconductor wafer and an enlarged view of a region a. It is a schematic block diagram of the cross section containing an electrode pad part and a scribe line. It is a schematic sectional block diagram of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a schematic cross-sectional block diagram of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. FIG. 10 is a manufacturing process diagram (part 1) illustrating a manufacturing method of a semiconductor device according to a third embodiment; FIG. 10 is a manufacturing process diagram (part 2) illustrating the manufacturing method of the semiconductor device according to the third embodiment; FIG. 11 is a manufacturing process diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment; FIG. 11 is a manufacturing process diagram (part 4) illustrating the manufacturing method of the semiconductor device according to the third embodiment; FIG. 11 is a manufacturing process diagram (part 5) illustrating the manufacturing method of the semiconductor device according to the third embodiment; FIG. 11 is a manufacturing process diagram (part 6) illustrating the manufacturing method of the semiconductor device according to the third embodiment; It is a schematic block diagram which shows the electronic device which concerns on the 4th Embodiment of this invention.

Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. Schematic configuration example of MOS type solid-state imaging device First Embodiment (Configuration Example of Back-illuminated Solid-State Imaging Device and Method for Manufacturing the Same)
3. Second Embodiment (Configuration Example of Backside Illumination Type Solid-State Imaging Device)
4). Third Embodiment (Configuration Example of Semiconductor Device and Method for Manufacturing the Same)
5. Fourth Embodiment (Configuration Example of Electronic Device)

<1. Schematic configuration example of MOS solid-state imaging device>
FIG. 1 shows a schematic configuration of a MOS type solid-state imaging device applied to the semiconductor device of the present invention. This MOS type solid-state imaging device is applied to the solid-state imaging device of each embodiment. The solid-state imaging device 1 of this example includes a pixel region (so-called pixel array) 3 in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate (not shown) such as a silicon substrate, and a peripheral circuit. And is configured. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, a selection transistor may be added to configure the transistor with four transistors. Since the equivalent circuit of the unit pixel is the same as usual, the detailed description is omitted. The pixel 2 can be configured as one unit pixel. Further, the pixel 2 may have a shared pixel structure. This pixel sharing structure is a structure in which a plurality of photodiodes share a floating diffusion constituting a transfer transistor and other transistors other than the transfer transistor.

  The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

  The control circuit 8 receives an input clock and data for instructing an operation mode, and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8 generates a clock signal and a control signal that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. These signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixels in units of rows. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 in the vertical direction sequentially in units of rows, and according to the amount of light received in, for example, a photodiode serving as a photoelectric conversion unit of each pixel 2 through the vertical signal line 9. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

  The column signal processing circuit 5 is disposed, for example, for each column of the pixels 2, and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. That is, the column signal processing circuit 5 performs signal processing such as CDS, signal amplification, and AD conversion for removing fixed pattern noise unique to the pixel 2. A horizontal selection switch (not shown) is connected to the horizontal signal line 10 at the output stage of the column signal processing circuit 5.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing and outputs the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, only buffering may be performed, or black level adjustment, column variation correction, various digital signal processing, and the like may be performed. The input / output terminal 12 exchanges signals with the outside.

  Next, the structure of the MOS type solid-state imaging device according to this embodiment will be described. 2A is a schematic configuration diagram illustrating a structure of a conventional MOS solid-state imaging device, and FIGS. 2B and 2C are schematic configuration diagrams illustrating a structure of a MOS solid-state imaging device according to the present embodiment.

  As shown in FIG. 2A, a conventional MOS solid-state imaging device 151 is configured by mounting a pixel region 153, a control circuit 154, and a logic circuit 155 for signal processing in one semiconductor chip 152. The Normally, the image sensor 156 is configured by the pixel region 153 and the control circuit 154.

  On the other hand, as shown in FIG. 2B, the MOS type solid-state imaging device 21 according to the present embodiment includes a pixel region 23 and a control circuit 24 mounted on the first semiconductor chip unit 22, and the second semiconductor chip unit. 26 includes a logic circuit 25 including a signal processing circuit for signal processing. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to constitute the MOS type solid-state imaging device 21 as one semiconductor chip.

  As shown in FIG. 2C, a MOS type solid-state imaging device 27 according to another embodiment of the present invention has a pixel region 23 mounted on the first semiconductor chip unit 22, and a control circuit connected to the second semiconductor chip unit 26. 24. A logic circuit 25 including a signal processing circuit is mounted. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to constitute a MOS solid-state imaging device 27 as one semiconductor chip.

The MOS type solid-state imaging device according to the above-described embodiment has a structure in which different types of semiconductor chips are stacked. As will be described later, the manufacturing method and the structure obtained based on the manufacturing method are characterized. have.
In the embodiment described below, the solid-state imaging device of the present invention and the manufacturing method thereof will be described.

<2. First Embodiment>
[Configuration Example of Solid-State Imaging Device and Method for Manufacturing the Same]
A backside illumination type MOS solid-state imaging device will be described together with its manufacturing method as a semiconductor device according to the first embodiment of the present invention, with reference to FIGS.

  FIG. 3 is a schematic cross-sectional configuration diagram (completed drawing) including the electrode pad portion 78 of the solid-state imaging device according to the present embodiment. The solid-state imaging device 81 according to the present embodiment includes a first semiconductor chip unit 22 including a pixel array (hereinafter referred to as a pixel region) 23 and a control circuit 24, and a second semiconductor chip unit on which a logic circuit 25 is mounted. 26 are stacked one above the other in an electrically connected state. A manufacturing method of the solid-state imaging device 81 according to the present embodiment will be described with reference to FIGS.

  In the first embodiment, first, as shown in FIG. 4, an image sensor in a semi-finished state is provided in each chip portion of a first semiconductor wafer (hereinafter referred to as a first semiconductor substrate) 31. That is, the pixel region 23 and the control circuit 24 are formed. That is, a photodiode (PD) serving as a photoelectric conversion unit of each pixel is formed in a region serving as each chip portion of the first semiconductor substrate 31 formed of a silicon substrate, and the source / source of each pixel transistor is formed in the semiconductor well region 32. A drain region 33 is formed. The semiconductor well region 32 is formed by introducing a first conductivity type, for example, a p-type impurity, and the source / drain region 33 is formed by introducing a second conductivity type, for example, an n-type impurity. The photodiode (PD) and the source / drain region 33 of each pixel transistor are formed by ion implantation from the substrate surface.

  The photodiode (PD) is formed having an n-type semiconductor region 34 and a p-type semiconductor region 35 on the substrate surface side. A gate electrode is formed on the surface of the substrate constituting the pixel via a gate insulating film, and pixel transistors Tr1 and Tr2 are formed by the source / drain regions 33 paired with the gate electrode. In FIG. 4, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. A pixel transistor Tr1 adjacent to the photodiode (PD) corresponds to a transfer transistor, and its source / drain region corresponds to a floating diffusion (FD). Each unit pixel 30 is separated by an element isolation region 38.

  On the other hand, on the control circuit 24 side, a MOS transistor constituting the control circuit is formed on the first semiconductor substrate 31. In FIG. 3, the MOS transistors constituting the control circuit 24 are represented by the MOS transistors Tr3 and Tr4. Each of the MOS transistors Tr3 and Tr4 is formed by an n-type source / drain region 33 and a gate electrode 36 formed through a gate insulating film.

Next, a first interlayer insulating film 39 is formed on the surface of the first semiconductor substrate 31, and then a connection hole is formed in the interlayer insulating film 39, and a connection conductor 44 connected to a required transistor is formed. . When forming the connection conductors 44 having different heights, the first insulating thin film 43a is formed of, for example, a silicon oxide film on the entire surface including the upper surface of the transistor, and the second insulating thin film 43b serving as an etching stopper is formed of, for example, a silicon nitride film. And laminate. A first interlayer insulating film 39 is formed on the second insulating thin film 43b. The first interlayer insulating film 39 is formed, for example, by forming a P-SiO film (plasma oxide film) at 10 to 150 nm, and then forming an NSG (non-doped silicate glass) film or a PSG film (phosphosilicate glass) at 50 nm to 1000 nm. Form with. Then, after forming a dTEOS film with a thickness of 100 to 1000 nm, a P-SiH ₄ film (plasma oxide film) can be formed with a thickness of 50 to 200 nm.

  Thereafter, connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched at each portion so as to be continuous with each connection hole, thereby forming a connection hole. Then, the connection conductor 44 is embedded in each connection hole.

  In addition, after the formation of the second insulating thin film 43b, an insulating spacer layer 42 that separates a desired region in the semiconductor well region 32 of the first semiconductor substrate 31 is formed. The insulating spacer layer 42 is formed by opening a desired position of the first semiconductor substrate 31 from the back surface side and embedding an insulating material after the second insulating thin film 43b is formed. The insulating spacer layer 42 is formed in a region surrounding the inter-substrate wiring 68 in FIG.

  Next, a multilayer wiring layer 41 is formed by forming a plurality of layers, in this example, three layers of copper wirings 40 via an interlayer insulating film 39 so as to be connected to each connection conductor 44. Usually, each copper wiring 40 is covered with a barrier metal layer (not shown) to prevent Cu diffusion. The barrier metal layer can be formed, for example, by forming a SiN film or a SiC film at 10 to 150 nm. The interlayer insulating film 39 from the second layer can be formed by forming a dTEOS film (a silicon oxide film formed by a plasma CVD method) with a thickness of 100 to 1000 nm. The multilayer wiring layer 41 is formed by alternately forming the interlayer insulating film 39 and the copper wiring 40 formed through the barrier metal layer. In the present embodiment, the multilayer wiring layer 41 is formed of the copper wiring 40, but it is also possible to use a metal wiring made of other metal materials.

  Through the steps so far, the first semiconductor substrate 31 having the pixel region 23 and the control circuit 24 in a semi-finished product state is formed.

  On the other hand, as shown in FIG. 5, a logic circuit 25 including a signal processing circuit for signal processing in a semi-finished product state is provided in each chip portion of a second semiconductor substrate (semiconductor wafer) 45 made of silicon, for example. Form. That is, a plurality of MOS transistors constituting the logic circuit 25 are formed in the p-type semiconductor well region 46 on the surface side of the second semiconductor substrate 45 so as to be isolated by the element isolation region 50. Here, the plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, Tr8. Each of the MOS transistors Tr6, Tr7, Tr8 is formed having a pair of n-type source / drain regions 47 and a gate electrode 48 formed through a gate insulating film. The logic circuit 25 can be composed of a CMOS transistor.

  Next, a first interlayer insulating film 49 is formed on the surface of the second semiconductor substrate 45, and then a connection hole is formed in the interlayer insulating film 49, and a connection conductor 54 connected to a required transistor is formed. . When the connection conductors 54 having different heights are formed, the first insulating thin film 43a, for example, a silicon oxide film, and the second insulating thin film 43b, for example, a silicon nitride film serving as an etching stopper are formed on the entire surface including the upper surface of the transistor, as described above. Laminate. A first interlayer insulating film 49 is formed on the second insulating thin film 43b. Then, connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness are selectively etched at each portion so as to be continuous with each connection hole, thereby forming a connection hole. Then, the connection conductor 54 is embedded in each connection hole.

  Thereafter, the multilayer wiring layer 55 is formed by repeating the formation of the interlayer insulating film 49 and the formation of a plurality of layers of metal wiring. In this embodiment, after forming the three-layer copper wiring 53 in the same manner as the formation process of the multilayer wiring layer 41 formed on the first semiconductor substrate 31, the aluminum wiring 57 is formed in the uppermost layer. Let's take an example. The aluminum wiring 57 is formed by first forming the interlayer insulating film 49 on the uppermost copper wiring 53 and then etching away the interlayer insulating film 49 so that a desired position on the uppermost copper wiring 53 is exposed. , Forming a connection hole. Then, in a region including the inside of the connection hole, a laminated film made of TiN (lower layer) / Ti (upper layer) serving as the barrier metal layer 56 is 5 to 10 nm, or a laminated film made of TaN (lower layer) / Ta (upper layer) is made 10 to 10. The film is formed at 100 nm. Thereafter, the connection hole is covered and aluminum is deposited at a thickness of 500 to 2000 nm, and then the aluminum wiring 57 is formed by patterning into a desired shape. Further, a barrier metal layer 58 required in a later process is formed on the aluminum wiring 57. The barrier metal layer 58 can also have the same configuration as the barrier metal layer 56 formed under the aluminum wiring 57. Then, an interlayer insulating film 49 is formed so as to cover the aluminum wiring 57 on which the barrier metal layer 58 is formed. As the interlayer insulating film 49 on the aluminum wiring 57, for example, an HDP film (high density plasma oxide film) or a P-SiO film (plasma oxide film) is formed with a thickness of 500 to 2000 nm, and then a P-SiO film is further formed thereon. It can be formed by forming a film with a thickness of 100 to 2000 nm. As described above, the multilayer wiring layer 55 is formed which includes the three-layer copper wiring 53 formed through the interlayer insulating film 49 and the aluminum wiring 57 formed in the uppermost layer.

  A stress correction film 59 for reducing stress when the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded is formed on the multilayer wiring layer 55. The stress correction film 59 can be formed, for example, by forming a P-SiN film or a P-SiON film (plasma oxynitride film) at 100 to 2000 nm.

  Through the above steps, the second semiconductor substrate 45 having the semi-finished logic circuit is formed.

  Next, as shown in FIG. 6, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded so that the multilayer wiring layers 41 and 55 face each other. The bonding is performed with an adhesive, for example. In the case of bonding with an adhesive, an adhesive layer 60 is formed on one side of the bonding surface of the first semiconductor substrate 31 or the second semiconductor substrate 45, and the adhesive layer 60 is overlapped via the adhesive layer 60. Join them together. In the present embodiment example, the first semiconductor substrate 31 in which the pixel region is configured is disposed in the upper layer, and the second semiconductor substrate 45 is disposed in the lower layer and bonded together.

  Further, in the present embodiment example, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded together via the adhesive layer 60, but other examples may be bonded by plasma bonding. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surface between the first semiconductor substrate 31 and the second semiconductor substrate 45, respectively. The joining surface on which this film is formed is overlapped by plasma treatment, and then annealed to join them together. The bonding process is preferably performed by a low-temperature process of 400 ° C. or lower that does not affect the wiring or the like.

  Then, the first semiconductor substrate 31 and the second semiconductor substrate 45 are stacked and bonded to each other, whereby a stacked body 81a including two different substrates is formed.

  Next, as shown in FIG. 7, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface 31 b side of the first semiconductor substrate 31. This thinning is performed so that the photodiode (PD) faces. As the first semiconductor substrate 31, for example, a semiconductor substrate formed using a p-type high-concentration impurity layer as an etching stopper layer (not shown) is used. Can be After thinning, a p-type semiconductor layer for suppressing dark current is formed on the back surface of the photodiode (PD). The thickness of the first semiconductor substrate 31 is, for example, about 600 μm, but is reduced to, for example, about 3-5 μm. Conventionally, such thinning has been performed by attaching a separately prepared support substrate to the multilayer wiring layer 41 side of the first semiconductor substrate 31. However, in the present embodiment, the thickness of the first semiconductor substrate 31 is reduced by using the second semiconductor substrate 45 on which the logic circuit 25 is formed as a support substrate. The back surface 31b of the first semiconductor substrate 31 is a light incident surface when configured as a back-illuminated solid-state imaging device.

Next, as shown in FIG. 8, an antireflection film 61 is formed on the back surface of the first semiconductor substrate 31. The antireflection film 61 can be formed, for example, by depositing TaO ₂ or HfO ₂ at a thickness of 5 to 100 nm. The antireflection film 61 made of TaO ₂ or HfO ₂ has a pinning effect at the interface of the first semiconductor substrate 31, and dark current generated at the back side interface of the first semiconductor substrate 31 by the antireflection film 61 is generated. It is suppressed. After the antireflection film 61 is formed, an annealing process is performed to perform dehydration from TaO ₂ or HfO ₂ constituting the antireflection film 61. Since the antireflection film 61 is dehydrated by this annealing treatment, peeling of the film such as an HDP film formed in a later process can be prevented. Thereafter, a first insulating film 62 is formed on the antireflection film 61 to a thickness of 100 to 1500 nm by an HDP film or a P-SiO film. Then, after the first insulating film 62 is formed, a desired region is opened so that the back side of the first semiconductor substrate 31 is exposed, and a photodiode (PD) is formed covering the opening. A light shielding film 63 is formed in a desired region excluding the upper portion of the region. The light shielding film 63 can be formed of, for example, W (tungsten) or Al, and may be formed of a laminated film of W / Ti (or Ta, TiN), or Al / Ti (or Ta, TiN). You may form by the laminated film of. In this case, for example, the lower layer film is formed with a thickness of 50 to 500 nm, and then the upper layer film is formed with a thickness of 5 to 100 nm.

Next, as shown in FIG. 9, an insulating film 62 is further formed on the light shielding film 63 by, for example, a SiO ₂ film, and then the first layer which is the upper substrate is formed in a desired region inside the insulating spacer layer 42. First groove portion 64 is formed from the semiconductor substrate 31 side. The first groove portion 64 is formed to a depth that does not reach the first semiconductor substrate 31, for example.

  Next, as shown in FIG. 10, in the desired bottom region of the first groove 64, the second semiconductor substrate 45 passes through the bonding surface of the first semiconductor substrate 31 and the second semiconductor substrate 45. Open up to a depth just before reaching the aluminum wiring 57 formed in (1). Thereby, the second groove portion 65 is formed. Next, similarly, in the desired bottom region of the first groove portion 64, the copper wiring 40 of the uppermost layer (the lowermost side in FIG. 10) of the multilayer wiring layer 41 formed on the first semiconductor substrate 31 is reached. Open up to the previous depth. Thereby, the third groove 66 is formed. Since the second groove portion 65 and the third groove portion 66 are formed after the first semiconductor substrate 31 is thinned, the aspect ratio becomes small and can be formed as fine holes.

Next, an insulating layer 67 made of, for example, a SiO ₂ film is formed in the region including the sidewalls and bottoms of the first to third groove portions 64, 65, 66 and etched back, as shown in FIG. The insulating layer 67 is left only on the side walls of the first to third grooves. Thereafter, the bottom portions of the second and third groove portions 65 and 66 are further etched away, whereby the aluminum wiring 57 (strictly, the barrier metal layer 58 on the upper portion of the aluminum wiring) is formed in the second groove portion 65. In the trench 66, the uppermost copper wiring 40 is exposed. As a result, the second groove 65 is a connection hole in which the aluminum wiring 57 of the second semiconductor substrate 45 is exposed, and the third groove 66 penetrates the first semiconductor substrate 31 and the first semiconductor substrate. The through-connection hole in which the copper wiring 40 formed in 31 is exposed is used.

  At this point in time, the pixel array manufacturing process has not undergone the processing steps of the on-chip color filter and the on-chip lens, and is incomplete. At the same time, the connection hole formed on the copper wiring 40 and the through-connection hole formed on the aluminum wiring 57 can be processed and formed by extension of the conventional wafer process. On the other hand, the logic circuit 25 is a process up to the uppermost metal wiring that is optimal as a circuit technology, and is not completed. In this manner, since the different types of substrates, which are semi-finished products, are bonded together, the manufacturing cost can be reduced as compared with the case where the different types of finished substrates are bonded.

  Thereafter, as shown in FIG. 12, inter-substrate wiring 68 is formed by forming connection conductors such as copper in the first to third groove portions 64, 65, and 66, for example. In this embodiment, since the second groove portion 65 and the third groove portion 66 are formed from within the first groove portion 64, the connection conductors (substrates) formed in the second groove portion 65 and the third groove portion 66 are formed. The interwiring 68) is electrically connected. Thereby, the copper wiring 40 formed in the multilayer wiring layer 41 of the first semiconductor substrate 31 and the aluminum wiring 57 formed in the multilayer wiring layer 55 of the second semiconductor substrate 45 are electrically connected. At this time, since the barrier metal layer 58 is formed on the aluminum wiring 57 formed in the multilayer wiring layer 55 of the second semiconductor substrate 45, even when the inter-substrate wiring 68 is formed of copper, Diffusion is prevented. In addition, an insulating layer 67 is formed in a portion of the second groove portion 65 and the third groove portion 66 that penetrates the first semiconductor substrate 31. For this reason, the inter-substrate wiring 68 and the first semiconductor substrate 31 are not electrically connected. Further, in the present embodiment example, the inter-substrate wiring 68 is formed in the region of the insulating spacer layer 42 formed on the first semiconductor substrate 31, so that the inter-substrate wiring 68 and the first semiconductor are also formed. The substrate 31 is prevented from being electrically connected.

  In the formation process of the inter-substrate wiring 68 according to the present embodiment, the first to third groove portions 64, 65, 66 are formed in three stages and the damascene method in which copper is embedded is used. Not. An inter-substrate wiring 68 is formed in which the copper wiring 40 of the multilayer wiring layer 41 above the first semiconductor substrate 31 and the aluminum wiring 57 of the multilayer wiring layer 55 above the second semiconductor substrate 45 are electrically connected. For example, various modifications are possible.

  In this embodiment, the insulation between the inter-substrate wiring 68 and the first semiconductor substrate 31 is performed by the insulating layer 67 and the insulating spacer layer 42. However, an example in which one of them is configured may be used. . When the insulating spacer layer 42 is not formed, a region corresponding to the insulating spacer layer 42 is not necessary, so that the pixel area can be reduced and the photodiode (PD) area can be increased.

  Next, as shown in FIG. 13, a cap film 72 is formed so as to cover the upper part of the inter-substrate wiring 68. The cap film 72 can be formed, for example, by forming a SiN film or a SiCN film with a thickness of 10 to 150 nm. Thereafter, an opening is formed in the insulating film 62 above the photodiode (PD), and a waveguide material film 69 is formed in a desired region including the opening. For example, SiN can be used as the waveguide material film 69, and the waveguide material 70 is formed by the waveguide material film 69 formed in the opening. By forming the waveguide 70, the light incident from the back side of the first semiconductor substrate 31 is efficiently condensed on the photodiode (PD). Thereafter, a planarizing film 71 is formed on the entire surface including the waveguide material film 69.

  In this embodiment, the cap film 72 and the waveguide material film 69 on the cap film 72 are separately formed in separate steps. However, the waveguide material film 69 may be used as the cap film 72. In this embodiment, the waveguide 70 is formed on the light incident surface side of the photodiode (PD). However, the waveguide 70 may not be formed. Furthermore, in this embodiment, the inter-substrate wiring 68 is formed after the light shielding film 63 is formed. However, before the light shielding film 63 is formed, the through-connection hole and the connection hole are formed, and the inter-substrate wiring 68 is formed. It is good also as an example to form. In that case, the light shielding film 63 also serves as a cap film for the inter-substrate wiring 68 by covering the upper portion of the inter-substrate wiring 68 with the light shielding film 63. In such a configuration, the number of manufacturing steps can be reduced.

  Next, as shown in FIG. 14, on-chip color filters 73 of, for example, red (R), green (G), and blue (B) are formed on the planarizing film 71 corresponding to each pixel. The on-chip color filter 73 can be formed on a photodiode (PD) constituting a desired pixel array by depositing and patterning an organic film containing a pigment or dye of a desired color. Thereafter, an on-chip lens material 74 a is formed on the pixel array region including the upper part of the on-chip color filter 73. As the on-chip lens material 74a, for example, an organic film or an inorganic film such as SiO, SiN, or SiON can be used, and the film is formed to 3000 nm to 4500 nm.

Next, as shown in FIG. 15, an on-chip lens resist film 75 is formed to a thickness of, for example, 300 nm to 1000 nm in an area corresponding to each pixel on the on-chip lens material 74a, and an etching process is performed. Thereby, the shape of the resist film 75 for the on-chip lens is transferred to the on-chip lens material 74a, and the on-chip lens 74 is formed above each pixel as shown in FIG. Thereafter, an oxide film such as the insulating film 62 formed on the first semiconductor substrate 31 is etched by CF ₄ gas (flow rate: 10 to 200 sccm) to expose the first semiconductor substrate 31.

  Next, as shown in FIG. 17, a resist film 76 in which the electrode pad portion 78 of FIG. 3 is opened is formed on the on-chip lens 74. As shown in FIG. 17, the resist film 76 is formed so that the opening end portion is closer to the pixel side than the end portion of the on-chip lens 74.

Next, an etching process is performed under desired etching conditions using the resist film 76 as a mask. As a result, as shown in FIG. 18, the first semiconductor substrate 31 is etched from the side of the first semiconductor substrate 31 which is the uppermost substrate, and the first semiconductor substrate 31 and the second semiconductor substrate 45 are joined. A through opening 77 penetrating the surface is formed. Then, the through opening 77 is formed until the aluminum wiring 57 formed in the multilayer wiring layer 55 of the second semiconductor substrate 45 which is the lowermost substrate is exposed. In this etching step, for example, SF ₆ / O ₂ -based gas (flow rates are SF ₆ : 50 to 500 sccm, O ₂ : 10 to 300 sccm) and etching is performed for 1 to 60 minutes, whereby the first semiconductor is processed. The substrate 31 can be removed by etching. After that, the oxide film or the like up to the aluminum wiring 57 can be removed by etching using a CF ₄ gas (flow rate: 10 to 150 sccm) for 1 to 100 minutes.

  The aluminum wiring 57 exposed in this way is used as an electrode pad portion 78 used when connecting to an external wiring. Hereinafter, the exposed aluminum wiring 57 is referred to as an electrode pad portion 78. It is preferable that a plurality of electrode pad portions 78 are formed on three or four sides outside the pixel region formed on each chip.

  A stacked body 81a formed by stacking two semiconductor substrates as shown in FIG. 18 is then divided into respective chip portions by dicing, whereby the solid-state imaging device of the present embodiment example 81 is completed. By the way, in this embodiment example, when the electrode pad portion 78 is opened, a groove portion used for crack stop at the time of chip division can be formed.

  FIG. 19A is a schematic configuration diagram of a stacked body 81a composed of the first semiconductor substrate 31 and the second semiconductor substrate 45 before the chip division, and FIG. 19B is an enlarged view of the chip portion 91 shown in the region a of FIG. 19A. Indicates. 20 is a schematic cross-sectional configuration along the line xx in FIG. 19B, and shows an electrode pad portion 78 formed on one chip portion 91 and a scribe line Ls adjacent to the electrode pad portion 78. Indicates the area to include.

  As shown in FIG. 19B, the plurality of chip portions 91 formed on the first semiconductor substrate 31 (second semiconductor substrate 45) are separated by a scribe line Ls indicated by a solid line. In this embodiment, as shown in FIG. 20, a groove portion 89 is formed at the same time as the opening process for exposing the electrode pad portion 78 on both sides of the scribe line Ls in the region between the chips. The groove 89 functions as a crack stop s.

  In this embodiment, as shown in FIG. 20, groove portions 89 serving as crack stops s are formed on both sides of the scribe line Ls, and the dicing blade 90 divides the scribe line Ls. Thereby, it is possible to prevent a crack from propagating at the time of dicing on a fragile surface such as a bonding surface between the first semiconductor substrate 31 and the second semiconductor substrate 45. Thereby, it becomes possible to prevent a crack from occurring in the chip portion 91 when the chip is divided.

  As shown in FIG. 3, each of the divided chip portions 91 can be connected to an electrode pad portion 78 with a bonding wire 79, and can be connected to an external wiring of the mounting substrate by the bonding wire 79. Then, the external wiring is electrically connected to the electrode pad portion 78, so that the multilayer wiring layers 41 and 55 of the first semiconductor substrate 31 and the second semiconductor substrate 45 connected by the inter-substrate wiring 68 are connected. Are also electrically connected.

  In the solid-state imaging device according to the first embodiment, the bonding wire 79 is connected to the electrode pad portion 78. However, the solder pad can be used to connect the electrode pad portion 78 and the external wiring. A bonding wire or a solder bump can be selected according to the user's request.

  In the first embodiment, the inspection for the solid-state imaging device on the semiconductor wafer is performed using the electrode pad portion 78. The inspection is performed twice, that is, inspection in a wafer state and inspection in a final module state after cutting into chips.

  According to the solid-state imaging device and the manufacturing method thereof according to the first embodiment, the pixel region 23 and the control circuit 24 are formed in the chip portion from the first semiconductor substrate 31 and the chip portion from the second semiconductor substrate 45 is formed. A logic circuit 25 for signal processing is formed. As described above, since the pixel array function and the logic function are formed in different chip portions, an optimum process forming technique can be used for each of the pixel array and the logic circuit. Therefore, the performance of each of the pixel array and the logic circuit can be sufficiently exhibited, and a high-performance solid-state imaging device can be provided.

  If the configuration of FIG. 2C is adopted, it is only necessary to form a pixel region 23 that receives light on the semiconductor chip portion 22 side, and the control circuit 24 and the logic circuit 25 are separated and formed in the second semiconductor chip portion 26. can do. As a result, the optimum process technology for each functional chip can be selected independently, and the area of the product module can be reduced.

  Since the pixel array and the logic circuit can be mixedly mounted by the conventional wafer process technology, manufacturing is also easy.

  In this embodiment, the first semiconductor substrate 31 having the pixel region 23 and the control circuit 24 and the second semiconductor substrate 45 having the logic circuit 25 are bonded together in a semi-finished state, and the first semiconductor substrate 31 is thinned. That is, the second semiconductor substrate 45 is used as a support substrate when the first semiconductor substrate 31 is thinned. As a result, the members can be saved and the manufacturing process can be saved. Furthermore, since the through-connection hole (second groove portion 65) and the connection hole (third groove portion 66) are formed after the thinning, the aspect ratio of the hole is reduced, and a highly accurate connection hole can be formed. . Further, since the inter-substrate wiring 68 is embedded in the through-connection hole and the connection hole having a low aspect ratio, not only a metal material such as tungsten (W) with good coverage but also a metal material such as copper (Cu) with poor coverage is used. Can be used. That is, the connection conductor material is not restricted. Thereby, the electrical connection between the pixel region and the control circuit and the logic circuit can be performed with high accuracy. Therefore, it is possible to manufacture a high-performance solid-state imaging device while achieving mass productivity, suppressing manufacturing costs.

  Further, in the present embodiment, the through opening 77 formed to open the electrode pad portion 78 is formed so as to penetrate the first semiconductor substrate 31 and the second semiconductor substrate 45 and the bonding surface. The pad portion 78 is constituted by the wiring of the second semiconductor substrate 45 in the lower layer. As a result, the electrode pad portion 78 is formed below the bonding surface that is a fragile surface between the first semiconductor substrate 31 and the second semiconductor substrate 45. For this reason, for example, when the bonding wire 79 is pressed against the electrode pad portion 78, it is possible to reduce the bonding stress applied to the bonding surface which is a fragile surface. Thereby, at the time of wire bonding, it can prevent that a crack generate | occur | produces from a weak joint surface (in this embodiment example, the joint surface of the 1st semiconductor substrate 31 and the 2nd semiconductor substrate 45).

  In the present embodiment, an example in which two layers of semiconductor wafers are stacked is used, but the present invention can be applied to a configuration in which two or more layers are stacked. In that case, a through opening is formed so that the wiring constituting the wiring layer of the lowermost semiconductor wafer is exposed, and the opened wiring is used as a wiring pad portion. Thereby, when connecting an external wiring and an electrode pad part, it can reduce that a stress generate | occur | produces on the weak joint surface between board | substrates.

  Further, as in the present embodiment example, in the backside illumination type solid-state imaging device, it is necessary to bring the photodiode serving as the light receiving portion closer to the circuit, and thus the semiconductor layer as described above must be thinned. Yes. Further, it is preferable that the opening for exposing the wiring below the bonding surface is shallower. Accordingly, when the upper semiconductor substrate (in this embodiment example, the first semiconductor substrate) is a solid-state imaging device having a pixel array as in this embodiment example, the first semiconductor layer is thinned. It is preferable to open the electrode pad portion from the semiconductor substrate side.

<3. Second Embodiment>
FIG. 21 is a schematic configuration diagram of a solid-state imaging device according to the second embodiment of the present invention. FIG. 21 is a schematic cross-sectional configuration diagram of a range including a region where a pad portion is formed, as in FIG. 3. The solid-state imaging device 82 according to the present embodiment forms a pixel region and a control circuit on the first semiconductor substrate 31 side and a second semiconductor substrate 45 side by forming an inter-substrate wiring 80 formed of one connection hole. This is an example in which a logic circuit is electrically connected. In FIG. 21, parts corresponding to those in FIG.

  In the present embodiment example, the inter-substrate wiring 80 that electrically connects the first semiconductor substrate 31 and the second semiconductor substrate 45 penetrates the first semiconductor substrate 31 from the back surface side of the first semiconductor substrate 31. Thus, it reaches the uppermost aluminum wiring 57 of the second semiconductor substrate 45. Further, the inter-substrate wiring 80 partially reaches the copper wiring 40 of the first semiconductor substrate 31. In this embodiment, after forming an insulating film on the inner wall surface of the connection hole, the inter-substrate wiring 80 for connecting the wiring on the pixel region and the control circuit side to the wiring on the logic circuit side by embedding a conductor in the connection hole. Form.

  In this embodiment, the light shielding film 63 is formed in a process after the inter-substrate wiring 80 is formed. In this case, after the inter-substrate wiring 80 is formed, the cap film 72 is formed on the inter-substrate wiring 80, and then the light shielding film 63 is formed.

  In the solid-state imaging device according to the present embodiment, the pixel area, the control circuit, and the logic circuit are electrically connected by one inter-substrate wiring 80. For this reason, compared with 1st Embodiment, while a structure is simplified, a manufacturing man-hour is also reduced. Therefore, the manufacturing cost can be further reduced. In addition, the same effects as those of the first embodiment are obtained.

  In the solid-state imaging device according to the above-described embodiment, the signal charge is an electron, the first conductivity type is a p-type, and the second conductivity type is an n-type, but the signal charge is a hole. It can also be applied to. In this case, the conductivity type of each semiconductor substrate, semiconductor well region or semiconductor region is reversed, n-type being the first conductivity type and p-type being the second conductivity type.

  In the first embodiment described above, the MOS type solid-state imaging device is taken as an example, but the present invention can also be applied to a semiconductor device. Next, a semiconductor device having a structure in which different types of chips are stacked will be described as a second embodiment of the present invention.

<4. Third Embodiment>
[Configuration example of semiconductor device and manufacturing method thereof]
A semiconductor device according to the third embodiment of the present invention will be described together with a manufacturing method thereof with reference to FIGS. 22 and 23 to 28. The semiconductor device 140 according to the present embodiment is configured by stacking a first semiconductor substrate 101 on which a first semiconductor integrated circuit is formed and a second semiconductor substrate 102 on which a second semiconductor integrated circuit is formed. It is a semiconductor device. In FIG. 22, parts corresponding to those in FIG.

  In the third embodiment, first, as shown in FIG. 23, the first semiconductor integrated circuit in the semi-finished state, in this example, is formed in each chip portion of the first semiconductor substrate (semiconductor wafer) 101. A logic circuit is formed. That is, a plurality of MOS transistors Tr9, Tr10, and Tr11 are formed in regions to be the chip portions of the semiconductor well region 108 formed on the first semiconductor substrate 101 made of a silicon substrate. Each of the MOS transistors Tr9 to Tr11 includes a pair of source / drain regions 105 and a gate electrode 106 formed via a gate insulating film. The MOS transistors Tr9 to Tr11 are isolated by the element isolation region 100.

  Although a plurality of MOS transistors are formed, in FIG. 23, the MOS transistors Tr9 to Tr11 are shown as representatives. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors Tr9 to Tr11 can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when an n-channel MOS transistor is formed, n-type source / drain regions are formed in the p-type semiconductor well region 108. When forming a p-channel MOS transistor, p-type source / drain regions are formed in the n-type semiconductor well region.

  The first semiconductor integrated circuit may be a semiconductor memory circuit, for example, instead of the logic circuit. In this case, a logic circuit serving as a second semiconductor integrated circuit described later is used for signal processing of the semiconductor memory circuit.

  In addition, after the formation of the second insulating thin film 43b, an insulating spacer layer 113 that separates a desired region in the semiconductor well region 108 of the first semiconductor substrate 101 is formed as in the first embodiment. The insulating spacer layer 113 is formed by opening a desired position of the first semiconductor substrate 101 from the back surface side and embedding an insulating material after the second insulating thin film 43b is formed. This insulating spacer layer 113 is formed in a region surrounding the inter-substrate wiring 115 in FIG.

  Next, a multilayer wiring layer 107 in which a plurality of layers, in this example, three layers of copper wirings 104 are stacked is formed on the first semiconductor substrate 101 with an interlayer insulating film 103 interposed therebetween. In the present embodiment, the wiring constituting the multilayer wiring layer 107 is made of copper, but the metal wiring can be made of other metal materials. These multilayer wiring layers 107 can be formed in the same manner as in the first embodiment. Each MOS transistor Tr9 to Tr11 is connected to a required first-layer copper wiring 104 via a connection conductor 112. Further, the three layers of copper wiring 104 are connected to each other through a connection conductor 112.

  On the other hand, as shown in FIG. 24, a second semiconductor integrated circuit in a semi-finished state, in this example, a logic circuit, is formed in a region to be each chip portion of the second semiconductor substrate (semiconductor wafer) 102. That is, as in FIG. 23, a plurality of MOS transistors Tr12, Tr13, and Tr14 are formed in regions to be the chip portions of the semiconductor well region 116 formed in the second semiconductor substrate 102 made of silicon. Each of the MOS transistors Tr12 to Tr14 includes a pair of source / drain regions 117 and a gate electrode 118 formed through a gate insulating film. Further, the MOS transistors Tr12 to Tr14 are separated by an element isolation region 127.

  Although a plurality of MOS transistors are formed, in FIG. 24, the MOS transistors Tr12 to Tr14 are shown as representatives. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when an n-channel MOS transistor is formed, n-type source / drain regions are formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, p-type source / drain regions are formed in the n-type semiconductor well region.

  Next, a multilayer wiring layer 124 in which a plurality of layers, in this example, four layers of metal wirings, are stacked on the second semiconductor substrate 102 with an interlayer insulating film 119 interposed therebetween. In this embodiment, an example in which three layers of copper wiring 120 and one layer of aluminum wiring 121 formed in the uppermost layer is formed. Each MOS transistor Tr12 to Tr14 is connected to a required first-layer copper wiring 120 via a connection conductor 126. Further, the three-layer copper wiring 120 and the aluminum wiring 121 are connected to each other by a connection conductor 126. Furthermore, also in this embodiment, barrier metal layers 129 and 130 are formed above and below the aluminum wiring 121, and the aluminum wiring 121 is connected to the lower copper wiring 120 through the lower barrier metal layer 129. Has been. The multilayer wiring layer 124 can be formed in the same manner as the multilayer wiring layer of the first embodiment.

  Then, a stress correction film 123 for reducing stress when the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded is formed on the multilayer wiring layer 124. The stress correction film 123 can also be formed in the same manner as in the first embodiment.

  Next, as shown in FIG. 25, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded so that the multilayer wiring layers 107 and 124 face each other. The bonding is performed with an adhesive, for example. In the case of bonding with an adhesive, an adhesive layer 125 is formed on one side of the bonding surface of the first semiconductor substrate 101 or the second semiconductor substrate 102, and the adhesive layer 125 is overlapped via the adhesive layer 125. Join them together. In the present embodiment example, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded to each other via the adhesive layer 125, but other examples may be bonded by plasma bonding. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surface between the first semiconductor substrate 101 and the second semiconductor substrate 102, respectively. The joining surface on which this film is formed is overlapped by plasma treatment, and then annealed to join them together. The bonding process is preferably performed by a low-temperature process of 400 ° C. or lower that does not affect the wiring or the like. Then, the first semiconductor substrate 101 and the second semiconductor substrate 102 are stacked and bonded to each other, so that a stacked body 140a including two different substrates is formed.

  Next, as shown in FIG. 26, one first semiconductor substrate 101 is thinned by grinding and polishing from the back surface side. When the thickness of the first semiconductor substrate 101 is, for example, about 600 μm, the first semiconductor substrate 101 is thinned so that the film thickness is, for example, about 5-10 μm.

  Next, as shown in FIG. 27, after thinning, the through connection holes and the connection holes formed in the insulating spacer layer 113 are insulated by the same steps as in FIGS. 8 to 12 in the first embodiment. Inter-substrate wiring 115 is formed through layer 114. Also in the present embodiment example, the through-connection hole and the connection hole are formed after the first semiconductor substrate 101 is thinned, so that the aspect ratio becomes small and can be formed as a fine hole. The circuit formed on the first semiconductor substrate 101 and the circuit formed on the second semiconductor substrate 102 are electrically connected by the inter-substrate wiring 115. Thereafter, as in the first embodiment, a cap film 72 is formed on the entire surface including the upper portion of the inter-substrate wiring 115.

  Next, as shown in FIG. 28, a resist film 143 in which the electrode pad portion 142 of FIG. 22 is opened is formed. Then, by using the resist film 143 as a mask, a through opening 132 penetrating the first semiconductor substrate 101 is formed by etching, and the aluminum wiring 121 is exposed. Then, an electrode pad portion 142 made of the exposed aluminum wiring 121 is formed. Also in the present embodiment example, as shown in FIG. 20, the through opening 132 is formed, and at the same time, a groove portion serving as a crack stop is formed on both sides of the scribe line. Thereafter, the semiconductor device 140 according to the present embodiment shown in FIG. 22 is completed by dicing to divide each chip portion.

  As shown in FIG. 22, each of the divided chips can be connected to an electrode pad 142 with a bonding wire 131, and can be connected to an external wiring of the mounting substrate by the bonding wire 131. Then, the external wiring is electrically connected to the electrode pad portion 142, so that the multilayer wiring layers 107 and 124 of the first semiconductor substrate 101 and the second semiconductor substrate 102 connected by the inter-substrate wiring 115 and Are also electrically connected.

  According to the semiconductor device 140 and the manufacturing method thereof according to the third embodiment, the first semiconductor integrated circuit and the second semiconductor integrated circuit are respectively formed in different chip portions by the optimum process technology as described above. And a high-performance semiconductor integrated circuit can be provided. In addition, the first and second semiconductor wafers are bonded and thinned in the semi-finished product state, and after the electrical connection of the first and second semiconductor integrated circuits, the finished product state is formed into a chip, thereby reducing the manufacturing cost. Reduction can be achieved.

  In addition, the same effects as those of the first embodiment can be obtained.

<5. Fourth Embodiment>
[Configuration example of electronic equipment]
The above-described solid-state imaging device of the present invention can be applied to electronic devices such as a camera system such as a digital camera and a video camera, a mobile phone having an imaging function, or other devices having an imaging function.

  FIG. 29 shows a schematic configuration diagram of an electronic apparatus according to the fourth embodiment of the present invention. FIG. 29 shows a camera 200 as an example of the electronic apparatus of the present invention. The camera 200 according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 200 according to the present embodiment includes a solid-state imaging device 203, an optical system 201 that guides incident light to a photoelectric conversion unit that includes a photodiode of the solid-state imaging device 203, and a shutter device 202. Furthermore, the camera 200 includes a drive circuit 205 that drives the solid-state imaging device 203 and a signal processing circuit 204 that processes an output signal of the solid-state imaging device 203.

  As the solid-state imaging device 203, any of the solid-state imaging devices in the first or second embodiment described above is applied. The optical system (optical lens) 201 forms image light (incident light) from a subject on the imaging surface of the solid-state imaging device 203. Thereby, signal charges are accumulated in the solid-state imaging device 203 for a certain period. The optical system 201 may be an optical lens system including a plurality of optical lenses. The shutter device 202 controls a light irradiation period and a light shielding period for the solid-state imaging device 203. The drive circuit 205 supplies a drive signal that controls the transfer operation of the solid-state imaging device 203 and the shutter operation of the shutter device 202. Signal transfer of the solid-state imaging device 203 is performed by a drive signal (timing signal) supplied from the drive circuit 205. The signal processing circuit 204 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  According to the electronic apparatus such as the camera 200 according to the fourth embodiment, the solid-state imaging device 203 can be improved in performance and the manufacturing cost can be reduced. For this reason, in this embodiment, an inexpensive and highly reliable electronic device can be provided.

  21 .. MOS type solid-state imaging device, 22... First semiconductor chip portion, 23... Pixel array, 24... Control circuit, 25. MOS solid-state imaging device, 30... Unit pixel, 31... First semiconductor substrate, 31 b .. back surface, 32... Semiconductor well region, 33... Source / drain region, 34. ..P-type semiconductor region 36..Gate electrode 38..Element isolation region 39..Interlayer insulating film 40..Copper wiring 41..Multilayer wiring layer 42..Insulating spacer layer 43a .. First insulating thin film, 43b, second insulating thin film, 44, connection conductor, 45, second semiconductor substrate, 46, semiconductor well region, 47, source / drain region, 48, gate electrode, 49 ..Interlayer insulating films, 50 Separation area, 53 ... Copper wiring, 54 ... Connection conductor, 55 ... Multi-layer wiring layer, 56 ... Barrier metal layer, 57 ... Aluminum wiring, 58 ... Barrier metal layer, 59 ... Stress compensation film, 60 ..Adhesive layer 61..Antireflection film 62..Insulating film 63..Light-shielding film 64..First groove portion 65..Second groove portion 66..Third groove portion 67 ..Insulating layer 68..Inter-substrate wiring 69..Waveguide material film 70..Waveguide 71..Planarizing film 72..Cap film 73..On-chip color filter 74 .. On-chip lens, 74a .. On-chip lens material, 75 .. Resist film, 76 .. Resist film, 77 .. Through opening, 78 .. Electrode pad part, 79.

Claims (22)

A first semiconductor substrate on which a first semiconductor integrated circuit is formed and comprising a first wiring layer;
A second semiconductor substrate on which a second semiconductor integrated circuit is formed and comprising a second wiring layer;
An inter-substrate wiring that is provided through the second wiring layer from above the first semiconductor substrate and electrically connects the first semiconductor substrate and the second semiconductor substrate;
A through opening formed through the first semiconductor substrate such that an electrode pad formed in the second wiring layer is exposed from the first semiconductor substrate;
A groove portion that is formed on at least the first semiconductor substrate and serves as a crack stop that prevents a crack from occurring in the chip portion when the chip is divided;
The first semiconductor substrate and the second semiconductor substrate are bonded so that the first wiring layer side and the second wiring layer side face each other;
The groove serving as the crack stop is formed so as to penetrate the first semiconductor substrate. The semiconductor device according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate are bonded together via an adhesive layer. The semiconductor device according to claim 1, wherein the wiring of the second wiring layer connected to the inter-substrate wiring is an aluminum wiring. The semiconductor device according to claim 1, wherein the first wiring layer includes a copper wiring, and the inter-substrate wiring is formed of copper. The semiconductor device according to claim 1, wherein a stress correction film is formed between the first semiconductor substrate and the second semiconductor substrate. The semiconductor device according to claim 1, wherein the second semiconductor integrated circuit is a logic circuit. The wiring of the second wiring layer connected to the inter-substrate wiring is continuously formed from a partial region where the logic circuit is formed to a region corresponding to the through opening. A semiconductor device according to 1. The first semiconductor substrate and the second semiconductor substrate are bonded together by plasma bonding.
The semiconductor device according to claim 1 . The semiconductor device according to claim 1, wherein the electrode pad portion is formed of a wiring that is closest to the first semiconductor substrate in the second wiring layer. The semiconductor device according to claim 1, wherein the first semiconductor integrated circuit is a semiconductor memory circuit. The semiconductor device according to claim 1, wherein the second wiring layer has a copper wiring. A first semiconductor substrate on which a first semiconductor integrated circuit is formed and provided with a first wiring layer; and a second semiconductor substrate on which a second semiconductor integrated circuit is formed and provided with a second wiring layer. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first wiring layer side and the second wiring layer side face each other,
By forming a through hole penetrating from the upper part of the first semiconductor substrate into the second wiring layer and embedding a metal material in the through hole, the first semiconductor substrate and the second semiconductor substrate are formed. Form inter-board wiring that connects electrically,
Forming a through-opening that penetrates the first semiconductor substrate so that the electrode pad formed in the second wiring layer is exposed;
A method for manufacturing a semiconductor device, comprising: forming a groove portion serving as a crack stop to prevent cracks from occurring in a chip portion at the time of chip division in at least the first semiconductor substrate so as to penetrate the first semiconductor substrate. The method for manufacturing a semiconductor device according to claim 12, wherein the first semiconductor substrate and the second semiconductor substrate are bonded together via an adhesive layer. The method for manufacturing a semiconductor device according to claim 12, wherein the wiring of the second wiring layer connected to the inter-substrate wiring is formed of aluminum. The method for manufacturing a semiconductor device according to claim 12, wherein the first wiring layer and the inter-substrate wiring are formed of copper. The method for manufacturing a semiconductor device according to claim 12, wherein a stress correction film is formed between the first semiconductor substrate and the second semiconductor substrate. The wiring of the second wiring layer connected to the inter-substrate wiring is continuously formed from a part of the region where the second semiconductor integrated circuit is formed to a region corresponding to the through opening. Item 17. A method for manufacturing a semiconductor device according to any one of Items 12 to 16. The method of manufacturing a semiconductor device according to claim 12, wherein an insulating film is formed on a side wall of the through hole before the metal material is embedded. The first semiconductor substrate and the second semiconductor substrate are bonded together by plasma bonding.
19. A method for manufacturing a semiconductor device according to claim 12, 14 to 18. 20. The method of manufacturing a semiconductor device according to claim 12, wherein the electrode pad portion is formed of a wiring closest to the first semiconductor substrate in the second wiring layer. The method for manufacturing a semiconductor device according to claim 12, wherein the first semiconductor integrated circuit is a semiconductor memory circuit. The method for manufacturing a semiconductor device according to claim 12, wherein the second semiconductor integrated circuit is a logic circuit.