JP2020129672A - Solid state image sensor and electronic apparatus - Google Patents

Abstract

To provide a high performance solid state image sensor in which the performance each of laminated semiconductor wafers is exhibited sufficiently, while achieving mass production and cost reduction.SOLUTION: A solid state image sensor includes a first semiconductor wafer including a first wiring layer provided on the opposite side to the light incident surface and on which a pixel array is formed, a second semiconductor wafer stuck on the first semiconductor wafer and on which a second wiring layer is formed, a through connection hole penetrating the first semiconductor wafer, and reaching the second wiring layer, a groove provided on the light incident surface side in the first semiconductor wafer, and a conductive material formed in a region including the through connection hole and the groove, where the conductive material connects the first and second wiring layers electrically.SELECTED DRAWING: Figure 4

Description

The present invention relates to a solid-state imaging device and an electronic device including the solid-state imaging device.

As a solid-state image pickup device, an amplification type solid-state image pickup device represented by a MOS type image sensor such as CMOS (Complementary Metal Oxide Semiconductor) is known. Further, a charge transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor is known. These solid-state imaging devices are widely used in digital still cameras, digital video cameras and the like. In recent years, a MOS image sensor has been widely used as a solid-state imaging device mounted on a mobile device such as a mobile phone with a camera or a PDA (Personal Digital Assistant) because of its low power supply voltage and power consumption.

The MOS type solid-state imaging device includes a pixel array (pixel region) in which a unit pixel is formed of a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors, and the plurality of unit pixels are arranged in a two-dimensional array. It is configured to have a circuit area. The plurality of pixel transistors are formed of MOS transistors, and are composed of transfer transistors, reset transistors, three transistors of amplification and transistors, or four transistors including selection transistors.

Conventionally, in such a MOS type solid-state imaging device, a semiconductor chip in which a pixel region in which a plurality of pixels are arranged is formed and a semiconductor chip in which a logic circuit for performing signal processing is formed are electrically connected to each other. Various solid-state imaging devices configured as devices have been proposed. For example, Patent Document 1 discloses a semiconductor module in which a backside illuminated image sensor chip having a micropad for each pixel cell and a signal processing chip having a micropad in which a signal processing circuit is formed are connected by microbumps. Has been done.

In Patent Document 2, a sensor chip, which is a back-illuminated MOS solid-state imaging device provided with an imaging pixel section, and a signal processing chip provided with a peripheral circuit for performing signal processing are mounted on an interposer (intermediate substrate). A device is disclosed. Patent Document 3 has a configuration including an image sensor chip, a thin circuit board, and a logic circuit chip that performs signal processing. Then, a configuration is disclosed in which the thin film circuit board and the logic circuit chip are electrically connected, and the thin film circuit board is electrically connected from the back surface of the image sensor chip through a through hole via.

Further, Patent Document 4 discloses a solid-state imaging device in which a through-electrode is provided in a solid-state imaging device supported by a transparent substrate, and the solid-state imaging device is electrically connected to a flexible circuit board via the through-electrode. Further, Patent Document 5 discloses a configuration in which an electrode penetrating a supporting substrate is provided in a backside illumination type solid-state imaging device.

As shown in Patent Documents 1 to 3, various technologies for mounting an image sensor chip and a heterogeneous circuit chip such as a logic circuit together have been proposed. In the prior art, all of the functional chips are in a completed state, through-holes are formed, and chips are formed on one chip in a state where interconnection between chips stacked one above the other is possible. Is a feature.

JP, 2006-49361, A JP, 2007-13089, A JP, 2008-130603, A Japanese Patent No. 4500507 JP, 2003-31785, A

As seen in the above-described conventional solid-state imaging device, it has been known as an idea to connect different types of chips stacked by connecting conductors penetrating a substrate to form a semiconductor device. However, the connection hole must be opened while ensuring insulation in a deep substrate, and it has been difficult to put it into practical use due to the cost economy of the manufacturing process required for processing the connection hole and embedding the connection conductor.

On the other hand, in order to form a small contact hole of, for example, about 1 μm, it is necessary to make the upper chip as thin as possible. In this case, a complicated process such as attaching the upper chip to the support substrate before thinning and an increase in cost are caused. Moreover, in order to fill the connection hole with a high aspect ratio with the connection conductor, it is inevitably required to use a CVD film having a good covering property such as tungsten (W) as the connection conductor, and the connection conductor material is restricted.

In order to have economical efficiency that can be easily applied in mass production, the aspect ratio of this connection hole is dramatically reduced to facilitate formation, and it is processed in the conventional wafer manufacturing process without using special connection hole processing. It is desirable to be able to select the technology that can. At this time, the contact hole connecting to the upper chip and the contact hole penetrating the upper chip and reaching the lower chip have different depths, but it is required that they can be formed by the same etching process or metal filling process as much as possible. ing.

Further, in a solid-state imaging device or the like, it is desired that the image area and the logic circuit that performs signal processing are formed so as to sufficiently exhibit their respective performances, and thus high performance is desired.
It is desired that not only the solid-state imaging device but also a semiconductor device having another semiconductor integrated circuit is formed so that the performance of each semiconductor integrated circuit can be sufficiently exerted, and high performance can be achieved.

However, if the upper and lower chips are designed so as to have the necessary functions, the circuit areas of the portions having the common functions will overlap, and the chip size will increase, making it difficult to reduce costs. For this reason, at least in order to reduce the cost, it is desirable to design the structure so that the areas of the upper and lower chips having the same function can be used in common as much as possible.

In view of the above points, the present invention provides a solid-state image pickup device and a solid-state image pickup device in which the performance of each of the stacked semiconductor wafers is sufficiently exerted to achieve high performance, and mass productivity and cost reduction are achieved. The electronic device provided is provided.

In the solid-state imaging device according to the present invention, a pixel array is formed, a first semiconductor wafer having a first wiring layer provided on the side opposite to the light incident surface, and a second wiring layer are formed. A second semiconductor wafer bonded to the first semiconductor wafer, a through connection hole that penetrates the first semiconductor wafer and reaches the second wiring layer, and a light incident surface side in the first semiconductor wafer And a conductive material formed in a region including the through connection hole and the groove, and the conductive material electrically connects the first wiring layer and the second wiring layer.
Electronic equipment according to the present invention includes the solid-state imaging device according to the present invention.

According to the present invention, a plurality of semiconductor wafers each having a circuit capable of sufficiently exhibiting each performance are laminated by an optimal process technology, so that the semiconductor wafer is excellent in mass productivity, low in cost, and high in cost. A high-performance solid-state imaging device can be obtained.

It is a schematic block diagram which shows an example of the MOS solid-state imaging device applied to this invention. A is a schematic diagram of a conventional solid-state imaging device. B and C are schematic views of the solid-state imaging device according to the embodiment of the present invention. It is a figure which shows an example of the circuit of the pixel structure of the MOS solid-state imaging device applied to this invention. It is a schematic block diagram of the principal part which shows the solid-state imaging device which concerns on 1st Embodiment. FIG. 5 is a manufacturing process diagram (1) illustrating an example of a method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 6 is a manufacturing process diagram (2) illustrating the example of the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 7 is a manufacturing process diagram (3) illustrating the example of the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 6 is a manufacturing process diagram (4) showing the example of the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 7 is a manufacturing process diagram (5) illustrating the example of the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 9 is a manufacturing process diagram (6) illustrating the example of the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 9 is a manufacturing process diagram (7) illustrating the example of the method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 9 is a manufacturing process diagram (8) showing the solid-state imaging device and the manufacturing method thereof according to the first embodiment. FIG. 9 is a manufacturing process diagram (9) showing the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 9 is a manufacturing process diagram (10) showing the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 11 is a manufacturing process diagram (11) showing the method of manufacturing the solid-state imaging device according to the first embodiment. FIG. 12 is a manufacturing process diagram (12) illustrating the method for manufacturing the solid-state imaging device according to the first embodiment. It is manufacturing process drawing (the 13) which shows the manufacturing method of the solid-state imaging device which concerns on 1st Embodiment. FIG. 14 is a manufacturing process diagram (14) illustrating the method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 15 is a manufacturing process diagram (15) illustrating the method for manufacturing the solid-state imaging device according to the first embodiment. It is a schematic cross-sectional block diagram of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. FIG. 9 is a manufacturing process diagram (1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a manufacturing process diagram (2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a manufacturing process diagram (3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a manufacturing process diagram (4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a manufacturing process diagram (5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a manufacturing process diagram (6) illustrating the method for manufacturing the semiconductor device according to the second embodiment. It is a schematic sectional block diagram of the principal part of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. A and B are an example using backside wiring on the backside of the first semiconductor substrate and an example not using it. A and B are a configuration example of a planar layout in which wirings having a common potential are connected between the stacked chips, and a configuration example of a planar layout in which wirings having a common potential are not connected. It is a flow which shows the design method of the solid-state imaging device of the present invention. 3A and 3B are manufacturing process diagrams of an upper chip and a lower chip according to the designing method of the present invention. 3A and 3B are manufacturing process diagrams of an upper chip and a lower chip according to the designing method of the present invention. 3A and 3B are manufacturing process diagrams of an upper chip and a lower chip according to the designing method of the present invention. 3A and 3B are manufacturing process diagrams of an upper chip and a lower chip according to the designing method of the present invention. It is a schematic block diagram which shows the electronic device which concerns on the 4th Embodiment of this invention.

Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. Example of schematic configuration of MOS type solid-state imaging device 1. First Embodiment (Example of Configuration of Back-illuminated Solid-state Imaging Device and Example of Manufacturing Method Thereof)
3. Second Embodiment (Configuration Example of Semiconductor Device and Manufacturing Method Example Thereof)
4. Third embodiment (configuration example of solid-state imaging device and design method thereof)
5. Fourth Embodiment (Configuration Example of Electronic Device)

<1. Schematic configuration example of MOS solid-state imaging device>
FIG. 1 shows a schematic configuration of a MOS type solid-state imaging device applied to the semiconductor device of the present invention. This MOS type solid-state imaging device is applied to the solid-state imaging device of each embodiment. The solid-state imaging device 1 of this example includes a pixel region (so-called pixel array) 3 in which pixels 2 including a plurality of photoelectric conversion units are regularly arranged in a two-dimensional array on a semiconductor substrate (not shown) such as a silicon substrate, and peripheral circuits And a part. The pixel 2 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can be composed of, for example, three transistors including a transfer transistor, a reset transistor, and an amplification transistor. In addition, it is also possible to add four selection transistors to form four transistors. The equivalent circuit of the unit pixel will be described later. The pixel 2 can be configured as one unit pixel, or can have a shared pixel structure in which a plurality of pixels share a transistor. This shared pixel structure is a structure in which a plurality of photodiodes share a floating diffusion forming a transfer transistor and a transistor other than the transfer transistor.

The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8 and the like.

The control circuit 8 receives an input clock and data instructing an operation mode and the like, and outputs data such as internal information of the solid-state imaging device. That is, the control circuit 8 generates a clock signal or a control signal that is a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like, based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. Then, these signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

The vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel to the selected pixel drive wiring, and drives the pixel in row units. In other words, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 sequentially in the vertical direction row by row, and through the vertical signal line 9, a photoelectric conversion unit of each pixel 2, for example, a photodiode, depending on the amount of light received. A pixel signal based on the generated signal charge is supplied to the column signal processing circuit 5.

The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and performs signal processing such as noise removal on the signals output from the pixels 2 for one row for each pixel column. That is, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise unique to the pixel 2, signal amplification, and AD conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 so as to be connected to the horizontal signal line 10.

The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to sequentially select each of the column signal processing circuits 5 and outputs pixel signals from each of the column signal processing circuits 5 to a horizontal signal line. Output to 10.

The output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the processed signals. For example, only buffering may be performed, and black level adjustment, column variation correction, various digital signal processing may be performed. The input/output terminal 12 exchanges signals with the outside.

Next, the structure of the MOS type solid-state imaging device according to this embodiment will be described. FIG. 2A is a schematic configuration diagram showing a structure of a conventional MOS solid-state imaging device, and FIGS. 2B and 2C are schematic configuration diagrams showing a structure of the MOS solid-state imaging device according to the present embodiment.

As shown in FIG. 2A, the conventional MOS solid-state imaging device 151 is configured by mounting a pixel region 153, a control circuit 154, and a logic circuit 155 for signal processing in one semiconductor chip 152. It Usually, the pixel area 153 and the control circuit 154 form an image sensor 156.

On the other hand, in the MOS type solid-state imaging device 21 of the present embodiment example, as shown in FIG. 2B, the pixel region 23 and the control region 24 are mounted on the first semiconductor chip portion 22, and the second semiconductor chip portion is mounted. A logic circuit 25 including a signal processing circuit for performing signal processing is mounted on 26. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected to each other to form the MOS solid-state imaging device 21 as one semiconductor chip.

As shown in FIG. 2C, a MOS solid-state imaging device 27 according to another embodiment of the present invention has a pixel region 23 mounted on a first semiconductor chip portion 22 and a second semiconductor chip portion 26 and a control region. 24, a logic circuit 25 including a signal processing circuit is mounted. The first semiconductor chip unit 22 and the second semiconductor chip unit 26 are electrically connected to each other to form a MOS solid-state imaging device 27 as one semiconductor chip.

FIG. 3 is a circuit diagram showing an example of the circuit configuration of the unit pixel 2. The unit pixel 2 according to the present circuit example is configured to include a photoelectric conversion unit, for example, a photodiode PD and four pixel transistors. The four pixel transistors are, for example, the transfer transistor 11, the reset transistor 13, the amplification transistor 14, and the selection transistor 15. For these pixel transistors, for example, n-channel MOS transistors are used.

The transfer transistor 11 is connected between the cathode of the photodiode PD and the floating diffusion portion 16. The signal charges (here, electrons) photoelectrically converted by the photodiode PD and accumulated therein are transferred to the floating diffusion unit 16 by applying a transfer pulse φTRG to the gate.

The drain of the reset transistor 13 is connected to the power supply VDD, and the source thereof is connected to the floating diffusion portion 16. Then, prior to the transfer of the signal charges from the photodiode PD to the floating diffusion portion 16, the reset pulse φRST is applied to the gate to reset the potential of the floating diffusion portion 16.

For example, the drain of the selection transistor 15 is connected to the power supply VDD, and the source thereof is connected to the drain of the amplification transistor 14. The selection pulse φSEL is applied to the gate of the selection transistor 15 to turn it on, and the power source VDD is supplied to the amplification transistor 14, whereby the pixel 2 can be selected. The selection transistor 15 may be connected between the source of the amplification transistor 14 and the vertical signal line 9.

The amplification transistor 14 has a source follower configuration in which the gate is connected to the floating diffusion section 16, the drain is connected to the source of the selection transistor 15, and the source is connected to the vertical signal line 9. The amplification transistor 14 outputs the potential of the floating diffusion portion 16 after being reset by the reset transistor 13 to the vertical signal line 9 as a reset level. Further, the amplification transistor 14 outputs the potential of the floating diffusion portion 16 after the signal charge is transferred by the transfer transistor 11 to the vertical signal line 9 as a signal level.

In the solid-state imaging device 1 of the present embodiment example, for example, elements such as a photodiode and a plurality of MOS transistors are formed in the first semiconductor chip unit 22 of FIG. 2B or 2C. Further, the transfer pulse, the reset pulse, the selection pulse, and the power supply voltage are supplied from the control area 24 of FIG. 2B or 2C. Further, the elements in the subsequent stage from the vertical signal line 9 connected to the drain of the selection transistor are configured in the logic circuit 25 of FIG. 2B or 2C, and are formed in the second semiconductor chip section 26.

The MOS type solid-state imaging device according to the above-described embodiment has a structure in which different types of semiconductor chips are stacked, and is characterized by its manufacturing method and the structure obtained based on the manufacturing method, as described later. have.
In the embodiments described below, the solid-state imaging device of the present invention and the manufacturing method thereof will be described.

<2. First Embodiment>
[Example of Configuration of Solid-State Imaging Device and Example of Manufacturing Method Thereof]
As a semiconductor device according to the first embodiment of the present invention, a backside illumination type MOS solid-state imaging device will be described with reference to FIGS.

FIG. 4 is a schematic cross-sectional configuration diagram (completed view) including the electrode pad portion 78 of the solid-state imaging device 81 of the present embodiment example. The solid-state imaging device 81 of the present embodiment example includes a first semiconductor chip unit 22 including a pixel array (hereinafter referred to as a pixel region) 23 and a control region 24, and a second semiconductor chip unit on which a logic circuit 25 is mounted. 26 are stacked one above the other in a state of being electrically connected.
A method for manufacturing the solid-state imaging device 81 according to the present embodiment will be described with reference to FIGS.

In the first embodiment, first, as shown in FIG. 5, an image sensor in a semi-finished product state is provided in a region of each chip portion of a first semiconductor wafer (hereinafter referred to as a first semiconductor substrate) 31. That is, the pixel area 23 and the control area 24 are formed. That is, a photodiode (PD) serving as a photoelectric conversion portion of each pixel is formed in a region serving as each chip portion of the first semiconductor substrate 31 made of a silicon substrate, and the source/source of each pixel transistor is formed in the semiconductor well region 32. The drain region 33 is formed. The semiconductor well region 32 is formed by introducing a first conductivity type, for example, p-type impurity, and the source/drain region 33 is formed by introducing a second conductivity type, for example, n-type impurity. The photodiode (PD) and the source/drain region 33 of each pixel transistor are formed by ion implantation from the substrate surface.

The photodiode (PD) is formed having an n-type semiconductor region 34 and a p-type semiconductor region 35 on the substrate surface side. A gate electrode 36 is formed on the surface of a substrate forming a pixel via a gate insulating film, and the source/drain regions 33 paired with the gate electrode 36 form pixel transistors Tr1 and Tr2. In FIG. 5, the plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. The pixel transistor Tr1 adjacent to the photodiode (PD) corresponds to the transfer transistor, and the source/drain region thereof corresponds to the floating diffusion (FD). Each unit pixel 30 is separated by the element separation region 38.

On the other hand, on the control region 24 side, a MOS transistor forming a control circuit is formed on the first semiconductor substrate 31. In FIG. 4, MOS transistors that constitute the control region 24 are shown as representative of the MOS transistors Tr3 and Tr4. Each of the MOS transistors Tr3 and Tr4 is formed of an n-type source/drain region 33 and a gate electrode 36 formed via a gate insulating film.

Next, a first-layer interlayer insulating film 39 is formed on the surface of the first semiconductor substrate 31, then a contact hole is formed in the interlayer insulating film 39, and a connection conductor 44 for connecting to a required transistor is formed. .. When forming the connection conductors 44 having different heights, the first insulating thin film 43a is formed of, for example, a silicon oxide film and the second insulating thin film 43b serving as an etching stopper is formed of, for example, a silicon nitride film on the entire surface including the upper surface of the transistor. And stack. The first interlayer insulating film 39 is formed on the second insulating thin film 43b. The first interlayer insulating film 39 is, for example, a P-SiO film (plasma oxide film) having a film thickness of 10 to 150 nm, and then an NSG (non-doped silicate glass) film or a PSG film (phosphosilicate glass) having a thickness of 50 nm to 1000 nm. To form. After that, a dTEOS film can be formed to a thickness of 100 to 1000 nm, and then a P-SiH4 film (plasma oxide film) can be formed to a thickness of 50 to 200 nm.

After that, contact holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the contact holes are formed by selectively etching the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness in each part so as to be continuous with the contact holes. Then, the connection conductor 44 is embedded in each contact hole.

After forming the second insulating thin film 43b, the insulating spacer layer 42 that separates a desired region in the semiconductor well region 32 of the first semiconductor substrate 31 is formed. The insulating spacer layer 42 is formed by forming a second insulating thin film 43b, opening a desired position of the first semiconductor substrate 31 from the front surface side, and burying an insulating material. The insulating spacer layer 42 is formed in a region surrounding the inter-substrate wiring 68 of FIG.

Next, a plurality of layers, in this example, three layers of copper wirings 40 are formed via the interlayer insulating film 39 so as to be connected to the respective connection conductors 44 to form the first multilayer wiring layer 41. Usually, each copper wiring 40 is covered with a barrier metal layer (not shown) to prevent Cu diffusion. The barrier metal layer can be formed, for example, by depositing a SiN film or a SiC film with a thickness of 10 to 150 nm. The interlayer insulating film 39 from the second layer can be formed by forming a dTEOS film (silicon oxide film formed by a plasma CVD (Chemical Vapor Deposition) method) to a thickness of 100 to 1000 nm. By alternately forming the interlayer insulating film 39 and the copper wiring 40 formed via the barrier metal layer, the first multilayer wiring layer 41 is formed. Although the first multilayer wiring layer 41 is formed of the copper wiring 40 in the present embodiment, it may be a metal wiring made of other metal material.

Through the steps up to this point, the first semiconductor substrate 31 having the first multilayer wiring layer 41 on the upper portion thereof and including the pixel region 23 and the control region 24 in the semi-finished product state is formed.

On the other hand, as shown in FIG. 6, a logic circuit 25 including a signal processing circuit for signal processing of a semi-finished product state is provided in a region which becomes each chip portion of a second semiconductor substrate (semiconductor wafer) 45 made of, for example, silicon. Form. That is, a plurality of MOS transistors forming the logic circuit 25 are formed in the p-type semiconductor well region 46 on the front surface side of the second semiconductor substrate 45 so as to be isolated by the element isolation region 50. Here, the plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, and Tr8. Each of the MOS transistors Tr6, Tr7, Tr8 is formed having a pair of n-type source/drain regions 47 and a gate electrode 48 formed via a gate insulating film. The logic circuit 25 can be composed of CMOS transistors.

Next, a first-layer interlayer insulating film 49 is formed on the surface of the second semiconductor substrate 45, then a contact hole is formed in the interlayer insulating film 49, and a connection conductor 54 for connecting to a required transistor is formed. .. When forming the connection conductors 54 having different heights, the first insulating thin film 43a, for example, a silicon oxide film and the second insulating thin film 43b serving as an etching stopper, for example, a silicon nitride film are formed on the entire surface including the upper surface of the transistor, as described above. Stack. The first interlayer insulating film 49 is formed on the second insulating thin film 43b. Then, contact holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating thin film 43b serving as an etching stopper. Next, the contact holes are formed by selectively etching the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness in each part so as to be continuous with the contact holes. Then, the connection conductor 54 is embedded in each contact hole.

After that, the formation of the interlayer insulating film 49 and the formation of the metal wirings of a plurality of layers are repeated to form the second multilayer wiring layer 55. In this embodiment, three layers of copper wiring 53 are formed in the same manner as the step of forming the first multilayer wiring layer 41 formed on the first semiconductor substrate 31, and then aluminum wiring is formed on the uppermost layer. In this example, 57 is formed. To form the aluminum wiring 57, first, the interlayer insulating film 49 is formed on the uppermost copper wiring 53, and then the interlayer insulating film 49 is removed by etching so that a desired position on the uppermost copper wiring 53 is exposed. , Forming contact holes. Then, a layered film of TiN (lower layer)/Ti (upper layer) that becomes the barrier metal layer 56 is 5 to 10 nm, or a layered film of TaN (lower layer)/Ta (upper layer) is 10 to 10 in a region including the inside of the contact hole. A film is formed at 100 nm. After that, the contact hole is covered to form an aluminum film having a thickness of 500 to 2000 nm, and then patterned into a desired shape to form an aluminum wiring 57. Further, a barrier metal layer 58, which will be required in a later step, is formed on the aluminum wiring 57. This barrier metal layer 58 can also have the same structure as the barrier metal layer 56 formed below the aluminum wiring 57.

Subsequently, the aluminum wiring 57 having the barrier metal layer 58 formed thereon is covered to form an interlayer insulating film 49. As the interlayer insulating film 49 on the aluminum wiring 57, for example, an HDP film (high density plasma oxide film) or a P-SiO film (plasma oxide film) is formed to a thickness of 500 to 2000 nm, and then a P-SiO film is further formed thereon. It can be formed by forming a film with a thickness of 100 to 2000 nm. As described above, the second multilayer wiring layer 55 including the three-layer copper wiring 53 formed via the interlayer insulating film 49 and the aluminum wiring 57 formed in the uppermost layer is formed.

Then, a warp correction film 59 for reducing a warp when the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded is formed on the second multilayer wiring layer 55. The warp correction film 59 can be formed by, for example, forming a P-SiN film or a P-SiON film (plasma oxynitride film) with a thickness of 100 to 2000 nm.

Through the steps up to this point, the second semiconductor substrate 45 having the second multilayer wiring layer 55 on the upper portion and having the logic circuit in the semi-finished product state is formed.

Next, as shown in FIG. 7, the first semiconductor substrate 31 and the second semiconductor substrate 45 are attached so that the first multilayer wiring layer 41 and the second multilayer wiring layer 55 face each other. The bonding is performed with an adhesive, for example. In the case of bonding with an adhesive, the adhesive layer 60 is formed on one side of the bonding surface of the first semiconductor substrate 31 or the second semiconductor substrate 45, and the adhesive layer 60 is overlaid with the adhesive layer 60 interposed therebetween. Join both. In the present embodiment example, the first semiconductor substrate 31 in which the pixel region is formed is arranged in the upper layer, and the second semiconductor substrate 45 is arranged in the lower layer and bonded.

Further, in the present embodiment example, the first multilayer wiring layer 41 on the first semiconductor substrate 31 and the second multilayer wiring layer 55 on the second semiconductor substrate 45 are bonded together via the adhesive layer 60. Although an example is given, another example may be used in which the bonding is performed by plasma bonding. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55, respectively. To do. The bonding surface on which this film is formed is subjected to plasma treatment to be superposed, and then an annealing treatment is performed to bond the two. The bonding process is preferably performed by a low temperature process of 400° C. or lower that does not affect wiring or the like.

Then, the first semiconductor substrate 31 and the second semiconductor substrate 45 having the multi-layered wiring layer on the upper part are laminated and adhered to each other, thereby forming a laminated body 81a composed of two different substrates.

Next, as shown in FIG. 8, the first semiconductor substrate 31 is thinned by grinding and polishing from the back surface side of the first semiconductor substrate 31. This thinning is performed so that the photodiode (PD) faces. As the first semiconductor substrate 31, for example, a semiconductor substrate in which a p-type high-concentration impurity layer is formed as an etching stopper layer (not shown) is used. Can be converted. After thinning, a p-type semiconductor layer (not shown) for suppressing dark current is formed on the back surface of the photodiode (PD). The thickness of the first semiconductor substrate 31 is, for example, about 600 μm, but is reduced to about 3 to 5 μm.

Conventionally, such thinning has been performed by bonding a separately prepared support substrate to the first multilayer wiring layer 41 side formed on the first semiconductor substrate 31. However, in the present embodiment, the second semiconductor substrate 45 on which the logic circuit 25 is formed is also used as the support substrate to thin the first semiconductor substrate 31. The back surface of the first semiconductor substrate 31 serves as a light incident surface when configured as a back-illuminated solid-state imaging device.

Next, as shown in FIG. 9, an antireflection film 61 is formed on the back surface of the first semiconductor substrate 31. The antireflection film 61 can add the effect of suppressing dark current by forming TaO2 or HfO2 in a thickness of 5 to 100 nm and performing necessary heat treatment. After that, an insulating film 62 is formed by forming a plasma SiO film on the antireflection film 61 to a thickness of 100 to 1500 nm.

Next, as shown in FIG. 10, a groove 64 is formed in a desired region inside the insulating spacer layer 42, and a light-shielding film groove 82 is formed in a light-shielding region where light shielding is required. The groove portion 64 and the light shielding film groove portion 82 are formed by forming an opening by etching from the upper surface of the insulating film 62 formed on the back surface side of the first semiconductor substrate 31, and do not reach the first semiconductor substrate 31, for example. Form to depth.

Next, as shown in FIG. 11, copper wiring from the desired bottom region of the groove 64 formed inside the insulating spacer layer 42 to the lowermost layer (uppermost in FIG. 11) of the first multilayer wiring layer 41. The connection hole 66 is formed by opening to a depth immediately before reaching 40.

Similarly, a through connection hole 65 penetrating a bonding surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55 from a desired bottom region of the groove 64 formed inside the insulating spacer layer 42 is formed. Form. This through connection hole 65 is formed by opening to a depth immediately before reaching the uppermost aluminum wiring 57 of the second multilayer wiring layer 55 formed on the second semiconductor substrate 45. At this time, the diameter of the through connection hole 65 is formed to be about 1.5 to 10 times larger than the diameter of the connection hole 66, and more preferably about 3 to 4 times larger.

When the diameter of the through connection hole 65 is smaller than 1.5 times that of the connection hole 66, the aspect ratio of the through connection hole 65 becomes large, and a void is generated when the conductive material is embedded in the hole in a later step. May occur. Further, when the diameter of the through connection hole 65 is larger than 10 times the diameter of the connection hole 66, there is a problem that the area occupied by the through connection hole 65 becomes large and the device cannot be downsized. Therefore, by making the diameter of the through connection hole 65 about 1.5 to 10 times larger than the diameter of the connection hole 66, it is possible to obtain a hole having an optimum aspect ratio for embedding a conductive material and not increasing the layout space. it can.

Since the connection hole 66 and the through connection hole 65 are formed after thinning the first semiconductor substrate 31 (step of FIG. 8 ), the aspect ratio becomes small and it can be formed as a fine hole. Further, the connection hole 66 is opened until just before reaching the lowermost layer of the first multilayer wiring layer 41 on the first semiconductor substrate 31, that is, the copper wiring 40 on the side closest to the first semiconductor substrate 31. Since it is formed as a result, the opening depth becomes shallower, which is advantageous for forming fine holes.

Next, an insulating layer 67 made of, for example, a SiO 2 film is formed in a region including the side wall and the bottom of the connection hole 66 and the through connection hole 65, and then etched back. As a result, as shown in FIG. 12, the insulating layer 67 is left only on the side walls of the connection hole 66 and the through connection hole 65. Then, the bottoms of the connection hole 66 and the through connection hole 65 are further removed by etching. As a result, the lowermost copper wiring 40 of the first multilayer wiring layer 41 is formed in the connection hole 66, and the uppermost aluminum wiring 57 of the second multilayer wiring layer 55 (strictly speaking, in the through connection hole 65). The barrier metal layer 58) on the aluminum wiring is exposed.

As a result, the connection hole 66 reaches the copper wiring 40 of the first multilayer wiring layer 41. Further, the through connection hole 65 penetrates the bonding surface of the first multilayer wiring layer 41 and the second multilayer wiring layer 55 and reaches the aluminum wiring 57 formed in the second multilayer wiring layer 55.

At this point, the process of manufacturing the pixel array has not yet undergone the processing steps of the on-chip color filter and the on-chip lens, and it is incomplete. At the same time, the connection hole 66 formed on the copper wiring 40 and the through connection hole 65 formed on the aluminum wiring 57 can be processed and formed by extending the conventional wafer process. On the other hand, also in the logic circuit 25, the process up to the metal wiring of the uppermost layer, which is optimum as a circuit technology, is not completed. Since the different types of substrates, which are semi-finished products, are bonded together in this manner, it is possible to suppress the manufacturing cost more than the case where the different types of completed substrates are bonded together.

After that, as shown in FIG. 13, a conductive material such as copper is formed in a region including the groove 64, the light shielding film groove 82, the connection hole 66, and the through connection hole 65, and is formed by a CMP (Chemical Mechanical Polising) method. Polish the surface. As a result, only the conductive material of the groove 64, the light shielding film groove 82, the connection hole 66, and the through connection hole 65 is left. As a result, the inter-substrate wiring 68 is formed in the region of the insulating spacer layer 42, and the light shielding film 63 is formed in the light shielding region. In the present embodiment, the inter-substrate wiring 68 formed in the connection hole 66 and the inter-substrate wiring 68 formed in the through connection hole 65 are electrically connected by the connection wiring 68 a formed of the damascene wiring formed in the groove 64. Connected. The light shielding film 63 is also formed by the damascene method. Then, the groove 64, the light-shielding film groove 82, the connection hole 66, and the through connection hole 65 are filled with a conductive material, so that the copper wiring 40 and the second multilayer wiring layer formed in the first multilayer wiring layer 41 are formed. Aluminum wiring 57 formed on 55 is electrically connected.

At this time, since the barrier metal layer 58 is formed on the aluminum wiring 57 formed on the second multilayer wiring layer 55 on the second semiconductor substrate 45, when the inter-substrate wiring 68 is made of copper. However, diffusion of copper is prevented. Further, an insulating layer 67 is formed on the side wall penetrating the first semiconductor substrate 31 in the connection hole 66 and the through connection hole 65. Therefore, the inter-substrate wiring 68 and the first semiconductor substrate 31 are electrically separated and are not connected. Further, in the present embodiment, the inter-substrate wiring 68 is formed in the region of the insulating spacer layer 42 formed on the first semiconductor substrate 31, so that the inter-substrate wiring 68 and the first semiconductor are also formed. The substrate 31 is prevented from being electrically connected.

In the process of forming the inter-substrate wiring 68 of the present embodiment, the damascene method in which the groove 64, the light shielding film groove 82, the connection hole 66, and the through connection hole 65 are formed in three steps and copper is embedded is used. It is not limited to this. Between boards in which the copper wiring 40 of the first multilayer wiring layer 41 above the first semiconductor substrate 31 and the aluminum wiring 57 of the second multilayer wiring layer 55 above the second semiconductor substrate 45 are electrically connected Various modifications can be made as long as the wiring 68 is formed.

For example, the inter-substrate wiring 68 can be formed by a CVD method, a sputtering method, or the like, and can be formed by ordinary lithography and dry etching, but stacking wiring layers makes it difficult to allow sensitivity deterioration. For this reason, it is desirable to apply a damascene wiring structure with a small number of additional insulating films.

Further, in the present embodiment, the light-shielding film groove portion 82 for forming the light-shielding film 63 is processed simultaneously with the groove portion 64 for forming the inter-substrate wiring 68, but the groove portion 64, the connection hole 66, It may be formed after the through connection hole 65 and the insulating spacer layer 42 are formed. Also in this case, the light-shielding film groove portion 82 is formed in the same layer as the groove portion 64, and the conductive material is embedded in the light-shielding film groove portion 82 so that the groove portion 64, the connection hole 66, and the through connection hole 65 are electrically conductive. Simultaneously with embedding the material. Processing the light-shielding film groove portion 82 simultaneously with the groove portion 64, the connection hole 66, and the through connection hole 65 simplifies the process. However, in this case, when the insulating spacer layer 42 is formed, the insulating spacer layer 42 is also formed in the light shielding film groove portion 82, and thus the desired line width of the light shielding film 63 may not be obtained. .. When the pixels are miniaturized, it is more desirable to form the light shielding film groove 82 in a separate process from the groove 64, the connection hole 66, and the through connection hole 65.

Conventionally, the light-shielding film 63 was separately formed of tungsten, aluminum, or the like in the process before the formation of the inter-substrate wiring 68, but by forming it by the damascene method at the same time as the formation of the inter-substrate wiring 68, the process is performed. Can be simplified. At the same time, the insulating film thickness on the light receiving portion side (back surface side) of the first semiconductor substrate 31 can be reduced, which can contribute to the improvement of sensitivity.

Further, since the through connection hole 65 becomes deeper within a range of 1.5 to 10 times the depth of the connection hole 66, even if the connection hole 66 is filled with a conductive material, the through connection does not occur with the same opening size. Voids can occur in the conductive material within the holes 65.

In the present embodiment, by opening the through-holes 65 and 66 having different opening sizes according to the depth, holes having an optimum aspect ratio for embedding a conductive material and a layout space that does not increase are formed. It is possible to form. As a result, it is possible to prevent the generation of voids when the conductive material is embedded even in the deep through-holes 65.

Further, in the present embodiment, the connection hole 66 is connected to the copper wiring 40 which is the lowermost layer of the first multilayer wiring layer 41 on the first semiconductor substrate 31. This space can be used as an effective space for wiring. Therefore, it is advantageous in reducing the size of the chip.

In this embodiment, the inter-substrate wiring 68 and the first semiconductor substrate 31 are insulated from each other by the insulating layer 67 and the insulating spacer layer 42, but either one may be configured. .. When the insulating spacer layer 42 is not formed, a region corresponding to the insulating spacer layer 42 is not necessary, so that it is possible to reduce the pixel area and the photodiode (PD) area.

Next, as shown in FIG. 14, a cap film 72 is formed so as to cover the inter-substrate wiring 68 and the upper portion of the light shielding film 63. The cap film 72 can be formed, for example, by forming a SiN film or a SiCN film with a thickness of 10 to 150 nm. After that, an opening is formed in the insulating film 62 above the photodiode (PD), and the waveguide material film 69 is formed in a desired region including the opening. As the waveguide material film 69, for example, SiN can be used, and the waveguide 70 is configured by the waveguide material film 69 formed in the opening. By forming the waveguide 70, the light incident from the back surface side of the first semiconductor substrate 31 is efficiently focused on the photodiode (PD). After that, a flattening film 71 is formed on the entire surface including the waveguide material film 69.

In the present embodiment, the cap film 72 and the waveguide material film 69 above the cap film 72 are separately formed in different steps, but the waveguide material film 69 may also be used as the cap film 72. Further, in the present embodiment, the waveguide 70 is formed on the light incident surface side of the photodiode (PD), but the waveguide 70 may not be formed.

Next, as shown in FIG. 15, on-chip color filters 73 of, for example, red (R), green (G), and blue (B) are formed on the flattening film 71 so as to correspond to each pixel. The on-chip color filter 73 can be formed on the photodiode (PD) forming a desired pixel array by forming an organic film containing a pigment or dye of a desired color and patterning the film. After that, an on-chip lens material 74a is formed in the pixel array region including the upper portion of the on-chip color filter 73. As the on-chip lens material 74a, for example, an organic film or an inorganic film such as SiO, SiN, and SiON can be used, and the film is formed to 3000 nm to 4500 nm.

Next, as shown in FIG. 16, a resist film 75 for an on-chip lens is formed in a region corresponding to each pixel above the on-chip lens material 74a with a thickness of, for example, 300 nm to 1000 nm, and an etching process is performed. As a result, the shape of the resist film 75 for the on-chip lens is transferred to the on-chip lens material 74a, and the on-chip lens 74 is formed above each pixel as shown in FIG. After that, the oxide film such as the insulating film 62 formed on the first semiconductor substrate 31 is etched by CF4 gas (flow rate 10 to 200 sccm) to expose the first semiconductor substrate 31.

Next, as shown in FIG. 18, a resist film 76 in which the electrode pad portion 78 of FIG. 3 is opened is formed on the on-chip lens 74. As shown in FIG. 18, the resist film 76 is formed so that the opening end portion is closer to the pixel side than the end portion of the on-chip lens 74.

Next, the resist film 76 is used as a mask to perform an etching process under desired etching conditions. As a result, as shown in FIG. 19, a through opening that is etched from the side of the first semiconductor substrate 31 that is the uppermost substrate and penetrates the joint surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. The part 77 is formed. Then, the through opening 77 is formed until the aluminum wiring 57 formed on the second multilayer wiring layer 55 formed on the second semiconductor substrate 45, which is the lowermost substrate, is exposed. In this etching step, for example, the first semiconductor substrate 31 is etched by using an SF6/O2-based gas (flow rate: SF6: 50 to 500 sccm, O2: 10 to 300 sccm) for 1 to 60 minutes. Can be removed. Then, an oxide film or the like reaching the aluminum wiring 57 can be removed by etching using a CF4 gas (flow rate 10 to 150 sccm) for 1 to 100 minutes.

The aluminum wiring 57 thus exposed serves as an electrode pad portion 78 used when connecting to the external wiring. Hereinafter, the exposed aluminum wiring 57 will be referred to as an electrode pad portion 78. It is preferable that a plurality of the electrode pad portions 78 be formed on each of the three or four sides outside the pixel region formed on each chip.

Then, the laminated body 81a formed by laminating two semiconductor substrates as shown in FIG. 19 is divided into each chip portion by performing a dicing process thereafter. As a result, as shown in FIG. 4, the solid-state imaging device 81 including the first semiconductor chip section 22 and the second semiconductor chip section 26 is completed.

As shown in FIG. 4, the solid-state imaging device 81 thus formed can be connected to the bonding wire 79 with respect to the electrode pad portion 78, and can be connected to the external wiring of the mounting substrate by the bonding wire 79. The external wiring is electrically connected to the electrode pad portion 78, so that the wirings of the first multilayer wiring layer 41 and the second multilayer wiring layer 55 connected by the inter-substrate wiring 68 are also electrically connected. Connected to.

In the solid-state imaging device 81 of the first embodiment, the bonding wire 79 is connected to the electrode pad portion 78, but the solder bump may be used to connect the electrode pad portion 78 and the external wiring. The bonding wire or the solder bump can be selected according to the desire of the user.

In the first embodiment, the inspection of the solid-state imaging device 81 on the semiconductor wafer is performed using the electrode pad section 78. Further, the inspection is performed twice, that is, the inspection in the wafer state and the inspection in the final module state after cutting into chips.

According to the solid-state imaging device 81 and the manufacturing method thereof according to the first embodiment, the pixel region 23 and the control region 24 are formed in the chip portion on the first semiconductor substrate 31 side, and the chip on the second semiconductor substrate 45 side is formed. A logic circuit 25 for signal processing is formed in the part. Since the function of the pixel array and the logic function are formed on different chip parts in this way, the optimum process forming technique can be used for each of the pixel array and the logic circuit. Therefore, the performances of the pixel array and the logic circuit can be sufficiently exhibited, and a high-performance solid-state imaging device can be provided.

If the configuration of FIG. 2C is adopted, it is only necessary to form the pixel region 23 that receives light on the first semiconductor chip unit 22 side, and the control region 24 and the logic circuit 25 are separated and the second semiconductor chip unit 22 is separated. 26 can be formed. As a result, the optimum process technology for each functional chip can be independently selected, and the area of the product module can be reduced.

Since the pixel array and the logic circuit can be mixedly mounted by the conventional wafer process technology, the manufacturing is easy.

Further, in the present embodiment example, the first semiconductor substrate 31 having the pixel region 23 and the control region 24 and the second semiconductor substrate 45 having the logic circuit 25 are bonded together in a semi-finished product, and the first semiconductor substrate 31 is thinned. That is, the second semiconductor substrate 45 is used as a support substrate for thinning the first semiconductor substrate 31. As a result, it is possible to save members and save the manufacturing process. Furthermore, since the through connection hole 65 and the connection hole 66 are formed after thinning, the aspect ratio of the hole is reduced, and the connection hole can be formed with high accuracy.

Further, the inter-substrate wiring 68 can be formed by embedding a conductive material in the through-hole connection holes 65 and the connection holes 66 having a low aspect ratio. Therefore, not only a metal material such as tungsten (W) having a good coverage but also a coverage It is possible to use a metal material such as copper (Cu), which has poor conductivity. That is, there is no restriction on the conductive material forming the inter-substrate wiring 68. As a result, the pixel region and the control circuit can be electrically connected to the logic circuit with high accuracy. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high productivity and low manufacturing cost.

Further, in the present embodiment, the through opening 77 formed to open the electrode pad portion 78 is formed so as to penetrate the joint surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. The electrode pad section 78 is composed of the wiring of the second multilayer wiring layer 55 below the bonding surface. As a result, the electrode pad portion 78 is formed below the joining surface, which is a brittle surface between the first multilayer wiring layer 41 and the second multilayer wiring layer 55. Therefore, for example, when the bonding wire 79 is pressed against the electrode pad portion 78, it is possible to reduce the bonding stress applied to the bonding surface which is a fragile surface. As a result, it is possible to prevent cracks from being generated from the brittle joint surface during wire bonding.

In this embodiment, two semiconductor wafers are stacked, but the present invention can be applied to a structure in which two or more semiconductor wafers are stacked. In that case, a through opening is formed so that the wiring forming the wiring layer of the lowermost semiconductor wafer is exposed, and the exposed wiring is used as a wiring pad portion. This can reduce the occurrence of stress on the brittle joint surface between the substrates when connecting the external wiring and the electrode pad portion.

Further, in the backside illumination type solid-state imaging device as in the present embodiment example, since it is necessary to bring the photodiode serving as the light receiving portion closer to the circuit, it is essential to reduce the thickness of the semiconductor layer as described above. There is. Further, it is preferable that the opening for exposing the wiring below the joining surface is shallower. Therefore, when the upper semiconductor substrate (the first semiconductor substrate in the present embodiment) is a solid-state imaging device including a pixel array as in the present embodiment, the first thinned semiconductor layer is used. It is preferable to open the electrode pad portion from the side of the semiconductor substrate.

In the solid-state imaging device according to the above-described embodiment, the signal charge is an electron, the first conductivity type is a p-type, and the second conductivity type is an n-type. However, the solid-state imaging device in which the signal charge is a hole is used. Can also be applied to. In this case, the conductivity type of each semiconductor substrate, semiconductor well region, or semiconductor region is reversed, and n-type becomes the first conductivity type and p-type becomes the second conductivity type.

In the above-mentioned first embodiment, the MOS type solid-state image pickup device is taken as an example, but the present invention can be applied to a semiconductor device. Next, as a second embodiment of the present invention, a semiconductor device having a structure in which different types of chips are stacked will be described.

<3. Second Embodiment>
[Example of Configuration of Semiconductor Device and Example of Manufacturing Method Thereof]
A semiconductor device according to the second embodiment of the present invention will be described together with its manufacturing method with reference to FIGS. The semiconductor device 140 of the present embodiment example is configured by stacking a first semiconductor substrate 101 on which a first semiconductor integrated circuit is formed and a second semiconductor substrate 102 on which a second semiconductor integrated circuit is formed. It is a semiconductor device. 20, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant description will be omitted.

In the second embodiment, first, as shown in FIG. 21, a first semiconductor integrated circuit in a semi-finished state, in this example, is formed in a region which becomes each chip portion of a first semiconductor substrate (semiconductor wafer) 101. Form a logic circuit. That is, a plurality of MOS transistors Tr9, Tr10, Tr11 are formed in the regions which will be the respective chip parts of the semiconductor well region 108 formed on the first semiconductor substrate 101 made of a silicon substrate. Each of the MOS transistors Tr9 to Tr11 is configured to have a pair of source/drain regions 105 and a gate electrode 106 formed via a gate insulating film. The MOS transistors Tr9 to Tr11 are isolated by the element isolation region 100.

Although a plurality of MOS transistors are formed, the MOS transistors Tr9 to Tr11 are shown as a representative in FIG. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors Tr9 to Tr11 can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when forming an n-channel MOS transistor, an n-type source/drain region is formed in the p-type semiconductor well region 108. When forming a p-channel MOS transistor, p-type source/drain regions are formed in an n-type semiconductor well region.

The first semiconductor integrated circuit may be, for example, a semiconductor memory circuit instead of the logic circuit. In this case, the logic circuit, which will be the second semiconductor integrated circuit described later, is used for signal processing of the semiconductor memory circuit.

After forming the second insulating thin film 43b, the insulating spacer layer 113 that separates a desired region in the semiconductor well region 108 of the first semiconductor substrate 101 is formed as in the first embodiment. After forming the second insulating thin film 43b, the insulating spacer layer 113 is formed by opening a desired position of the first semiconductor substrate 101 from the back surface side and burying an insulating material. The insulating spacer layer 113 is formed in a region surrounding the inter-substrate wiring 115 of FIG.

Then, a first multilayer wiring layer 107 is formed on the first semiconductor substrate 101 with a plurality of layers, in this example, three layers of copper wirings 104, being stacked with an interlayer insulating film 103 interposed therebetween. In this embodiment, the wiring forming the first multilayer wiring layer 107 is made of copper, but a metal wiring can be made of other metal materials. These first multilayer wiring layers 107 can be formed in the same manner as in the first embodiment. Each of the MOS transistors Tr9 to Tr11 is connected to the required first-layer copper wiring 104 via the connection conductor 112. Further, the three layers of copper wiring 104 are connected to each other via the connection conductor 112.

On the other hand, as shown in FIG. 22, a second semiconductor integrated circuit in a semi-finished product state, which is a logic circuit in this example, is formed in each chip region of the second semiconductor substrate (semiconductor wafer) 102. That is, as in the case of FIG. 20, a plurality of MOS transistors Tr12, Tr13, Tr14 are formed in regions that will be the respective chip portions of the semiconductor well region 116 formed on the second semiconductor substrate 102 made of silicon. Each of the MOS transistors Tr12 to Tr14 is configured to have a pair of source/drain regions 117 and a gate electrode 118 formed via a gate insulating film. The MOS transistors Tr12 to Tr14 are separated by the element separation region 127.

Although a plurality of MOS transistors are formed, FIG. 24 shows the MOS transistors Tr12 to Tr14 as representatives. The logic circuit can be composed of CMOS transistors. Therefore, the plurality of MOS transistors can be configured as n-channel MOS transistors or p-channel MOS transistors. Therefore, when forming an n-channel MOS transistor, n-type source/drain regions are formed in the p-type semiconductor well region. When forming a p-channel MOS transistor, p-type source/drain regions are formed in the n-type semiconductor well region.

Next, a second multilayer wiring layer 124 is formed by laminating a plurality of layers, in this example, four layers of metal wiring, on the second semiconductor substrate 102 with an interlayer insulating film 119 interposed therebetween. In this embodiment, the copper wiring 120 having three layers and the aluminum wiring 121 having one layer formed on the uppermost layer are formed. Each of the MOS transistors Tr12 to Tr14 is connected to the required first-layer copper wiring 120 via a connection conductor 126. Further, the three-layer copper wiring 120 and the aluminum wiring 121 are connected to each other by the connection conductor 126. Further, also in the present embodiment example, barrier metal layers 129 and 130 are formed above and below the aluminum wiring 121, and the aluminum wiring 121 is connected to the lower copper wiring 120 via the lower barrier metal layer 129. Has been done. The second multilayer wiring layer 124 can be formed in the same manner as the multilayer wiring layer of the first embodiment.

Then, a warp correction film 123 is formed on the second multilayer wiring layer 124 to reduce a warp when the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded to each other. The warp correction film 123 can also be formed in the same manner as in the first embodiment.

Next, as shown in FIG. 23, the first semiconductor substrate 101 and the second semiconductor substrate 102 are attached so that the first multilayer wiring layer 107 and the second multilayer wiring layer 124 face each other. .. The bonding is performed with an adhesive, for example. In the case of bonding with an adhesive, an adhesive layer 125 is formed on one side of the bonding surface of the first semiconductor substrate 101 or the second semiconductor substrate 102, and they are stacked with the adhesive layer 125 interposed therebetween. Join both. In the present embodiment, the first semiconductor substrate 101 and the second semiconductor substrate 102 are bonded to each other via the adhesive layer 125, but other examples may be used. In the case of plasma bonding, a plasma TEOS film, a plasma SiN film, a SiON film (block film), a SiC film, or the like is formed on the bonding surfaces of the first semiconductor substrate 101 and the second semiconductor substrate 102, respectively. The bonding surface on which this film is formed is subjected to plasma treatment to be superposed, and then an annealing treatment is performed to bond the two. The bonding process is preferably performed by a low temperature process of 400° C. or lower that does not affect wiring or the like. Then, the first semiconductor substrate 101 and the second semiconductor substrate 102 are laminated and adhered to each other, so that a laminated body 140a including two different substrates is formed.

Next, as shown in FIG. 24, one of the first semiconductor substrates 101 is thinned by grinding and polishing from the back surface side. When the thickness of the first semiconductor substrate 101 is, for example, about 600 μm, it is thinned so that the film thickness is, for example, about 5 to 10 μm.

Next, as shown in FIG. 25, after thinning, the groove portion 164, the through connection hole 165, and the connection hole 166 are formed in the insulating spacer layer 113 in the same process as in FIGS. 10 to 13 in the first embodiment. To form. After that, the inter-substrate wiring 115 is formed in the groove portion 164, the through connection hole 165, and the connection hole 166 with the insulating layer 114 interposed therebetween. Although not shown, a light-shielding film is formed in the light-shielding region, if necessary, as in the first embodiment. Also in the present embodiment, since the through-hole connecting holes 165 and the connecting holes 166 are formed after thinning the first semiconductor substrate 101, the aspect ratio becomes small and the through-holes 165 and the connecting holes 166 can be formed as fine holes. Also in this embodiment, the through connection holes 165 and the connection holes 166 having different opening sizes are separately opened depending on the depth, so that the conductive material has an optimum aspect ratio and a layout space. It is possible to form a hole that does not become too large. Thereby, even in the deep through-connection hole 165, it is possible to prevent the occurrence of voids when the conductive material is embedded.

Then, the circuit formed on the first semiconductor substrate 101 and the circuit formed on the second semiconductor substrate 102 are electrically connected by the inter-substrate wiring 115. After that, similarly to the first embodiment, the cap film 72 is formed on the entire surface including the upper portion of the inter-substrate wiring 115.

Next, using a mask (not shown) having an opening in a desired region, etching is performed as shown in FIG. 26 to form a through opening 132 penetrating the first semiconductor substrate 101, and the aluminum wiring 121 is formed. Expose. As a result, the electrode pad portion 142 formed of the exposed aluminum wiring 121 is formed.
After that, the semiconductor device 140 of the present embodiment example shown in FIG. 20 is completed by performing a dicing process to divide each chip portion.

As shown in FIG. 20, each of the divided chips can be connected to the bonding wire 131 with respect to the electrode pad portion 142, and can be connected to the external wiring of the mounting substrate by the bonding wire 131. Then, by electrically connecting the external wiring to the electrode pad portion 142, between the wirings (circuits) formed on the first semiconductor substrate 101 and the second semiconductor substrate 102 connected by the inter-substrate wiring 115. Is also electrically connected.

According to the semiconductor device 140 and the method of manufacturing the same according to the second embodiment, similarly to the above, the first semiconductor integrated circuit and the second semiconductor integrated circuit are formed on different chip parts by the optimum process technology. Therefore, a high-performance semiconductor integrated circuit can be provided. In addition, the first and second semiconductor wafers are bonded to each other in a semi-finished product state to reduce the thickness, and after the electrical connection of the first and second semiconductor integrated circuits, the finished product state is made into a chip, thereby reducing the manufacturing cost. It can be reduced.

In addition, the same effects as those of the first embodiment can be obtained.

In the above-described first and second embodiments, the inter-substrate wiring includes the first semiconductor integrated circuit formed on the first semiconductor substrate and the second semiconductor formed on the second semiconductor substrate. An example has been shown in which it is used only as a wiring for electrically connecting to the body integrated circuit. However, the present invention is not limited to this, and, for example, by using inter-substrate wiring, wiring of the same potential formed separately in the first semiconductor substrate and the second semiconductor substrate (for example, power wiring or A part of the ground wiring) can be commonly used for each substrate.
An example in which the inter-substrate wiring is formed as a power supply wiring and a ground wiring commonly used for the first semiconductor substrate and the second semiconductor substrate will be described below.

<4. Third Embodiment>
FIG. 27 shows a schematic configuration diagram of a solid-state imaging device according to the third embodiment of the present invention. 27, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant description will be omitted.

FIG. 27 shows a region including the pixel region 23 and the control region 24 of the solid-state imaging device, and for simplification, illustration of transistors and photodiodes is omitted.

As shown in FIG. 27, in the pixel region 23, the copper wiring 40 a for outputting a pixel signal formed on the first semiconductor substrate 31 is the uppermost layer of the second multilayer wiring layer 55 via the inter-substrate wiring 68. It is connected to the signal wiring 57a formed by wiring. In this case, in the circuit configuration shown in FIG. 3, an inter-substrate wiring is formed between the wiring connected to the drain of the selection transistor formed on the first semiconductor substrate 31 and the signal wiring. Then, the processing subsequent to the signal wiring 57 a is performed in the logic circuit 25 configured by the second semiconductor substrate 45.

In the present embodiment example, the power supply wiring 57b and the ground wiring 57c formed by the uppermost wiring of the second multilayer wiring layer 55 and the copper wiring 40b formed by the uppermost wiring of the first multilayer wiring layer 41. , 40c are connected via inter-substrate wiring 68. As a result, the power supply wiring 57b and the ground wiring 57c are shared between the first semiconductor substrate 31 and the second semiconductor substrate 45.

In a three-dimensional device in which two semiconductor substrates are bonded and connected by wiring between the substrates, a wiring layer (the first multilayer wiring layer 41 and the second multilayer wiring layer 41 and the second multilayer wiring layer 41 in FIG. (Corresponding to the multi-layered wiring layer 55) cannot be formed thick. For this reason, in the conventional three-dimensional device, the distance between the wirings becomes short, and the resistance between the wirings cannot be lowered, and if the power supply wiring and the ground wiring are separately formed on the two semiconductor substrates, a large irreversible resistance will be generated. This may cause noise due to the enlargement of the element or the power supply drop.

In the solid-state imaging device of the present embodiment example, the power supply wiring 57b and the ground wiring 57c are shared between the first semiconductor substrate 31 and the second semiconductor substrate 45 formed above and below via the inter-substrate wiring 68. By doing so, it is possible to effectively form a wiring having a low resistance. Further, by forming a back surface wiring connected to the inter-substrate wiring 68 on the back surface side of the thinned first semiconductor substrate 31, it is possible to straddle the element and the different potential wiring.

A wiring layout in a laminated chip in which a first semiconductor chip (hereinafter, upper chip) and a second semiconductor chip (hereinafter, lower chip) are laminated and a design method thereof will be described below.

FIG. 28A is a schematic configuration diagram of the laminated chip 90 in the solid-state imaging device according to the present embodiment when a part of the power supply circuit 92 in which the power supply wiring 57b is formed is formed by the back surface wiring 99. 28B shows a schematic configuration diagram of a laminated chip 91 in the case where all the power supply circuits 92 in which the power supply wiring 57b is formed are formed in the second multilayer wiring layer 55 as a comparative example.

As shown in FIG. 28A, the power supply wiring between the chips is shared between the first semiconductor substrate 31 and the second semiconductor substrate 45 via the inter-substrate wiring 68. Then, the connection of the terminal connected to the power supply wiring of the power supply circuit 92 to the mounting substrate is performed through the power supply wiring 57b in the uppermost layer of the second multilayer wiring layer 55. Further, a part of the power supply circuit 92 formed by the first multilayer wiring layer 41 is interrupted at a position where layout overlap can be minimized, and is configured by the backside wiring 99 via the inter-board wiring 68. That is, a part of the power supply circuit 92 (region a surrounded by a broken line) in the configuration of FIG. 28B shown as a comparative example is a back surface wiring 99 formed on the back surface side of the first semiconductor substrate 31 in the present embodiment example. It consists of. In this case, the back surface wiring 99 can be formed by the damascene method like the connection wiring 68a formed on the inter-substrate wiring 68.

As described above, in the example of FIG. 28A, by moving a part of the power supply circuit 92 to the back surface side of the first semiconductor substrate 31 and forming the back wiring 99, the wiring can be vertically stacked. Therefore, the area of the power supply circuit 92 can be reduced as compared with the configuration of FIG. 28B.

FIG. 29A is a block diagram showing the connection between the power supply wiring and the power supply terminal and the connection between the ground wiring and the ground terminal of the laminated chip 90 according to the present embodiment. Further, FIG. 29B is a block diagram showing the connection from the power supply wiring to the power supply terminal and the connection from the ground wiring to the ground terminal in the circuit portion of the laminated chip 91 in the comparative example.

29A and 29B are schematic configuration diagrams of a main part when the laminated chips 90 and 91 in which the upper chip and the lower chip are laminated are viewed from the top, and the circuit portion 96 formed in the upper chip and the lower chip are shown. The formed circuit portion 97 is schematically shown.

In the comparative example, as shown in FIG. 29B, the power supply wiring 40b and the ground wiring 40c of the circuit portion 96 of the upper chip and the power supply wiring 57b and the ground wiring 57c of the circuit portion 97 of the lower chip are separately provided to the power supply terminals 95 and It is connected to the ground terminal 94. In this case, it is necessary to route the power supply wirings 40b and 57b and the ground wirings 40c and 57c in both the upper chip and the lower chip.

As described above, in order to operate the upper and lower chips independently in the design of the laminated chip, wiring to the input/output terminals such as the power supply wiring or the ground wiring, and the protection circuit of the input/output unit (not shown) Must be completed within each chip. However, in the laminated chip 91 as shown in FIG. 29B, the configuration in which the shared potential wiring such as the power supply wiring and the ground wiring and the protection circuit (not shown) are overlapped on both the chips have poor layout efficiency and increase the chip cost. Become a factor

On the other hand, in the configuration of the present embodiment, as shown in FIG. 29A, the power supply wirings 40b and 57b and the ground wirings 40c and 57c in the upper chip and the lower chip are provided in the connection hole 66 and the through connection hole 65, respectively. It is connected via the formed inter-substrate wiring and back wiring 99. Then, the connection to the ground terminal 94 and the power supply terminal 95 is made by the power supply wiring 57b and the ground wiring 57c of the lower chip. Therefore, in the upper chip, after the power supply wiring 40b and the ground wiring 40c are connected to the inter-substrate wiring 68, it is not necessary to route the wiring. As a result, as compared with the example of FIG. 29B, a surplus space is formed in the area z surrounded by the broken line shown in FIG. 29A, so that a new circuit can be formed in this surplus space. As a result, it is possible to realize the optimum arrangement that maximizes the chip area.

In this embodiment, a part of the circuit is formed by the backside wiring 99 formed on the backside of the first semiconductor substrate 31, but the side of the wiring has a larger surplus space on the substrate side. A common circuit may be formed between the two chips. This makes it possible to reduce the number of wiring layers and the layout area of each other.

By the way, when wirings of the same potential such as power supply wirings and ground wirings are originally formed on the same substrate, they can be shared by adjacent circuits and the layout area can be easily suppressed. However, in the structure in which the chips of two layers are formed on different substrates, it is not easy to share the wiring of the common potential because the wiring paths of the circuits of each other are limited by the wiring between the substrates.
Below, a design method for realizing the design of the solid-state imaging device of the present embodiment will be described.

FIG. 30 shows a method of designing the solid-state imaging device of the present embodiment, and FIGS. 31 to 34 show an upper chip (A in FIGS. 31 to 34) and a lower chip (FIGS. 31 to 34) in accordance with the design process. 34 B) Manufacturing process drawing.

In the solid-state imaging device according to the present embodiment, in order to connect the stacked upper chip 22 and lower chip 26 with the inter-board wiring, it is important to place the inter-board wiring 68 at a position where it does not batte with the circuit or the wiring. is there.

First, the chip size is determined from the total circuit area (step S1). Next, the circuits put in the upper chip 22 and the lower chip 26 are classified (step S2). In the present embodiment, as shown in FIGS. 31A and 31B, an example in which the pixel region 23 and the control circuit 96 are formed on the upper chip 22, and the logic circuit 97 and the input/output terminal 12 are formed on the lower chip 26. To do.

Next, the layout of the wiring between the boards is determined. The layout of the inter-substrate wiring is such as a location where many signal lines are directly connected to the upper chip 22 and the lower chip 26 (in the solid-state imaging device, a connection location between a pixel and a signal wiring). First, a custom-designed area (designed by the customer's order) is determined (step S2). As a result, the placement area of the inter-board wiring by the custom design is determined in the area indicated by the area z1 in FIGS. 32A and 32B. As shown in FIGS. 32A and 32B, the circuit surface to be directly connected (that is, the position of the inter-substrate wiring in the custom design) must be at the same position on the upper chip 22 and the lower chip 26. Rough placement is limited.

Next, the provisional external sizes of the circuit components mounted on the upper chip 22 and the lower chip 26 are defined, the provisional layout is determined, and the area of the gap where the circuit is not disposed is determined. As a result, the area where the inter-board wiring other than the custom design can be arranged (area z2 in FIG. 32A) is determined (step S4). As for the lower chip 26, if the wiring for receiving the wiring between the substrates can be placed, the circuit can be placed immediately thereunder. However, in the upper chip 22, when the inter-substrate wiring is arranged, the circuit cannot be placed immediately below and in the periphery thereof, and therefore the region where the inter-substrate wiring is arranged is mainly limited by the circuit arrangement of the upper chip 22.

Next, the wiring path (wiring 88 in FIG. 32B) for connecting and connecting the input/output terminal 12 and each circuit in the lower chip 26 is obtained by automatic wiring similar to the normal circuit design (step S5). Thereby, as shown in FIG. 32B, the input/output terminal 12 in the lower chip 26 and the logic circuit 97 are connected by the wiring 88.

Next, the wirings of the same potential to be connected between the upper chip 22 and the lower chip 26 are extracted (step S6). Thereby, as shown in FIG. 33A, in the upper chip 22, the wiring 89 desired to be connected to the wiring 88 of the lower chip 26 is laid out. Next, as shown in FIGS. 34A and 34B, the distance between the wiring 89 of the upper chip 22 and the wiring 88 of the lower chip 26 is rear surface wiring due to the automatic arrangement within the area where the inter-substrate wiring determined in step S4 can be arranged. The positions where the through connection holes 65 and the connection holes 66 are arranged are determined to be the shortest positions including the above. As a result, the placement position of the inter-substrate wiring is determined (step S7). That is, the wiring route of the back surface wiring 99 is also determined here. As a result, desired electrodes of the lower chip 26 and the upper chip 22 are connected by inter-substrate wiring, and the inter-substrate wiring connected to the lower chip 26 and the inter-substrate wiring connected to the upper chip 22 are backside wiring 99. Connected by.

The solid-state imaging device designed and manufactured in this manner is completed by performing connection verification, physical verification, timing verification, etc., as in a general flow.

As described above, in the solid-state imaging device according to the present embodiment, since the inter-substrate wiring penetrating between the stacked chips is formed, it is necessary to form the inter-substrate wiring at a position where the circuit and the wiring are not batting. It is necessary to add a process that is not in the design process of

Then, according to the solid-state imaging device designing method of the present embodiment, wirings of common potential can be formed between the upper chip 22 and the lower chip 26 by inter-substrate wiring, and the back surface can be formed. By using the wiring, the circuit formed in the chip can be simplified. As a result, the chip area can be effectively used, and the chip size can be reduced.

Although the solid-state imaging device has been described as an example in the present embodiment, the designing method of the present embodiment can be applied to the manufacture of the semiconductor device of the second embodiment.

In the conventional design of a semiconductor device of a laminated chip, a circuit is divided into functional blocks, and each is divided into upper and lower chips. On the other hand, in the semiconductor device of the present invention, the pitch of the connection holes and the through connection holes can be made sufficiently small (for example, up to 1 μm or less). It is possible to move parts to another substrate. This makes it possible to move a part of the circuit from a board with insufficient wiring area to a board with a large surplus area, or to use a part of the circuit in common, which is optimal with a small surplus area overall. Layout is possible.

<5. Fourth Embodiment>
[Configuration example of electronic device]
The above-described solid-state imaging device of the present invention can be applied to an electronic device such as a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or another device having an imaging function.

FIG. 35 is a schematic configuration diagram of an electronic device according to the fourth embodiment of the present invention. FIG. 35 illustrates a camera 200 as an example of the electronic device of the invention. The camera 200 according to the present embodiment example is a video camera capable of capturing a still image or a moving image. The camera 200 according to the present exemplary embodiment includes a solid-state imaging device 203, an optical system 201 that guides incident light to a photoelectric conversion unit configured by a photodiode of the solid-state imaging device 203, and a shutter device 202. Further, the camera 200 has a drive circuit 205 that drives the solid-state imaging device 203, and a signal processing circuit 204 that processes an output signal of the solid-state imaging device 203.

The solid-state imaging device 203 is the solid-state imaging device according to the first embodiment described above. The optical system (optical lens) 201 forms image light (incident light) from a subject on the imaging surface of the solid-state imaging device 203. As a result, signal charges are accumulated in the solid-state imaging device 203 for a certain period. The optical system 201 may be an optical lens system including a plurality of optical lenses. The shutter device 202 controls a light irradiation period and a light shielding period for the solid-state imaging device 203. The drive circuit 205 supplies a drive signal for controlling the transfer operation of the solid-state imaging device 203 and the shutter operation of the shutter device 202. The signal transfer of the solid-state imaging device 203 is performed by the drive signal (timing signal) supplied from the drive circuit 205. The signal processing circuit 204 performs various kinds of signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

According to the electronic device such as the camera 200 according to the fourth embodiment, the solid-state imaging device 203 has high performance and the manufacturing cost can be reduced. Therefore, in this embodiment, an inexpensive and highly reliable electronic device can be provided.

1... Solid-state imaging device, 2... Pixel, 3... Pixel area, 4... Vertical drive circuit, 5... Column signal processing circuit, 6... Horizontal drive circuit, 7... Output circuit, 8... Control circuit, 9... Vertical signal line, 10... Horizontal signal line, 11... Transfer transistor, 12... Input/output terminal, 13... Reset transistor, 14. ..Amplification transistor, 15...Selection transistor, 16...Floating diffusion part, 21...MOS solid-state image pickup device, 22...First semiconductor chip part, 23...Pixel region, 24. ..Control area, 25... Logic circuit, 26... Second semiconductor chip portion, 27... MOS type solid-state imaging device, 30... Unit pixel, 31... First semiconductor substrate , 31b... Back surface, 32... Semiconductor well region, 33... Source/drain region, 34... N-type semiconductor region, 35... P-type semiconductor region, 36... Gate electrode, 38 ... Element isolation region, 39... Interlayer insulating film, 40... Copper wiring, 41... First multilayer wiring layer, 42... Insulating spacer layer, 43a... First insulating thin film, 43b... second insulating thin film, 44... connection conductor, 45... second semiconductor substrate, 46... semiconductor well region, 47... source/drain region, 48... gate electrode, 49... Interlayer insulating film, 50... Element isolation region, 53... Copper wiring, 54... Connection conductor, 55... Second multilayer wiring layer, 56... Barrier metal layer, 57 ...Aluminum wiring, 57a...Signal wiring, 57b...Power supply wiring, 57c...Ground wiring, 58...Barrier metal layer, 59...Warp correction film, 60...Adhesive layer , 61... Antireflection film, 62... Insulating film, 63... Shading film, 64... Groove portion, 65... Through connection hole, 66... Connection hole, 67... Insulation layer , 68... Inter-substrate wiring, 68a... Connection wiring, 69... Waveguide material film, 70... Waveguide, 71... Flattening film, 72... Cap film, 73... On-chip color filter, 74... On-chip lens, 74a... On-chip lens material, 75... Resist film, 76... Resist film, 77... Through opening, 78... Electrode Pad portion, 79... Bonding wire, 81... Solid-state imaging device, 81a... Laminated body, 140... Semiconductor device, 140a... Laminated body

Claims (20)

A first semiconductor wafer in which a pixel array is formed and which has a first wiring layer provided on the side opposite to the light incident surface;
A second semiconductor wafer having a second wiring layer formed thereon and bonded to the first semiconductor wafer;
A penetrating connection hole that penetrates through the first semiconductor wafer and reaches the second wiring layer;
A groove portion provided on the light incident surface side in the first semiconductor wafer;
A conductive material formed in a region including the through connection hole and the groove portion,
Equipped with
A solid-state imaging device in which the conductive material electrically connects the first wiring layer and the second wiring layer. The solid-state imaging device according to claim 1, wherein
The solid-state imaging device, wherein the conductive material includes tungsten or copper. It is a solid-state imaging device of Claim 1 or 2, Comprising:
A solid-state imaging device having an insulating layer formed on a sidewall of the through-hole. It is a solid-state imaging device in any one of Claims 1-3, Comprising:
The solid-state imaging device, wherein the through connection hole is in contact with the barrier metal layer. It is a solid-state imaging device in any one of Claims 1-4, Comprising:
A solid-state imaging device in which wirings having a common potential are connected to the first wiring layer and the second wiring layer by the conductive material. The solid-state imaging device according to claim 5, wherein
The first semiconductor integrated circuit provided on the first semiconductor wafer and the second semiconductor integrated circuit provided on the first semiconductor wafer by the backside wiring formed on the light incident surface side of the first semiconductor wafer and electrically connected to the conductive material. A solid-state imaging device in which a part of a circuit used in common with a second semiconductor integrated circuit provided on a semiconductor wafer is formed. It is a solid-state imaging device in any one of Claims 1-6, Comprising:
A solid-state imaging device comprising a connection hole provided on the light incident surface side in the first semiconductor wafer. It is a solid-state imaging device in any one of Claims 1-7, Comprising:
The solid-state imaging device, wherein the through connection hole and the groove portion are arranged in a pixel region. The solid-state imaging device according to claim 1, wherein
The solid-state imaging device, wherein the through connection hole and the groove are arranged outside the pixel region. The solid-state imaging device according to claim 8, wherein
A solid-state imaging device including a plurality of the through connection holes and the groove in the pixel region. It is a solid-state imaging device in any one of Claims 1-10, Comprising:
The first semiconductor wafer is a solid-state imaging device including a photodiode. It is a solid-state imaging device in any one of Claims 1-11, Comprising:
The second semiconductor wafer is a solid-state imaging device including a signal processing circuit or a control circuit. It is a solid-state imaging device in any one of Claims 1-12, Comprising:
A solid-state imaging device in which a power supply terminal and an installation terminal are formed at opposite corners of the rectangular chip. The solid-state imaging device according to claim 7, wherein
The solid-state imaging device, wherein the conductive material is formed in a region including the through connection hole, the groove, and the connection hole. The solid-state imaging device according to any one of claims 1 to 14,
A solid-state imaging device in which copper is included in the first wiring layer. It is a solid-state imaging device in any one of Claims 1-15, Comprising:
The solid-state imaging device in which the second wiring layer contains copper or aluminum. The solid-state imaging device according to claim 7, wherein
The solid-state imaging device, wherein the diameter of the opening of the through-connection hole is 1.5 to 10 times larger than the diameter of the opening of the connection hole. The solid-state imaging device according to claim 7, wherein
In the solid-state imaging device, the depth of the through connection hole is formed to be 1.5 to 10 times deeper than the depth of the connection hole. The solid-state imaging device according to any one of claims 1 to 18,
A solid-state imaging device, wherein an insulating spacer layer for separating a desired region is formed in the first semiconductor wafer. A solid-state imaging device according to claim 1,
An optical system that guides incident light to the photoelectric conversion unit,
An electronic device including a signal processing circuit that processes an output signal of the solid-state imaging device.

Images