CN113793811B - Connecting method of chip stacking structure - Google Patents
Connecting method of chip stacking structure Download PDFInfo
- Publication number
- CN113793811B CN113793811B CN202111351802.3A CN202111351802A CN113793811B CN 113793811 B CN113793811 B CN 113793811B CN 202111351802 A CN202111351802 A CN 202111351802A CN 113793811 B CN113793811 B CN 113793811B
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- layer
- gap
- material layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a connecting method of a chip stacking structure, which comprises the following steps: providing a substrate; fixing at least two chip stacking structures on the substrate, wherein a gap is formed between every two adjacent chip stacking structures, each chip stacking structure comprises a plurality of layers of chips which are stacked, each layer of chip comprises a substrate, a bonding pad formed on the substrate and a dielectric layer covering the substrate and the bonding pad, and the gap exposes the side face of the bonding pad; removing part of the substrate and part of the dielectric layer on the side face of the gap to enable the bonding pad to partially protrude out of the dielectric layer; forming a connecting material layer on the chip stacking structure and the surface of the substrate, removing the connecting material layer on the chip stacking structure and the surface of the substrate to form a connecting layer, and connecting the adjacent bonding pads through the connecting layer; and filling the gap to connect the at least two chip stack structures together. The problem that the larger the chip area is, the lower the yield is solved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a connecting method of a chip stacking structure.
Background
With the increasing demands of the market on chips, chip manufacturing is developing toward smaller, thinner and larger devices, wherein the chip size is limited by the effective exposure area of the photomask, the effective exposure area of the conventional photomask is 26 mm × 33mm, and larger-sized chips cannot be produced by one-time exposure.
To produce larger-sized chips, it is necessary to make a plurality of exposure fields (shots) into one chip, or even one chip per wafer. It is known that the larger the chip area, the lower the yield and the higher the cost.
Disclosure of Invention
The invention aims to provide a connecting method of a chip stacking structure, which aims to solve the problem that the larger the chip area is, the lower the yield is.
In order to solve the above technical problem, the present invention provides a method for connecting a chip stacking structure, including:
providing a substrate;
fixing at least two chip stacking structures on the substrate, wherein a gap is formed between every two adjacent chip stacking structures, each chip stacking structure comprises a plurality of layers of chips which are stacked, each layer of chip comprises a substrate, a bonding pad formed on the substrate and a dielectric layer covering the substrate and the bonding pad, and the gap exposes the side face of the bonding pad;
removing part of the substrate and part of the dielectric layer on the side face of the gap to enable the bonding pad to partially protrude out of the dielectric layer;
forming a connecting material layer on the chip stacking structure and the surface of the substrate;
removing the connecting material layers on the chip stacking structure and the surface of the substrate to form a connecting layer, wherein the adjacent bonding pads are connected through the connecting layer; and the number of the first and second groups,
the gap is filled to connect at least two chip stack structures together.
Optionally, a connection material layer is formed on the chip stacking structure and the surface of the substrate by using an atomic layer deposition method.
Optionally, the step of forming a connection material layer on the chip stack structure and the substrate includes:
depositing a first connecting material layer by adopting an atomic layer deposition process; and the number of the first and second groups,
and depositing a second connecting material layer by adopting an electroplating process.
Optionally, the thickness of the first connection material layer is 10 angstroms to 500 nanometers.
Optionally, the electroplating process for depositing the second connection material layer adopts isotropic electroplating.
Optionally, the cross-sectional width of the gap is 50nm-10 μm.
Optionally, a wet etching process is used to remove a part of the substrate and a part of the dielectric layer on the side surface of the gap.
Optionally, a wet etching process or a reverse electroplating process is used to remove the chip stack structure and the connection material layer on the surface of the substrate.
Optionally, the bonding pad is made of copper, tungsten or aluminum.
Optionally, the material filling the two gaps is an insulating material.
In the method for connecting the chip stacking structure, the part of the substrate and the part of the medium layer on the side surface of the gap are removed firstly, so that the bonding pads partially protrude out of the surface of the medium layer, the connecting material layer is formed on the chip stacking structure and the substrate, the connecting material layer on the chip stacking structure and the surface of the substrate is removed, the connecting layer is formed, the adjacent bonding pads are connected through the connecting layer, the gap between the adjacent multilayer stacking chips is filled, so that the at least two chip stacking structures form a whole, a single wafer produces the chip part corresponding to a single exposure visual field area, the chip part is cut into a plurality of core particles, the core particles passing the electrical property test are selected from the cut core particles, the core particles are transversely spliced through the connecting method of the chip stacking structure, a new large chip is formed again, and the problem that the area of the chip is larger is solved, the lower the yield.
Drawings
FIG. 1 is a flow chart of a method for connecting chip stack structures according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an initial structure of a chip stack structure according to an embodiment of the present invention without connection;
FIG. 3 is a schematic structural diagram of the chip stack structure after a step of removing a part of the substrate and a part of the dielectric layer at the side of the gap according to the embodiment of the invention;
FIG. 4 is a schematic structural diagram of the chip stacking structure after the step of forming the first connecting material layer according to the embodiment of the invention;
FIG. 5 is a schematic structural diagram of the chip stacking structure after the step of forming the second connecting material layer according to the embodiment of the invention;
FIG. 6 is a schematic structural diagram of the chip stack structure after the step of forming the connection layer according to the embodiment of the invention;
FIG. 7 is a schematic diagram of a chip stacking structure for completing a lateral connection according to an embodiment of the present invention;
in the figure, the position of the upper end of the main shaft,
10-chip stacking structure; 10 a-gap; 11-a substrate; 12-a dielectric layer; 13-a pad; 14-a first layer of connecting material; 14 a-a second layer of connecting material; 14 b-a tie layer; 15-a filler material; 20-substrate.
Detailed Description
The following describes a method for connecting a chip stack structure according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Specifically, referring to fig. 1, fig. 1 is a flow chart of a connection method of a chip stack structure according to an embodiment of the invention; as shown in fig. 1, the present invention provides a method for connecting a chip stack structure, including:
step S10, providing a substrate;
step S20, fixing at least two chip stacking structures on the substrate, wherein a gap is formed between every two adjacent chip stacking structures, each chip stacking structure comprises a plurality of layers of chips which are stacked, each layer of chip comprises a substrate, a bonding pad formed on the substrate and a dielectric layer covering the substrate and the bonding pad, and the gap exposes the side face of the bonding pad;
step S30, removing part of the substrate and part of the dielectric layer on the side surface of the gap to make the pad partially protrude out of the dielectric layer;
step S40, forming a connecting material layer on the chip stacking structure and the surface of the substrate;
step S50, removing the connecting material layer on the chip stacking structure and the substrate surface to form a connecting layer, wherein the adjacent bonding pads are connected through the connecting layer; and the number of the first and second groups,
step S60, filling the gap to connect at least two chip stack structures together.
Fig. 2 to 7 are schematic structural views formed in a connection method of a chip stack structure according to an embodiment of the present invention; the following describes an embodiment of the present invention in detail with reference to fig. 2 to 7.
Before step S10, a single wafer produces a chip portion corresponding to a single exposure field area, and after dicing, a die (die) that passes an electrical test is selected, and different dies are combined into the chip stack structure 10.
As shown in fig. 2, in step S10, a substrate 20 is provided, wherein the substrate 20 is, for example, a wafer or an organic material. In step S20, at least two chip stacking structures 10 are fixed on the substrate, and a gap 10a is formed between two adjacent chip stacking structures, wherein the gap 10a is, for example, 50nm to 10 μm; each chip stacking structure 10 includes a plurality of layers of chips stacked, each layer of chips includes a substrate 11, a pad 13 formed on the substrate, and a dielectric layer 12 covering the substrate and the pad, the gap 10a exposes a side surface of the pad, and the pad 13 is, for example, copper, tungsten, or aluminum; the substrate 11 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a glass substrate, or other III-V compound substrate, and the present embodiment does not limit the material and structure of the substrate 11. In addition, a device structure (not shown) may be formed in the substrate 11, and the device structure may be a device structure formed in a semiconductor process, such as a MOS transistor. In the present embodiment, the chip stack structure 10 is, for example, a High Bandwidth Memory (HBM). The high-bandwidth memory is a high-performance DRAM (dynamic random access memory) based on a 3D (three-dimensional) stack process initiated by an ultra-micro semiconductor and SK (shell-based) Hynix, and is suitable for application occasions with high memory bandwidth requirements, such as a graphics processor, network switching and forwarding equipment (such as a router and a switch). The high-bandwidth memory is a CPU/GPU memory chip (namely, RAM), and in fact, a plurality of DDR chips are stacked together and then packaged with a GPU to realize a high-capacity and high-bit-width DDR combined array. The HBM stack is not physically integrated with the CPU or GPU, but is compactly and quickly connected through an interposer, and the HBM has almost the same characteristics as a chip-integrated RAM, and thus, has higher speed and higher bandwidth.
As shown in fig. 3, in step S30, removing a portion of the substrate 11 and the dielectric layer 12 on the side of the gap, so that the pad 13 partially protrudes from the surface of the dielectric layer 12; a wet etching process may be used to remove portions of the substrate 11 and the dielectric layer 12 lateral to the gap. The etching liquid of the wet etching process is, for example, hydrofluoric acid (HF), ammonia (NH)3·H2O) and hydrogen peroxide (H)2O2) The mixed solution of (1).
In step S40, forming a first connection material layer 14 on the chip stacking structure 10 and the surface of the substrate 20, wherein the adjacent pads 13 are connected by a connection layer; in the process of forming the connection layer connection, a process of forming the connection layer connection is selected according to the size of the gap between the two chip stack structures 10. If the gap between two chip stack structures 10 is less than or equal to 500nm, the bonding pads of adjacent chip stack structures 10 can be connected together by selectively forming the connecting material layer only through the atomic layer deposition process. The material of the first connection material layer 14 is, for example, tungsten.
As shown in fig. 4 and 5, if the gap 10a between the two chip stack structures 10 is 500nm-10 μm, the step of forming the connection material layer on the surfaces of the chip stack structures 10 and the substrate 20 includes: depositing a first connecting material layer 14 by using an atomic layer deposition process, wherein the first connecting material layer 14 covers the substrate 20, the top and the edge of the chip stack structure 10, and the protruding bonding pad 13, in this embodiment, the thickness of the first connecting material layer by using atomic layer deposition is, for example, 10 angstroms to 500 nanometers, and the material of the first connecting material layer 14 is, for example, tungsten; and depositing a second connecting material layer 14a by adopting an electroplating process, wherein the second connecting material layer 14a covers the first connecting material layer 14 and connects the protruding bonding pads 13 of the adjacent chip stacking structures 10. The electroplating process for depositing the second connecting material layer 14a, which is made of, for example, tungsten, is, for example, isotropic electroplating.
As shown in fig. 6, in step S50, the connecting material layer on the chip stack structure 10 and the surface of the substrate 20 is removed; the process of removing the connecting material layer on the chip stack structure 10 and the substrate 20 is a wet etching process or a reverse electroplating process. The principle of the reverse electroplating process is as follows: directly utilizing reverse electroplating reaction to prepare a three-phase electrode, and placing an anode and a reference electrode in an electrolyte containing a corrosion source; the first electrode is a chip stacking structure containing a connecting material layer, the other electrode is a carbon electrode, the electrochemical oxidation-reduction potential suitable for the plating layer is selected as a basic voltage, and the connecting material layer is removed by adjusting the suitable current input. The wet etching is an over-etching process to remove all the connecting material layers on the surface of the chip stack structure 10. And forming a connecting layer 14b between the bonding pads 13, wherein the connecting layer 14b is a first connecting material layer and a second connecting material layer which are etched.
Illustratively, assuming that the gap 10a between two of the chip stack structures 10 is 0.5 μm and the height of the pads 13 is 5 μm, in the process of forming the connection layer 14b, since the connection material layer grows along two pads simultaneously, the growth of the connection material layer larger than 0.25 μm can make adjacent pads 13 connected through the connection material layer, and in order to ensure that adjacent pads 13 are connected through the connection material layer, the degree of backward movement of the connection material layer can be 0.3 μm. When the connecting material layer is removed, the connecting material layer is removed along the upper surface and the lower surface, that is, the upper surface and the lower surface are respectively removed by 0.3 μm, so that the connecting material layer on the surface of the chip stacking structure 10 can be completely removed, in order to ensure that the connecting material layer on the surface of the chip stacking structure 10 is completely removed, an over-etching process can be adopted to further remove a part of the bonding pad, wherein the height of the bonding pad is 5 μm originally, and the bonding pad is etched to be 4.5 μm.
As shown in fig. 7, in step S60, the gap 10a is filled so that at least two chip stack structures form a whole. The material filling the gap 10a is an insulating material to prevent the adjacent two chip stacking structures from being short-circuited, and the material filling the gap 10a is, for example, a resin or a dielectric layer, such as a silicon oxide layer or a silicon nitride layer.
In step S60, the material filling the gap 10a fills the gap 10a between at least two chip stack structures 10, and the surface of the chip stack structure 10 is covered with a layer of filling material, so that after step S60, the filling material on the surface of the chip stack structure 10 needs to be removed, and the method for removing the filling material on the surface of the chip stack structure 10 is, for example, a chemical mechanical polishing process.
The single wafer produces the chip part corresponding to the single exposure visual field area, the crystal grains passing the electrical test are selected after cutting, and different crystal grains are transversely spliced by the connecting method of the chip stacking structure provided by the embodiment to form a new large chip again. By dispersing the chip processing area, yield loss is reduced.
Based on the same inventive concept, the present embodiment further provides a chip stacking structure, including:
a substrate 20 for carrying the chip stack structure 10;
a plurality of chip stacking structures 10, each chip stacking structure including a plurality of stacked chips, each chip stacking structure 10 including a substrate 11, a dielectric layer 12 and a pad 13 protruding from the dielectric layer 12, the protruding pads 13 of adjacent chip stacking structures 10 being connected by a connection layer 14 b; the gap 10a in front of the adjacent chip stack structure 10 is filled with a filling material.
In the present embodiment, the pad 13 is, for example, copper, tungsten, or aluminum; the filling material filling the gap 10a is an insulating material, such as a resin or a dielectric layer, such as a silicon oxide layer or a silicon nitride layer, to prevent the adjacent two chip stacked structures from being short-circuited.
At least two chip stacking structures are fixed on the substrate, and a new large chip is formed by transverse splicing.
In summary, in the method for connecting a chip stacking structure according to the embodiment of the present invention, a part of the substrate and the dielectric layer of the multi-layered stacked chip is removed to partially protrude the bonding pad on the surface of the dielectric layer, a connection material layer is formed on the chip stacking structure and the substrate, the connection material layer on the chip stacking structure and the substrate is removed to form a connection layer, the adjacent local protruded portions of the bonding pad are connected by the connection layer to fill the gap between the adjacent multi-layered stacked chips, so that the at least two multi-layered stacked chips are integrated, a single wafer produces a chip local corresponding to a single exposure field area, the chip local is cut into a plurality of core particles, the cut core particles are selected from the core particles passing the electrical performance test, the core particles are transversely spliced by the connection method of the chip stacking structure to form a new large chip, to solve the problem that the larger the chip area is, the lower the yield is.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of connecting a chip stack structure, comprising:
providing a substrate;
fixing at least two chip stacking structures on the substrate, wherein a gap is formed between every two adjacent chip stacking structures, each chip stacking structure comprises a plurality of layers of chips which are stacked, each layer of chip comprises a substrate, a bonding pad formed on the substrate and a dielectric layer covering the substrate and the bonding pad, and the gap exposes the side face of the bonding pad;
removing part of the substrate and part of the dielectric layer on the side face of the gap to enable the bonding pad to partially protrude out of the dielectric layer;
forming a connecting material layer on the chip stacking structure and the surface of the substrate;
removing the connecting material layers on the chip stacking structure and the surface of the substrate to form a connecting layer, wherein the adjacent bonding pads are connected through the connecting layer; and the number of the first and second groups,
the gap is filled to connect at least two chip stack structures together.
2. The method of claim 1, wherein the chip stack and the bonding material layer on the substrate surface are formed by atomic layer deposition.
3. The method of connecting chip stack structures according to claim 1, wherein the step of forming a connection material layer on the chip stack structure and the substrate comprises:
depositing a first connecting material layer by adopting an atomic layer deposition process; and the number of the first and second groups,
and depositing a second connecting material layer by adopting an electroplating process.
4. The method of connecting chip stack structures according to claim 3, wherein the first connecting material layer has a thickness of 10 angstroms to 500 nanometers.
5. The method for connecting chip stack structures according to claim 3, wherein the electroplating process for depositing the second connecting material layer employs isotropic electroplating.
6. The method of connecting chip stack structures according to claim 1, wherein the cross-sectional width of the gap is 50nm to 10 μm.
7. The method of claim 1, wherein a wet etching process is used to remove a portion of the substrate and a portion of the dielectric layer on the sides of the gap.
8. The method of connecting chip stack structures according to claim 1, wherein the connecting material layer of the chip stack structure and the substrate surface is removed by a wet etching process or a reverse plating process.
9. The method of connecting chip stack structures according to claim 1, wherein the bonding pad is copper, tungsten, or aluminum.
10. The method of connecting chip stack structures according to claim 1, wherein the material filling the two gaps is an insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111351802.3A CN113793811B (en) | 2021-11-16 | 2021-11-16 | Connecting method of chip stacking structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111351802.3A CN113793811B (en) | 2021-11-16 | 2021-11-16 | Connecting method of chip stacking structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113793811A CN113793811A (en) | 2021-12-14 |
| CN113793811B true CN113793811B (en) | 2022-02-15 |
Family
ID=78955138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111351802.3A Active CN113793811B (en) | 2021-11-16 | 2021-11-16 | Connecting method of chip stacking structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113793811B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110024093A (en) * | 2016-09-30 | 2019-07-16 | 株式会社新川 | The manufacturing method and packaging system of semiconductor device |
| CN110137096A (en) * | 2019-05-17 | 2019-08-16 | 武汉新芯集成电路制造有限公司 | A kind of bonding structure and its manufacturing method |
| CN110349933A (en) * | 2019-07-23 | 2019-10-18 | 上海先方半导体有限公司 | A kind of encapsulating structure and preparation method of wafer bonding stacked chips |
| CN110993518A (en) * | 2019-12-19 | 2020-04-10 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2905198B1 (en) * | 2006-08-22 | 2008-10-17 | 3D Plus Sa Sa | COLLECTIVE MANUFACTURING METHOD OF 3D ELECTRONIC MODULES |
| US8513789B2 (en) * | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
| JP2009071095A (en) * | 2007-09-14 | 2009-04-02 | Spansion Llc | Method of manufacturing semiconductor device |
| KR20170008588A (en) * | 2015-07-14 | 2017-01-24 | 에스케이하이닉스 주식회사 | Semiconductor package which are stacked SoC and memory chips |
-
2021
- 2021-11-16 CN CN202111351802.3A patent/CN113793811B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110024093A (en) * | 2016-09-30 | 2019-07-16 | 株式会社新川 | The manufacturing method and packaging system of semiconductor device |
| CN110137096A (en) * | 2019-05-17 | 2019-08-16 | 武汉新芯集成电路制造有限公司 | A kind of bonding structure and its manufacturing method |
| CN110349933A (en) * | 2019-07-23 | 2019-10-18 | 上海先方半导体有限公司 | A kind of encapsulating structure and preparation method of wafer bonding stacked chips |
| CN110993518A (en) * | 2019-12-19 | 2020-04-10 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113793811A (en) | 2021-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230057464A1 (en) | Structures and methods for memory cells | |
| US11895824B2 (en) | Vertical 1T-1C DRAM array | |
| US11784121B2 (en) | Integrated circuit components with dummy structures | |
| US11374024B2 (en) | Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor | |
| WO2018182725A1 (en) | A fully self-aligned cross grid vertical memory array | |
| CN116368616A (en) | Integrated circuit assembly | |
| TWI812670B (en) | Metallization structures for stacked device connectivity and their methods of fabrication | |
| KR20210144547A (en) | Back end of line integration for self-aligned vias | |
| NL2029640B1 (en) | Microelectronic structures including glass cores | |
| KR20210119868A (en) | Magnetic structures in integrated circuit package supports | |
| CN113793811B (en) | Connecting method of chip stacking structure | |
| WO2018182724A1 (en) | Technique for creating a self-aligned bitline in a vertical fet | |
| US20220270976A1 (en) | Microelectronic assemblies including bridges | |
| CN116264197A (en) | Backside heat dissipation using buried thermal trajectories | |
| CN115939047A (en) | Self-Aligned Gate Cut Structure | |
| US11450738B2 (en) | Source/drain regions in integrated circuit structures | |
| US20240006381A1 (en) | Microelectronic assemblies including stacked dies coupled by a through dielectric via | |
| US11842979B2 (en) | Semiconductor device and method of manufacturing the same | |
| US20240006366A1 (en) | Microelectronic assemblies including stacked dies coupled by a through dielectric via | |
| TW202230697A (en) | Cap structure for interconnect dielectrics and methods of fabrication | |
| CN116096067A (en) | Semiconductor structure and forming method thereof | |
| CN116417457A (en) | Semiconductor structure and forming method thereof | |
| TW202101768A (en) | Self-aligned gate endcap (sage) architecture having gate contacts | |
| JP2024510338A (en) | Contact structure and method of forming it | |
| TW202310324A (en) | Back-side power delivery with glass support at the front |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |