CN106449590B - A kind of semi-conductor memory module and preparation method thereof - Google Patents

A kind of semi-conductor memory module and preparation method thereof Download PDF

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Publication number
CN106449590B
CN106449590B CN201610981072.8A CN201610981072A CN106449590B CN 106449590 B CN106449590 B CN 106449590B CN 201610981072 A CN201610981072 A CN 201610981072A CN 106449590 B CN106449590 B CN 106449590B
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layer
insulation layer
conductive column
groups
chip
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CN106449590A (en
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陆原
陈�峰
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

The embodiment of the invention discloses a kind of semi-conductor memory modules and preparation method thereof, the semi-conductor memory module includes the control chipset stacked gradually from bottom to top and at least two groups of memory chips, first rewiring layer of two adjacent groups of memory chips is electrically connected by interlayer conductive column, second rewiring layer of control chipset is electrically connected with adjacent groups of memory chips by interregional conductive column, groups of memory chips includes at least two storage chips stacked gradually, with the first composite insulation layer being located at below at least two storage chips, conductive column is staggered predetermined angle in the first layer of at least two storage chips, to be electrically connected with the first rewiring layer, controlling chipset includes control chip, with the second composite insulation layer for being located at control beneath chips, conductive column in the second layer of chip is controlled to be electrically connected with the second rewiring layer.To sum up, the storage capacity and control ability of memory module can be improved, reduce memory module size, and realize the wafer scale manufacture of memory module.

Description

A kind of semi-conductor memory module and preparation method thereof
Technical field
The present embodiments relate to technical field of semiconductors more particularly to a kind of semi-conductor memory module and its production sides Method.
Background technique
Memory module is mainly made of two big funtion parts: memory device and control device.And mass storage device is wanted It is made of more storage chips or single storage chip is constituted by high density multiple memory cell；Control device is by logic chip It constitutes.The manufacture of storage chip and logic chip, because its function is different, it is difficult to use so-called System on Chip/SoC (System- On-Chip, SOC) mode, manufactured in same chip using same semiconductor processing technology.So, how effectively Ground integrates this two big funtion part, produces large capacity in a manner of large-scale production, small high-end of volume structure Memory module, come meet semiconductor technology development and microelectronic component manufacture trend --- higher performance, smaller shape Coefficient, lower cost are semi-conductor memory module research field concerns always.
For the manufacturing method of memory module, first the similar single memory of structure (or chip) is stacked in the prior art Get up, forms the memory device of large capacity, then be connected with control device.So far, the technology development of memory module is substantially edge Above-mentioned thinking carry out.
United States Patent (USP) US2006/0055020A1 (Todd O.Bolken etc.) uses ball grid array structure proposing in early days (Ball Grid Array, BGA) technology is first encapsulated single storage chip, then these single BGA package bodies, It is connected using soldered ball, a packaging body is stacked in the upper surface of another packaging body, i.e., so-called laminate packaging (Package-on- Package, POP) structure, to construct mass storage.In order to be able to achieve the BGA stacked interconnected of single storage enclosure body, BGA Soldered ball is had to the two sides for being distributed in main packaging body (including storage chip), this causes storage entirely with BGA package form Encapsulation volume is larger.It is stacked up again with such storage enclosure body when forming mass storage, entire mass storage Volume seem huge, as shown in Figure 1 a, 1 b, 40 is entirely have the function of the high-end storage of massive store and control function Modular structure；41 encapsulate in 40 the insides, the single memory with BGA structure；42 be the chip active surface of memory package body； 43 be control (logic) unit；44 one sides dribbled for packaging body；45,46 be respectively encapsulation stacking when alignment mark and space Slider；48 be the pinboard part of the single memory packaging body with BGA structure, and effect is in high-end memory module Power supply is dispensed, signal is transmitted；50 be BGA soldered ball, as the electrical interconnection between single memory；52 be substrate, by high-end storage Module is connected with the outside world.
United States Patent (USP) 2010/0270689A1 (Hye-jin Kim etc.) proposes the packaging body for removing single storage chip, Several naked storage chips and naked control logic chip are directly encapsulated in the same packaging body together to form high-end memory module Concept, as shown in Fig. 2, massive store part be divided into up and down two groups, every group of 4 storage chip staggered superpositions.310,320, 330,340,350,360,370 and 380 be storage chip；315,325,335,345,355,365,375 and 385 be adjacent storage Chip bounding wires play the role of chip chamber electrical interconnection；346 and 356 be the auxiliary pad for connecting two groups of storage chips up and down； 410 be control section (logic chip)；415 be corresponding bonding wire, and electrical connection is formed between control chip and substrate. 102 be the lower surface of BGA package structure base board；104 be the pad on the upper face of BGA package structure base board；110 seal for BGA Fill structure base board.The structure of this high-end memory module, compared with United States Patent (USP) shown in Figure 1A, Figure 1B, volume is substantially reduced, system Making process becomes simple.Manufacturing cost is also greatly reduced in this way.The specific manufacturing technology of the memory module is memory chip It stacks one by one in a manner of dislocation formula, then is used in one terrace of wire bonding single order and each chip is connected electrically in Together.Purpose using dislocation formula structure is to implement metal lead wire bonding.Then control coremaking piece is also attached in packaging body, Wire bonding is imposed again.The last entire memory module of plastic packaging simultaneously plants ball reflux.Because using chip stacked offset, memory module is occupied Not small space, and being electrically interconnected because being formed using wire bonding layer by layer, along with being discrete device encapsulation and electrical measurement, this Sample not only occupies exceptional space, and time-consuming, and manufacture efficiency is not high.But because it is that bare chip stacks and uses inexpensive lead Bonding techniques, although there is through silicon via technology later, the manufacture of high-end memory module is at present still based on the technology.
The Steven K.Grouthuis team of Micron Technology proposes based on mixing memory data set (Hybrid Memory Cube, HMC) technology high end storage concept.The main imagination of its concept is that storage chip is with through silicon via technology (Through Silicon Via, TSV) technology, vertical stacking together, then with soldered ball is electrically connected with control logic chip.Last logic chip Also it is realized with TSV technology and is connect with the external world.Their research achievement is mainly disclosed in United States Patent (USP) US2015/0279431A1 (figure 3), in US2015/0348956A1 and US2016/0013115A1.As shown in figure 3,102a and 102b are logic chip；103 For storage chip, and each storage chip 103 between 2 logic chips vertical stacking at mass storage 105；Logic chip 102a is electrically connected by pinboard 122 with the realization of package substrate 120.Package substrate 120 passes through pad 124, soldered ball 125 and the external world Realize electrical connection；110 be the packaging body (including cap 112 and encapsulation cavity 113) with heat sinking function；114a and 114b are equal For hot interfacial bonding material.The concept that these patents propose is optimal high-end memory module skill from function, volume Art, but TSV technology has it to life weakness, and manufacturing cost is expensive.It is not able to achieve slowly above in large-scale engineering manufacture.Main cause It is: (1) must is through silicon via reserved area in storage chip design；(2) logical to each independent storage chip production A possibility that Kong Shi, there are wafer damages；(3) certain complex and costly semiconductor to form pore electrod need to be increased Preceding road technique；(4) both made to identical storage chip, the necessary RDL for each chip layer of heap poststack reroutes layer Increase.Other deficiencies are the design of storage chip and the mutual restricted influence of the design of logic chip.In addition, being based on TSV technology High-end memory module carried out still in the form of discrete device assembling and functional test, low efficiency.
After the advent of fan-out-type wafer-level packaging (Fan-Out Wafer Level Packaging, FOWLP) technology, grind The person of studying carefully also considers to be applied to the technology in the manufacture of high-end memory module, a collection of patent also occurs.Regrettably, it is reported The high end storage fabrication scheme based on FOWLP technology attention is put into because of the two-dimentional feature of the current technology of FOWLP How FOWLP technology control (logic) part is made in the form of wafer scale.United States Patent (USP) US2015/0035146A1 (Jing-Cheng Lin etc.) is exactly an example, as shown in figure 4,10 be control section packaging body；66 be mass storage Packaging body；70 be include each storage chip in 66；68 be the high-end storage mould with POP structure connected through soldered ball Block.Although realizing wafer scale Integrated manufacture to logic chip, and non-through silicon via is used in the upper surface of control element, lower surface (TSV-less) technology forms electrical connection, but the processing to massive store funtion part, which is still using classical Storage chip stacks, and is subject to be electrically connected between wire bonding realizes storage chip, forms the large capacity with BGA package form Memory, the subsequent BGA package body are constituted high-end memory module with by the control section of FOWLP production with soldered ball.It is formed in this way High-end memory module there is POP package feature, and assemble, functional test carries out in the form of discrete device.
In conclusion the manufacturing technology for the high-end memory module being made of at present mass storage and control logic chip There is some distinctive and common short slab, mainly: module volume is larger, assembling and function are carried out in a manner of discrete device Test, low efficiency.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of semi-conductor memory module and preparation method thereof, to solve existing skill Semi-conductor memory module volume is larger in art, and assembling and functional test are carried out in a manner of discrete device, causes semiconductor The lower technical problem of memory module manufacture efficiency.
In a first aspect, the embodiment of the invention provides a kind of semi-conductor memory modules, comprising: stack gradually from bottom to top Chipset and at least two groups of memory chips are controlled, the first rewiring layer of two neighbouring groups of memory chips passes through The electrical connection of interlayer conductive column passes through area between the second rewiring floor and the adjacent groups of memory chips of the control chipset Between domain conductive column be electrically connected, and be located at bottom it is described first reroute layer or it is described second reroute layer and external connection it is convex Block electrical connection；
The groups of memory chips includes at least two storage chips stacked gradually, and is located at least two storage First composite insulation layer of beneath chips, at least two storage chips encapsulating are structure as a whole, and described first reroutes layer It is arranged in first composite insulation layer, conductive column is staggered predetermined angle in the first layer of at least two storage chip, To be electrically connected respectively with the first rewiring layer；
The control chipset include control chip, and positioned at it is described control beneath chips the second composite insulation layer, It is described second reroute layer be arranged in second composite insulation layer, it is described control chip the second layer in conductive column with it is described Second reroutes layer electrical connection.
Second aspect, the embodiment of the invention also provides a kind of production methods of semi-conductor memory module, comprising: in support plate Successively production controls chipset and at least two groups of memory chips, and production interlayer conductive column and interregional conduction from bottom to top Column, and the first rewiring layer of two neighbouring groups of memory chips is electrically connected by interlayer conductive column, the control It is electrically connected, and is located at most by interregional conductive column between second rewiring layer of chipset and the adjacent groups of memory chips The first rewiring layer or the second rewiring layer of lower section are electrically connected with external connection convex block；
Wherein when making any groups of memory chips, include the following steps:
At least two storage chips are stacked gradually, conductive column is staggered pre- in the first layer of at least two storage chip If angle；
At least two storage chip encapsulating is structure as a whole, and by conductive column in the first layer of the storage chip Expose；
The first composite insulation layer is formed below the integral structure, is formed with the first weight in first composite insulation layer Wiring layer, the first rewiring layer are electrically connected with conductive column in the first layer；
The step of production control chipset includes:
Conductive column in the second layer for controlling chip is exposed；
The second composite insulation layer is formed in the control beneath chips, is formed with the second weight in second composite insulation layer Wiring layer, the second rewiring layer are electrically connected with conductive column in the second layer.
Semi-conductor memory module provided in an embodiment of the present invention and preparation method thereof, by stacking gradually control from bottom to top Chipset and at least two groups of memory chips, the first of two neighbouring groups of memory chips reroute layer and pass through interlayer conduction Column electrical connection is controlled and is electrically connected between the second rewiring layer of chipset and adjacent groups of memory chips by interregional conductive column It connects, groups of memory chips includes at least two storage chips stacked gradually, and below at least two storage chips One composite insulation layer, conductive column is staggered predetermined angle in the first layer of at least two storage chips, to reroute respectively with first Layer electrical connection, control chipset includes control chip, and positioned at the second composite insulation layer of control beneath chips, controls chip The second layer in conductive column with second rewiring layer be electrically connected.Using above-mentioned technical method, groups of memory chips includes at least two Storage chip reroutes layer electrical connection, groups of memory chips and control by interlayer conductive column and first between groups of memory chips Chipset is electrically connected by interregional conductive column with the second rewiring group, guarantee memory module storage capacity with higher and Lesser size, while guaranteeing that groups of memory chips and control chipset are placed in the same wafer, realize the crystalline substance of memory module The manufacture of circle grade and wafer scale functional test, improve the production efficiency of memory module.
Detailed description of the invention
Fig. 1 a is the schematic diagram of the section structure of the memory module of spherical array array structure in the prior art；
Fig. 1 b is the side structure schematic diagram of the memory module of spherical array array structure in the prior art；
Fig. 2 is the schematic diagram of the section structure for the memory module that naked storage chip and naked control chip are constituted in the prior art；
Fig. 3 is the schematic diagram of the section structure of the memory module in the prior art based on mixing memory data set technology；
Fig. 4 is the schematic diagram of the section structure of the memory module in the prior art based on fan-out-type Wafer level packaging；
Fig. 5 is a kind of the schematic diagram of the section structure of semi-conductor memory module provided in an embodiment of the present invention；
Fig. 6 is a kind of schematic top plan view of the support plate of semi-conductor memory module provided in an embodiment of the present invention；
Fig. 7 is a kind of the schematic diagram of the section structure that interim bonding glue is coated on support plate provided in an embodiment of the present invention；
Fig. 8 a is a kind of vertical view signal that the first storage chip is formed on memory die provided in an embodiment of the present invention Figure；
Fig. 8 b is a kind of cross-section structure that the first storage chip is formed on memory die provided in an embodiment of the present invention Schematic diagram；
Fig. 9 a is a kind of vertical view signal that the second storage chip is formed on memory die provided in an embodiment of the present invention Figure；
Fig. 9 b is a kind of cross-section structure that the second storage chip is formed on memory die provided in an embodiment of the present invention Schematic diagram；
Figure 10 a is the cross-section structure that cutting memory die provided in an embodiment of the present invention forms multiple first storage chips Schematic diagram；
Figure 10 b is the cross-section structure that cutting memory die provided in an embodiment of the present invention forms multiple second storage chips Schematic diagram；
Figure 11 a, Figure 11 b and Figure 11 c are provided in an embodiment of the present invention the first storage chip and second to be made on support plate The structural schematic diagram of storage chip；
Figure 12 is provided in an embodiment of the present invention to be formed with the first storage chip and the support plate of the second storage chip is consolidated Envelope forms the schematic diagram of the section structure of sealing layer；
Figure 13 carries out thinned the schematic diagram of the section structure to sealing layer to be provided in an embodiment of the present invention；
Figure 14 is that first lower insulation layer provided in an embodiment of the present invention that formed on sealing layer carries out thinned section knot Structure schematic diagram；
Figure 15 is that the cross-section structure provided in an embodiment of the present invention for forming the first rewiring layer in the first lower insulation layer shows It is intended to；
Figure 16 is the cross-section structure provided in an embodiment of the present invention that the first upper insulation layer is formed on the first rewiring layer Schematic diagram；
Figure 17 is the schematic diagram of the section structure provided in an embodiment of the present invention for forming interlayer conductive column；
Figure 18 is the schematic diagram of the section structure provided in an embodiment of the present invention that integral structure is prepared between interlayer conductive column；
Figure 19 is provided in an embodiment of the present invention to integral structure progress sealing, forms the cross-section structure signal of sealing layer Figure；
Figure 20 is that the sealing layer provided in an embodiment of the present invention in second layer groups of memory chips carries out thinned section knot Structure schematic diagram；
Figure 21 is the section knot of the first lower insulation layer provided in an embodiment of the present invention for forming second layer groups of memory chips Structure schematic diagram；
Figure 22 is the first rewiring layer provided in an embodiment of the present invention for forming second layer groups of memory chips and the first top The schematic diagram of the section structure of insulating layer；
Figure 23 is the schematic diagram of the section structure provided in an embodiment of the present invention for forming second interlayer conductive column；
Figure 24 is the schematic diagram of the section structure provided in an embodiment of the present invention for forming four groups of memory chips；
The schematic diagram of the section structure of Figure 25 conductive column between forming region provided in an embodiment of the present invention；
Figure 26 a is a kind of schematic top plan view that control chip is formed in logic wafer provided in an embodiment of the present invention；
Figure 26 b is a kind of cross-section structure signal that control chip is formed in logic wafer provided in an embodiment of the present invention Figure；
Figure 27 is the schematic diagram of the section structure that cutting logic wafer provided in an embodiment of the present invention forms multiple control chips；
Figure 28 is the schematic diagram of the section structure provided in an embodiment of the present invention that control chip is made in storage region；
Figure 29 is the schematic diagram of the section structure provided in an embodiment of the present invention that sealing is carried out to control chip；
Figure 30 is that the sealing layer provided in an embodiment of the present invention to control chip carries out thinned the schematic diagram of the section structure；
Figure 31 is the schematic diagram of the section structure of second composite insulation layer of production provided in an embodiment of the present invention；
Figure 32 is the cross-section structure provided in an embodiment of the present invention that external connection convex block is made on the second composite insulation layer Schematic diagram；
Figure 33 is the inverted structure schematic diagram of Figure 32 provided in an embodiment of the present invention；
Figure 34 is the structural schematic diagram that multiple memory modules provided in an embodiment of the present invention to formation are cut；
Figure 35 is the structural schematic diagram of single memory module provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below with reference to attached in the embodiment of the present invention Figure, by specific embodiment, is fully described by technical solution of the present invention.Obviously, described embodiment is of the invention A part of the embodiment, instead of all the embodiments, based on the embodiment of the present invention, those of ordinary skill in the art are not doing The every other embodiment obtained under the premise of creative work out, falls within the scope of protection of the present invention.
Embodiment
Fig. 5 is a kind of structural schematic diagram of semi-conductor memory module provided in an embodiment of the present invention, as shown in figure 5, this hair The semi-conductor memory module that bright embodiment provides may include:
The control chipset stacked gradually from bottom to top and at least two groups of memory chips, two neighbouring storage cores First rewiring layer of piece group is electrically connected by interlayer conductive column, and control chipset second reroutes layer and adjacent storage core Be electrically connected between piece group by interregional conductive column, and be located at bottom first reroute layer or second reroute layer and externally Connect convex block electrical connection；
Groups of memory chips includes at least two storage chips stacked gradually, and is located at below at least two storage chips The first composite insulation layer, at least two storage chip encapsulating is structure as a whole, and first to reroute layer setting multiple first It closes in insulating layer, conductive column is staggered predetermined angle in the first layer of at least two storage chips, to reroute layer with first respectively Electrical connection；
Controlling chipset includes control chip, and positioned at the second composite insulation layer of control beneath chips, the second heavy cloth Line layer is arranged in the second composite insulation layer, controls conductive column in the second layer of chip and is electrically connected with the second rewiring layer.
Illustratively, memory module shown in fig. 5 includes a control chipset and four groups of memory chips, here with one A control chipset and four groups of memory chips are illustrated, as shown in figure 5, memory module include a control chipset 810, First groups of memory chips 310, the second groups of memory chips 510, third groups of memory chips 610 and the 4th groups of memory chips 710, In, control chipset 810, the 4th groups of memory chips 710, third groups of memory chips 610, the second groups of memory chips 510 and the One groups of memory chips 310 stacks gradually from bottom to top.
First groups of memory chips 310, the second groups of memory chips 510, third groups of memory chips 610 and the 4th groups of memory chips 710 can respectively include two, three or four storage chips, be only with two storage chips, the first storage chip in Fig. 5 110 and second storage chip 210 be illustrated.First storage chip 110 includes the first active surface and setting in the first active The first pad on face, is provided with conductive column 122 in the first layer of the first storage chip 110 in first pad, and second Storage chip 210 includes the first active surface and the first pad being arranged on the first active surface, sets in first pad It is equipped with conductive column 222 in the first layer of the second storage chip 210.Specifically, the first storage chip 110 and the second storage chip 210 spatial orientation is consistent, i.e., the first active surface of two storage chips towards identical, therefore conductive column 122 in first layer It is also identical with 222 direction.Optionally, the first storage chip 110, the second storage chip 210,122 and of conductive column in first layer 222 can be understood as an integral structure.
Further, the first groups of memory chips 310 can also include being located in the first groups of memory chips 310 under integral structure Side the first composite insulation layer, first composite insulation layer include the first upper insulation layer 405, the first lower insulation layer 401 with And first between the first upper insulation layer 405 and the first lower insulation layer 401 reroutes layer 403；Second storage chip Group 510 can also include the first composite insulation layer in the second groups of memory chips 510 below integral structure, this is first compound Insulating layer is including the first upper insulation layer 505, the first lower insulation layer 501 and is located at the first upper insulation layer 505 and first First between lower insulation layer 501 reroutes layer 503；Third groups of memory chips 610 can also include being located at third to store core The first composite insulation layer in piece group 610 below integral structure, first composite insulation layer include the first upper insulation layer 605, First lower insulation layer 601 and the first rewiring between the first upper insulation layer 605 and the first lower insulation layer 601 Layer 603；4th groups of memory chips 710 can also include first multiple in the 4th groups of memory chips 710 below integral structure Insulating layer is closed, first composite insulation layer is including the first upper insulation layer 705, the first lower insulation layer 701 and positioned at first First between upper insulation layer 705 and the first lower insulation layer 701 reroutes layer 703.Optionally, the first groups of memory chips Conductive column 122 and 222 can pass through the first through hole and the first heavy cloth in the first lower insulation layer 401 in first layer in 310 Line layer 403 is electrically connected；Conductive column 122 and 222 can be insulated by the first lower part in first layer in second groups of memory chips 510 Through-hole in layer 501 is electrically connected with the first rewiring layer 503；122 He of conductive column in first layer in third groups of memory chips 610 222 can be electrically connected by the through-hole in the first lower insulation layer 601 with the first rewiring layer 603；4th groups of memory chips 710 In first layer in conductive column 122 and 222 layer 703 can be rerouted by through-hole in the first lower insulation layer 701 and first Electrical connection.
Conductive column 122 and 222 can be staggered predetermined angle in first layer in groups of memory chips, respectively with corresponding One reroutes layer electrical connection, for example, in first layer in the first groups of memory chips 310 conductive column 122 and 222 can be staggered it is default Angle, to be electrically connected respectively with the first rewiring layer 403 in the first storage chip 310, the in the second groups of memory chips 510 Conductive column 122 and 222 can equally be staggered predetermined angle in one layer, with respectively with the first heavy cloth in the second storage chip 510 Line layer 503 is electrically connected.Optionally, the predetermined angle can be 180 °, 90 ° or 45 °.It should be noted that storage chip Conductive column can be staggered any angle other than 0 ° in layer in group, excellent as long as guaranteeing that conductive column does not overlap in layer Choosing is to be staggered 180 °, 90 ° or 45 °.
Optionally, it can also include interlayer conductive column in groups of memory chips, realize between different groups of memory chips Electrical connection, for example, may include interlayer conductive column 407 in the second groups of memory chips 510, the first of the first groups of memory chips 310 The the first rewiring layer 503 for rerouting layer 403 and the second groups of memory chips 510 can realize electrical connection by interlayer conductive column, To realize the electrical connection of the first groups of memory chips 310 and the second groups of memory chips 510.
Control chipset 810 may include controlling chip 806 and the second compound inslation positioned at 806 lower section of control chip Layer, second composite insulation layer may include the second upper insulation layer 805, the second lower insulation layer 801, and be located at second Second between upper insulation layer 805 and the second lower insulation layer 801 reroutes layer 803.Specifically, control chip 806 includes Second active surface and the second pad being arranged on second active surface, are provided with control chip in second pad Conductive column 808 in 806 second layer, conductive column 808 is electrically connected with the second pad in the second layer.Optionally, it controls in chip 806 The second layer in conductive column 808 can be electrically connected by the second through-hole in the second lower insulation layer 801 and the second rewiring layer 803 It connects.
Optionally, the second active surface and the first active surface of storage chip direction for controlling chip 806 can be identical.
Optionally, the memory module can also include external connection convex block 908, when control chipset 810 is positioned at most lower The second rewiring layer 803 of Fang Shi, control chipset 810 are electrically connected with external connection convex block 908.Further, the storage Module can also include Underbump metallization layer 906, and the second of control chipset 810 reroutes layer 803 and pass through Underbump metallization layer 906 are electrically connected with outer connection convex block 908.
It should be noted that memory module shown in fig. 5 is intended only as the one of memory module provided in an embodiment of the present invention Kind illustrates, and in memory module provided in an embodiment of the present invention, control chipset be may be located between groups of memory chips, uses In control of the realization to groups of memory chips.
Optionally, under first upper insulation layer, the first lower insulation layer, the second upper insulation layer and second Portion's insulating layer is made of organic photosensitive material.
Optionally, at least two storage chips in the groups of memory chips and the control in the control chipset Chip is encapsulated by thermosetting material.
Optionally, matcoveredn can be set in the bottom of the groups of memory chips of the top or control chipset, such as Fig. 5 institute Show, matcoveredn 909 is set above groups of memory chips 310.
Memory module provided in an embodiment of the present invention, by stacking gradually control chipset and at least two storage chips First rewiring layer of group, two neighbouring groups of memory chips is electrically connected by interlayer conductive column, controls the of chipset It is electrically connected between double wiring layer and adjacent groups of memory chips by interregional conductive column, groups of memory chips includes stacking gradually At least two storage chips, and conductive column is staggered predetermined angle in the first layer of two storage chips, respectively with first Reroute layer electrical connection.Using above-mentioned technical method, groups of memory chips includes at least two storage chips, between groups of memory chips Layer electrical connection is rerouted by interlayer conductive column and first, groups of memory chips is pre- by interregional conductive column with control chipset The electrical connection of the second rewiring group is counted, guarantees memory module storage capacity with higher and lesser size, while guaranteeing to deposit Storage chipset and control chipset are placed in the same wafer, and the wafer scale manufacture and wafer scale function for realizing memory module are surveyed Examination, improves the production efficiency of memory module.
The embodiment of the present invention also provides a kind of production method of memory module, is included in support plate successively production control from bottom to top Chipset processed and at least two groups of memory chips, and production interlayer conductive column and interregional conductive column, and neighbouring two First rewiring layer of a groups of memory chips is electrically connected by interlayer conductive column, and the second of the control chipset reroutes Layer is electrically connected between the adjacent groups of memory chips by interregional conductive column, and is located at the described first heavy cloth of bottom Line layer or the second rewiring layer are electrically connected with external connection convex block；
It is answered below as production groups of memory chips, control chipset, interlayer conductive column, zone conducts current column, first in engineering The sequence for closing insulating layer and the second composite insulation layer is illustrated, and the embodiment of the present invention is carried out by taking four groups of memory chips as an example Explanation.
Firstly, providing a support plate 300, the material of support plate 300 can be metal, silicon, glass and organic substrate etc..Support plate 300 geometry can be round or rectangular.Production is for chip patch location on 300 edge of support plate after cleaning Alignment mark, as shown in Figure 6.The production of alignment mark generally by film deposition techniques realize, such as: ion sputtering, photoetching, Development and etching, can also be realized by laser-induced thermal etching, silk-screen printing, graphic plating and machine finishing etc..The present invention is real The production method for applying the memory module of example offer can once form multiple memory modules, and the cutting of multiple memory modules is obtained Single memory module.Interim bonding glue 301 is coated after cleaning again to support plate 300 on support plate 300, as shown in Figure 8 b. Spin coating, spraying, rolling, printing, non-rotating coating, hot pressing, vacuum pressing-combining and pressure can be used in the coating of interim bonding glue 301 The modes such as fitting.Interim bonding glue 301 can be organic material or composite material.
Groups of memory chips is made on support plate 300, is specifically as follows: the storage chip first in production groups of memory chips, The embodiment of the present invention is introduced by taking two storage chips as an example.
When making any groups of memory chips, include the following steps:
At least two storage chips are stacked gradually, conductive column is staggered pre- in the first layer of at least two storage chip If angle；
At least two storage chip encapsulating is structure as a whole, and by conductive column in the first layer of the storage chip Expose；
The first composite insulation layer is formed below the integral structure, is formed with the first weight in first composite insulation layer Wiring layer, the first rewiring layer are electrically connected with conductive column in the first layer；
As figures 8 a and 8 b show, memory wafer 100 has the array arrangement of the first storage chip 110.First storage core There is piece 110 active surface 110a and non-active face 110b to have 110 external connection of the first storage chip to lead on active surface 110a First pad 121 of electricity has conductive column 122 in the first layer being previously deposited on pad 121.Conductive column is conductive in first layer Distinct methods realization, such as vacuum deposition and plating etc. can be used in the deposition of column 122.First pad pad 121 can for single layer or Multiple layer metal, such as Ti, W, Al, Cu, Ni, Pt, Ag, Au or its alloy etc., the material of conductive column 122 is metal in first layer, such as Cu, Ni, Ag, Au or its alloy etc..The height of conductive column 122 is at 70~90 μm or so in first layer.First storage chip 110 With a thickness of 40~50 μm.On the back side (the non-active face of corresponding first storage chip 110) of wafer 100, DAF film 101 is deposited. Its deposition may be implemented in a variety of ways: such as spin coating, spraying, printing, rolling and hot pressing.Effective adhesive layer of DAF film 101 Thickness at 10~30 μm or so.DAF film 101 is organic material.
As shown in figures 9 a and 9b, memory wafer 200 has the array arrangement of the second storage chip 210.Second storage core Piece 210 and the first storage chip 110 can be same type memory, can also be different kinds of memory.Second storage chip 210 With active surface 210a and non-active face 210b, on active surface 210a, there is that 210 external connection of the second storage chip is conductive One pad 221.On the first pad 221, has and be conductively connected column 222 in the first layer being previously deposited.Conductive column 122 in first layer Deposition can be used distinct methods realization, such as vacuum deposition and plating etc..First pad 121 can be single-layer or multi-layer metal, Such as Ti, W, Al, Cu, Ni, Pt, Ag, Au or its alloy etc., the material of the first conductive column 122 is metal, e.g., Cu, Ni, Ag, Au or Its alloy etc..The height of first conductive column is at 20~40 μm or so.Second storage chip 210 with a thickness of 40~50 μm.In crystalline substance On the back side (the non-active face of corresponding second storage chip 210) of circle 200, DAF film 201 is deposited.Its deposition can be with a variety of sides Formula is realized: such as, spin coating, spraying, printing, rolling and hot pressing etc..The thickness of effective adhesive layer of DAF film 201 is at 10~30 μm Left and right, DAF film 201 are organic material, and it can also be different DAF films that DAF film 201 and DAF film 101, which can be same DAF film,.
As as-shown-in figures 10 a and 10b, above-mentioned two semiconductor memory wafer is cut respectively, obtains first and deposits Store up chip 110 and the second storage chip 210.Optionally, standard semiconductor method for cutting wafer is taken in cutting, such as machine cuts or The modes such as person's laser cutting.
Such as Figure 11 a, shown in Figure 11 b and Figure 11 c, on support plate 300, with semiconductor patch device by the first storage chip 110 active surface 110a upward, in a manner of so-called " Chip-to-Wafer ", is attached on support plate 300 and is temporarily bonded glue 301 Upper surface, realize reconfiguration of first storage chip 110 on support plate.Similarly, second is deposited with semiconductor patch device The active surface 220a for storing up chip 210 upward, in a manner of so-called " Chip-to-Chip ", is placed to the first storage chip respectively On 110 active surface 110a, integral structure is formed, the integral structure can visually be interpreted as one " superchip ".It sets When putting the second storage chip 210, the second storage chip 210 and the first storage chip 110 have being staggered to expose on a position Conductive column 122 in first layer on first storage chip, 110 active surface.Storing in this way also achieves the second storage core The resetting on support plate 300 again of piece 210.The support plate for having pasted integral structure is placed in the baking oven with certain high pressure.Add Pressure really reports the integrality of patch interface to be expelled from the bubble for being stranded in each patch interface, while carrying out precuring to DAF material Processing.
As shown in figure 12, deposits dielectric materials carry out sealing to the support plate comprising integral structure, form sealing layer 302, i.e., The gap and surface of filling cladding integral structure.The height of sealing layer 302 should be than pillar height conductive in the first layer in integral structure. Deposition method can be spin coating, printing, organic lamination or plastic packaging etc..Dielectric material is generally organic thermosetting material, but does not arrange Except for insulate non-organic material.
As shown in figure 13, reduction processing is carried out to sealing layer 302, is thinned and is led until in first layer all on integral structure Expose on electric column surface.Thining method uses the standard grinding and polishing technology of semiconductors manufacture.At this point, sealing dielectric material surface is from one Structure the top surface, the i.e. distance of the active surface 210a of the second storage chip 210 are 20 μm or so.
First composite insulation layer that formed above the integral structure may include:
The first lower insulation layer is formed above the integral structure, and is formed in first lower insulation layer One through-hole；
First is formed above first lower insulation layer and reroutes layer, and the first rewiring layer passes through first through hole It is electrically connected with conductive column in the first layer；
The first upper insulation layer is formed above the first rewiring layer.
Method in specific engineering is as follows: as shown in figure 14, in the upper surface of sealing layer 302 deposition can photoetching first Lower insulation layer 401.The material of first lower insulation layer 401 includes photosensitive resin and can be formed by techniques such as dry etchings In the resin of figure, such as polyimides, photosensitive type epoxy resin, double benzocyclobutene resins and phenyl and dioxazole resin One or more, the first lower insulation layer 401 with a thickness of 5~7 μm.
Using the standard technology of semiconductor devices wafer manufacturing, graphic making is carried out to the first lower insulation layer 401, is formed First through hole, and first through hole until in integral structure in each first layer conductive column surface, it is conductive in each first layer to expose Column (not shown).
As shown in figure 15, using standard semiconductor manufacture craft, first is made in the first lower insulation layer 401 and is rerouted Layer 403.The process includes the production of the techniques such as a series of film deposition, plating, photoetching, development and etching.First reroutes The terminal on 403 one side of layer conductive column 122 in the first layer in the first through hole and integral structure in the first lower insulation layer 401 It is connected with 222, to draw the electrical connection of the first storage chip 110 and the second storage chip 210.First reroutes the material of layer 403 Material can be metal material, such as Al, Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W and its alloy.
As shown in figure 16, first reroute production in layer 403 and the first lower insulation layer 401 can photoetching the first top Insulating layer 405.The material of first upper insulation layer 405 includes photosensitive resin and can form figure by techniques such as dry etchings One of resin, such as polyimides, photosensitive type epoxy resin, double benzocyclobutene resins, phenyl and dioxazole resin or Person is a variety of.First upper insulation layer 405 with a thickness of 5~7 μm.
Using the standard technology of semiconductor devices wafer manufacturing, graphic making is carried out to the first upper insulation layer 405, is formed Opening, and the opening is until the first rewiring each corresponding end-faces of layer 403, make its exposing.First upper insulation layer, 405 graphic making The road the Qian Daohuozhong technique of standard semiconductor can be used, such as pass through exposure, development, wet process or dry etching technique.
It is formed after the first upper insulation layer, interlayer conductive column can be made in the first upper insulation layer, specifically, system Making interlayer conductive column may include:
It is formed after the first upper insulation layer, forms interlayer conductive column, the interlayer in first upper insulation layer Conductive column is for connecting two adjacent groups of memory chips.
Specifically, as shown in figure 17, in the first upper insulation layer 405, the standard technology made of semiconductor crystal wafer, The interlayer conductive column 407 for the structure that is made into one.One end of interlayer conductive column 407 passes through the opening of the first upper insulation layer 405, with First reroutes the connection of each corresponding end-faces of layer 403.The height of 407 other end of interlayer conductive column should be than the first upper insulation layer 405 Surface be higher by 100~120 μm or so.The realization of semiconductor fabrication standard technique can be used in the production of interlayer conductive column 407, such as true Sky deposition, plating and chemical plating etc..Interlayer conductive column 407 is metal material, such as Cu, Ni, Pd, Ag, Au or its alloy.This The production method for the interlayer conductive column that inventive embodiments provide, directly makes above the composite insulation layer of formation, first makes layer Between conductive column, after be made into one the dielectric medium filling of structure and integral structure, cheap thermosetting material conduct can be used in this way The dielectric medium of filling, rather than the expensive actinodielectric material of thick-layer, and remove from and use the techniques such as photoetching, production in sealing layer Cost decline also solves laser drill to the difficulty of pitch limit simultaneously because not carry out laser drill to fixed sealing material, To meet requirement of the large capacity sensor production to ultra fine pitch.
So far, the production of a groups of memory chips is completed.
In the following, the preparation to another groups of memory chips is illustrated:
As shown in figure 18, with semiconductor patch device that the active of above-mentioned integral structure is face-up, according to design position, In a manner of so-called " Chip-to-Wafer ", continue to need to illustrate in the first upper insulation layer 405 being attached on support plate 300 , the integral structure in each groups of memory chips can be identical, that is, includes the first storage chip 110, the second storage chip 120 And the conductive column 122 and on 120 active surface of the second storage chip in the layer on 110 active surface of the first storage chip Conductive column 222 in layer.
As shown in figure 19, deposits dielectric materials carry out sealing to entire support plate again, form sealing layer 502, i.e. filling bag Cover the gap and surface of integral structure.The height of sealing layer 502 should be than conductive column and layer in all first layers in integral structure Between conductive column 407 want high.Deposition method can be spin coating, printing, organic lamination and plastic packaging etc..Dielectric material is generally organic thermosetting Material, but be not excluded for as the non-organic material that insulate.
As shown in figure 20, reduction processing is carried out to sealing layer 502, is thinned and is led until in first layer all on integral structure Electric column and 407 surface of interlayer conductive column are exposed.Thining method uses the standard grinding and polishing technology of semiconductors manufacture.After grinding and polishing, sealing Layer 502 upper surface from integral structure with a distance from the surface of the top be 20 μm or so.
As shown in figure 21, the front surface coated of sealing layer 502 can photoetching the first lower insulation layer 501.First lower part is exhausted The material of edge layer 501 include photosensitive resin and can by the techniques such as dry etching formed figure resin, such as polyimides, One or more of photosensitive type epoxy resin, double benzocyclobutene resins, phenyl and dioxazole resin, the first lower insulation layer 501 with a thickness of 5~7 μm.
Using the standard technology of semiconductor devices wafer manufacturing, graphic making is carried out to the first lower insulation layer 501, is formed First through hole, and first through hole until in integral structure in each first layer conductive column surface, it is conductive in each first layer to expose Column (not shown).
As shown in figure 22, using standard semiconductor manufacture craft, first is made in the first lower insulation layer 501 and is rerouted Layer 503.The process includes the production of the techniques such as a series of film deposition, plating, photoetching, development and etching.First reroutes The terminal on 503 one side of layer conductive column 122 in the first layer in the first through hole and integral structure in the first lower insulation layer 501 It is connected with 222, to draw the electrical connection of the first storage chip 110 and the second storage chip 210.First reroutes the material of layer 503 Material can be metal material, such as Al, Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W and its alloy.
First reroute production in layer 503 and the first lower insulation layer 501 can photoetching the first upper insulation layer 505. The material of first upper insulation layer 505 includes photosensitive resin and the resin that figure can be formed by techniques such as dry etchings, example Such as one or more of polyimides, photosensitive type epoxy resin, double benzocyclobutene resins, phenyl and dioxazole resin.The One upper insulation layer 505 with a thickness of 5~7 μm.
Using the standard technology of semiconductor devices wafer manufacturing, graphic making is carried out to the first upper insulation layer 505, is formed Opening, and the opening is until the first rewiring each corresponding end-faces of layer 503, make its exposing.First upper insulation layer, 505 graphic making The road the Qian Daohuozhong technique of standard semiconductor can be used, such as pass through exposure, development, wet process or dry etching technique.
As shown in figure 23, in the first upper insulation layer 505, the standard technology made of semiconductor crystal wafer, production one The interlayer conductive column 507 of body structure.One end of interlayer conductive column 507 passes through the opening of the first upper insulation layer 505, with the first weight The connection of each corresponding end-faces of wiring layer 503.The height of 507 other end of interlayer conductive column should be than the surface of the first upper insulation layer 505 It is higher by 100~120 μm or so.The realization of semiconductor fabrication standard technique can be used in the production of interlayer conductive column 507, as vacuum is heavy Product, plating and chemical plating etc..In this way, each storage chip in integral structure reroutes layer 403 and integral structure by first Layer conductive column 407, with storage chip each in integral structure by first reroute layer 503 and integral structure interlayer conductive column 507, it realizes be electrically connected with extraneous together.Interlayer conductive column 507 is metal material as interlayer conductive column 407, e.g., Cu, Ni, Pd, Ag, Au or its alloy etc..
So far, the production of second groups of memory chips is completed.
To sum up, the groups of memory chips with massive store ability of description of the embodiment of the present invention, experienced two bull wheels After process cycles, two layers of " superchip " structure is formd, four layers of storage chip is realized and stacks.Following step is substantially Circulation more than repeating continues, until complete four layers of " superchip " structure (realizing that eight layers of storage chip stack), this not It is described in detail.
As shown in figure 24,310,510,610 and 710 be groups of memory chips；602 and 702 be dielectric medium sealing layer；601 Hes 701 be the first lower insulation layer, and 701 and 705 be the first upper insulation layer；603 and 703 first reroute layer；507 and 607 are The interlayer conductive column of groups of memory chips.
To construct high-end memory module, using the standard technology of semiconductor devices wafer manufacturing, to the 4th layer first First upper insulation layer 705 of composite insulation layer carries out graphic making, forms opening, and the opening is until first reroutes layer 703 each corresponding end-faces make it expose (not shown).Standard semiconductor can be used in first upper portion insulating passivation layer, 705 graphic making The road Qian Daohuozhong technique, such as pass through exposure, development, wet process or dry etching technique.
As shown in figure 25, on the first above-mentioned insulating layer 705, production groups of memory chips is led with control the interregional of chipset Electric column 707.
It is described to make interregional conductive column, may include:
It is formed after the first upper insulation layer, conductive column, the area between forming region in first upper insulation layer Conductive column is for connecting control chipset and groups of memory chips between domain.
Specifically, one end of interregional conductive column 707 passes through the opening of the first upper insulation layer 705, rerouted with first Each corresponding end-faces connection of 703 layers of layer, the height of interregional 707 other end of conductive column should be at 100 μm or so.Interregional conductive column The realization of semiconductor fabrication standard technique, such as vacuum deposition, plating and chemical plating can be used in 707 production.
The production method of interregional conductive column provided in an embodiment of the present invention, it is similar with the production method of interlayer conductive column, It is directly made above the composite insulation layer of formation, first makes interregional conductive column, rear production control chip and control chip Dielectric medium filling, in this way can using cheap thermosetting material as filling dielectric medium, rather than valuableness thick-layer it is photosensitive Dielectric material, and remove in sealing layer the production cost decline using the techniques such as photoetching from, simultaneously because should not to fixed sealing material into Row laser drill also solves laser drill to the difficulty of pitch limit, to meet large capacity sensor production to ultra-fine section Away from requirement.
After making interregional conductive column 707, control chipset 810 can be made between interregional conductive column 707, Specifically, the step of production control chipset, may include:
Conductive column in the second layer for controlling chip is exposed；
The second composite insulation layer is formed above control chip, is formed with the second rewiring in second composite insulation layer Layer, the second rewiring layer are electrically connected with conductive column in the second layer.
Method in specific engineering is as follows: as shown in Figure 26 a and 26b, there is control chip (logic on logic wafer 800 Chip) 810 array arrangement.There is control chip 806 active surface 806a and non-active face 806b to have on active surface 806a The second pad 821 for controlling 806 external connection of chip conduction has conductive in the second layer being previously deposited on the second pad 821 Column 822.Distinct methods realization, such as vacuum deposition and plating etc. can be used in the deposition of conductive column 822 in the second layer.Second pad 821 can be single-layer or multi-layer metal, such as Ti, W, Al, Cu, Ni, Pt, Ag, Au or its alloy etc..Conductive column 822 in the second layer Material is metal, such as Cu, Ni, Ag, Au or its alloy etc., and the height of the second interlayer conductive column is at 20~40 μm or so.Control core Piece 806 with a thickness of 40~50 μm.On the back side (the non-active face of corresponding control 806 chip of chip) of wafer 800, deposition DAF film 801.Its deposition may be implemented in a variety of ways: such as spin coating, spraying, printing, rolling and hot pressing.DAF film 801 The thickness of effective adhesive layer is at 10~30 μm or so.DAF film 801 and DAF film 101, DAF film 201 can be same DAF film, It can be different DAF films.DAF film is organic material.
As shown in figure 27, logic semiconductor wafer is cut, obtains control chip 806.Cutting takes standard partly to lead Body method for cutting wafer, such as machine cuts, laser cutting mode.
As shown in figure 28, with semiconductor patch device by control chip 806 active surface 806a upward, with so-called The mode of " Chip-to-Wafer " is attached to 705 surface of the first upper insulation layer of the 4th layer of the first composite insulation layer, realizes core Configuration of the piece 806 on support plate on store function region.
As shown in figure 29, deposits dielectric materials carry out sealing to entire support plate, form sealing layer 802, that is, filling cladding is patrolled The gap and surface of volume chip 806 and the gap of interregional conductive column 707.The height of sealing layer 802 should be than in control chip 806 Conductive column 822 and interregional conductive column 707 want high in all second layers.Deposition method can be spin coating, printing, organic lamination with And plastic packaging etc..Dielectric material is generally organic thermosetting material, but is not excluded for as the non-organic material that insulate.
As shown in figure 30, reduction processing is carried out to sealing layer 802, be thinned until conductive column all on control chip 806 Surface and 707 surface of interregional conductive column are all exposed.Thining method uses the standard grinding and polishing technology of semiconductors manufacture, grinding and polishing Afterwards, 802 upper surface of sealing layer is 20 μm or so with a distance from control 806 the top surface of chip.
After the sealing for completing control chip 806, the second compound inslation is formed above the good control chip 806 of sealing Layer, forming the second composite insulation layer above control chip 806 may include:
The second lower insulation layer is formed above the control chip, and is formed in second lower insulation layer Two through-holes；
Second is formed above second lower insulation layer and reroutes layer, and described second, which reroutes layer, passes through the second through-hole It is electrically connected with conductive column in the second layer；
The second upper insulation layer is formed above the second rewiring layer.
Specifically, sealing layer 802 front surface coated can photoetching the second lower insulation layer 801, the second lower insulation layer 801 material includes photosensitive resin and the resin that figure can be formed by techniques such as dry etchings, such as polyimides, photosensitive One or more of type epoxy resin, double benzocyclobutene resins, phenyl and dioxazole resin.Second lower insulation layer 801 With a thickness of 5~7 μm.Then the standard technology for using semiconductor devices wafer manufacturing, carries out figure to the second lower insulation layer 801 Shape is made, and forms the second through-hole, and two through-holes are until control the surface and region of conductive column 822 in each second layer in chip 806 Between 707 surface of conductive column, make its expose (being not drawn into figure).
Using standard semiconductor manufacture craft, second is made in the second lower insulation layer 801 and reroutes layer 803.The mistake Journey includes the production of the techniques such as a series of film deposition, plating, photoetching, development and etching.Second reroutes 803 one side of layer Terminal is led through the second through-hole in the second lower insulation layer 801 with the second interlayer on control 806 the second pad of active surface of chip Electric column 822 is connected with interregional 707 surface of conductive column, with each storage core in extraction control chip 806, groups of memory chips 710 Each storage chip (passes through the first weight in piece (passing through the first rewiring layer 703 and interregional conductive column 707), groups of memory chips 610 Wiring layer 603, groups of memory chips interlayer conductive column 607 and interregional conductive column 707), respectively store core in groups of memory chips 510 Piece (rerouting layer 503, groups of memory chips interlayer conductive column 507,607 and interregional conductive column 707 by first) and storage core Each storage chip (reroutes layer 403 by first, 407,507,607 and region is electrically interconnected in groups of memory chips interlayer in piece group 310 Between conductive column 707) electrical connection (not shown).Second reroute layer 803 material be metal material, as Al, Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W etc. and its alloy.
As shown in figure 31, second reroute production in structure 803 and the second lower insulation layer 801 can photoetching second on Portion's insulating layer (passivation layer) 805.The production of second upper insulation layer (passivation layer) 805 uses the road Qian Daohuozhong of standard semiconductor Technique, such as pass through exposure, development, wet process or dry etching technique.The material of second upper insulation layer 805 is generally organic material Material, but be not excluded for as inorganic material.Organic material includes the photosensitive resin for forming figure, such as polyimides, photosensitive type epoxy Resin, solder mask, green paint, dry film, photosensitive type increasing layer material, double benzocyclobutene resins, in phenyl benzo dioxazole resin It is one or more kinds of.
For the production for completing high-end memory module, Underbump metallization and external connection terminal are made below.
Using the standard technology of semiconductor devices wafer manufacturing, graphic making is carried out to the second upper insulation layer 805, is formed Opening, and the opening is until second rewiring 803 layers of each corresponding end-faces of layer, make its expose (being not drawn into figure).Second top is exhausted The road the Qian Daohuozhong technique of standard semiconductor can be used in 805 graphic making of edge layer, is such as carved by exposure, development, wet process or dry method The techniques such as erosion.
As shown in figure 32, production Underbump metallization 906 is in the opening of the second upper insulation layer 805, and with the second heavy cloth Each end face pad of line layer 803 is connected.The production of Underbump metallization 906 passes through techniques such as sputtering, plating, vacuum evaporation deposition and auxiliary With the realization of the techniques such as photoetching, development, etching.The material of Underbump metallization 906 is the metal or alloy mutually affine with solder, such as Ni, Cu, Pt, Ag and its alloy.Then, external connection convex block 908 is made on Underbump metallization 906.Its production can pass through It is electroplated, prints, plant ball, putting the techniques such as ball, then carrying out reflux technique.Reflux can be real by heat transfer, convection current, radiation etc. It is existing.The material of external connection convex block 908 is mainly solder metal.Such as, Sn, Ag, Cu, Pb, Au, Ni, Zn, Mo, Ta, Bi, In, etc. And its alloy.
Remove support plate 300 and interim bonding glue 301.Support plate 300 can pass through mechanical, heating, change with interim bonding glue 301 The modes such as, laser remove.Then, to entire high-end memory module, structure " wafer " is overturn again, is made in groups of memory chips 310 The non-active face 110b of the first storage chip 110 and the lower surface of sealing layer 302 be in memory module top surface and (do not draw Out).
As shown in figure 33, one is deposited on the lower surface of the non-active face 110b of the first storage chip 110 and sealing layer 302 Layer protective film 909.The deposition of protective film can in many ways, such as: spin coating, spraying, printing, rolling, hot pressing or vacuum pressing-combining Deng Protective coatings are organic material.
Such as Figure 34, the dotted line in figure carries out separation cutting, is stored to advanced semiconductor memory module is formed by Module.
Such as Figure 35, single semi-conductor memory module is obtained after process above process.The semi-conductor memory module is by two A functional area composition: massive store region and control area.Massive store region itself again by 4 groups of memory chips and One control chipset composition, each groups of memory chips stack structure by first storage chip and second storage chip At control chipset is 1 control chip.Optionally, the first storage chip and the second storage chip can be identical or not Together, when the first storage chip and identical the second storage chip, the storage chip integrated in storage region will be " superchip " 2 times.
The production method of semi-conductor memory module provided in an embodiment of the present invention, successively production controls chipset on support plate With at least two groups of memory chips, each groups of memory chips includes at least two storage chips, groups of memory chips and storage chip Group is electrically connected by conductive column, interlayer conductive column and the first rewiring layer realization between groups of memory chips in first layer It connects, multiple groups of memory chips and control chipset pass through the first interlayer conductive column, the second interlayer conductive column, interlayer conductive column, area Conductive column, first between groups of memory chips reroute layer and are located between groups of memory chips and control chipset between domain Second reroute layer and realize electrical connection, in this way, provide not only the storage region of large capacity, guarantee storage region small size Feature can also realize that storage chip is arranged on the same wafer with control chip (logic chip), realize control chip It is integrated with the three-dimensional wafer-level of storage chip, reduce circuit loss of the memory module on encapsulating structure, memory module it is whole Body function is improved, and can also further be realized the wafer scale manufacture and wafer scale functional test of memory module, be improved production Efficiency reduces production cost.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation, It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.

Claims (13)

1. a kind of semi-conductor memory module, which is characterized in that including the control chipset stacked gradually from bottom to top and at least two First rewiring layer of a groups of memory chips, two neighbouring groups of memory chips is electrically connected by interlayer conductive column, It is electrically connected between the second rewiring layer and the adjacent groups of memory chips of the control chipset by interregional conductive column, And layer is rerouted positioned at the first rewiring layer of bottom or described second and is electrically connected with external connection convex block；
The groups of memory chips includes at least two storage chips stacked gradually, and is located at least two storage chip First composite insulation layer of lower section, at least two storage chips encapsulating are structure as a whole, and described first reroutes layer setting In first composite insulation layer, conductive column is staggered predetermined angle in the first layer of at least two storage chip, with point It is not electrically connected with the first rewiring layer；
The control chipset includes control chip, and positioned at the second composite insulation layer of the control beneath chips, described Second, which reroutes layer, is arranged in second composite insulation layer, conductive column and described second in the second layer of the control chip Reroute layer electrical connection.
2. semi-conductor memory module according to claim 1, which is characterized in that the control chipset is located at bottom, Second rewiring layer of the control chipset is electrically connected with external connection convex block.
3. semi-conductor memory module according to claim 1, which is characterized in that the first of at least two storage chip Active surface towards identical, and the first pad is provided on first active surface, in first pad and the first layer Conductive column electrical connection.
4. semi-conductor memory module according to claim 3, which is characterized in that it is described control chip the second active surface with First active surface of the storage chip is provided with the second pad towards identical on second active surface, second weldering Disk is electrically connected with conductive column in the second layer.
5. semi-conductor memory module according to claim 1, which is characterized in that each groups of memory chips includes two A, three or four storage chips.
6. semi-conductor memory module according to claim 5, which is characterized in that at least two in the groups of memory chips Conductive column is staggered 90 ° or 180 ° in the first layer of storage chip.
7. semi-conductor memory module according to claim 1, which is characterized in that first composite insulation layer includes first Upper insulation layer and the first lower insulation layer, and between first upper insulation layer and the first lower insulation layer One reroutes layer, and conductive column reroutes layer by the first through hole and described first in the first lower insulation layer in the first layer Electrical connection；
Second composite insulation layer includes the second upper insulation layer and the second lower insulation layer, and is located at second top Second between insulating layer and the second lower insulation layer reroutes layer, and conductive column passes through the second lower insulation layer in the second layer In the second through-hole with it is described second rewiring layer be electrically connected.
8. semi-conductor memory module according to claim 7, which is characterized in that first upper insulation layer, the first institute Lower insulation layer, the second upper insulation layer and the second lower insulation layer is stated to be made of organic photosensitive material.
9. semi-conductor memory module according to claim 1, which is characterized in that at least two in the groups of memory chips Control chip in storage chip and the control chipset is encapsulated by thermosetting material.
10. semi-conductor memory module according to claim 1, which is characterized in that the groups of memory chips or control of the top Matcoveredn is arranged in the bottom of chipset.
11. a kind of production method of semi-conductor memory module, which is characterized in that be included in support plate successively production control from bottom to top Chipset and at least two groups of memory chips, and production interlayer conductive column and interregional conductive column, and neighbouring two First rewiring layer of the groups of memory chips is electrically connected by interlayer conductive column, and the second of the control chipset reroutes layer It is electrically connected between the adjacent groups of memory chips by interregional conductive column, and is located at described the first of the top and reroutes Layer or the second rewiring layer are electrically connected with external connection convex block；
Wherein when making any groups of memory chips, include the following steps:
At least two storage chips are stacked gradually, conductive column is staggered preset angle in the first layer of at least two storage chip Degree；
At least two storage chip encapsulating is structure as a whole, and conductive column in the first layer of the storage chip is revealed Out；
The first composite insulation layer is formed above the integral structure, is formed with the first rewiring in first composite insulation layer Layer, the first rewiring layer are electrically connected with conductive column in the first layer；
The step of production control chipset includes:
Conductive column in the second layer for controlling chip is exposed；
The second composite insulation layer is formed above the control chip, is formed with the second rewiring in second composite insulation layer Layer, the second rewiring layer are electrically connected with conductive column in the second layer.
12. production method according to claim 11, which is characterized in that described to form first above the integral structure Composite insulation layer includes:
The first lower insulation layer is formed above the integral structure, and is formed first in first lower insulation layer and led to Hole；
First is formed above first lower insulation layer and reroutes layer, and described first, which reroutes layer, passes through first through hole and institute Conductive column in first layer is stated to be electrically connected；
The first upper insulation layer is formed above the first rewiring layer；
It is described to form the second composite insulation layer above the control chip and include:
The second lower insulation layer is formed above the control chip, and is formed second in second lower insulation layer and led to Hole；
Second is formed above second lower insulation layer and reroutes layer, and described second, which reroutes layer, passes through the second through-hole and institute Conductive column in the second layer is stated to be electrically connected；
The second upper insulation layer is formed above the second rewiring layer.
13. production method according to claim 12, which is characterized in that the production interlayer conductive column, comprising:
It is formed after the first upper insulation layer, forms interlayer conductive column in first upper insulation layer, the interlayer is conductive Column is for connecting two adjacent groups of memory chips；
The interregional conductive column of production, comprising:
It is formed after the first upper insulation layer, conductive column between forming region, described interregional in first upper insulation layer Conductive column is for connecting control chipset and groups of memory chips.
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