CN202434509U - Stackable semiconductor chip packaging structure - Google Patents
Stackable semiconductor chip packaging structure Download PDFInfo
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- CN202434509U CN202434509U CN2012200240478U CN201220024047U CN202434509U CN 202434509 U CN202434509 U CN 202434509U CN 2012200240478 U CN2012200240478 U CN 2012200240478U CN 201220024047 U CN201220024047 U CN 201220024047U CN 202434509 U CN202434509 U CN 202434509U
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Abstract
The utility model discloses a stackable semiconductor chip packaging structure, which comprises a top layer package and a bottom layer package, wherein a groove is arranged on a bottom layer package substrate, a semiconductor chip of the bottom layer package is arranged in the groove, a bonding pad is arranged on the substrate, the bottom layer semiconductor chip is connected with the bonding pad through a bonded lead, the top layer package is overlapped and packaged above the upper surface of the top layer package substrate through one or more of semiconductor chip layers, the bonding pad is arranged on the top layer package substrate, the semiconductor chip is connected with the bonding pad through the bonded lead, the top layer package part is sealed by a sealant, the top layer package is connected with the bottom layer package through the bonding pad and a welding ball array, and the sealant is filled between the top layer package substrate and the bottom layer package substrate. The stackable semiconductor chip packaging structure, provided by the utility model, has the advantages of capability of effectively improving packaging density, and being simple in process flow, large in substrate rigidity, difficulty in generating warping, thin in total thickness and high in reliability.
Description
Technical field
The utility model relates to a kind of semiconductor packaging, particularly a kind of stacked semiconductor chip encapsulating structure.
Background technology
Because people are urgent for the increasing demand of miniaturization of electronic products, lightness, three-dimension packaging has been complied with this trend, and the three-dimensional electronic encapsulation technology has obtained the development of advancing by leaps and bounds recently.Encapsulating range upon range of (package on package) technology is a kind of three-dimension packaging solution with low cost; It can be incorporated into logic chip and storage chip in the packaging body; And control storage capacity flexibly as required; Therefore, in electronic products such as mobile phone, obtained at present using widely.The base plate for packaging that traditional P oP encapsulation is adopted is thinner, and in technological process, the basal plate heated expansion produces warpage, has caused interconnection difficulty between bottom and the top layer packaging body, and generation is tired in combining soldered ball easily, and crackle etc. cause reliability of products to reduce.
Summary of the invention
The purpose of the utility model is to the defective that exists in the prior art, and a kind of stacked semiconductor chip encapsulating structure is provided.The utility model comprises the sealant between welded ball array, top layer encapsulation and the bottom encapsulation between top layer encapsulation, bottom encapsulation, top layer encapsulation and the bottom encapsulation; It is characterized in that said bottom base plate for packaging is provided with an inverted trapezoidal groove; The upper surface of bottom base plate for packaging is a first surface, and the lower surface of bottom base plate for packaging is a second surface, and the surface in the bottom base plate for packaging groove is the 3rd surface; The semiconductor chip of bottom encapsulation is arranged in the groove; Be equipped with pad on first, second, third surface, the bottom semiconductor chip links to each other with the 3rd lip-deep pad through bonding wire, and top layer encapsulates by one or several semiconductor chip laminate packaging on the upper surface of top layer base plate for packaging; The upper surface and the lower surface of top layer base plate for packaging are equipped with pad; Semiconductor chip in the top layer encapsulation links to each other with the pad of top layer base plate for packaging upper surface through bonding wire, and the top layer packed part seals through sealant, is connected with welded ball array through pad between top layer encapsulation and the bottom encapsulation; Filling sealing agent between top layer base plate for packaging and the bottom base plate for packaging is referring to Fig. 2.
The utility model bottom base plate for packaging is provided with groove, and the bottom packaged chip is fixed on bottom portion of groove, therefore can not cause the packaging body integral thickness to increase.Therefore this encapsulating structure has thin thickness, and the advantage that reliability is high is as shown in Figure 1.The base plate for packaging that the bottom encapsulation is adopted is big than conventional base plate for packaging thickness, so the rigidity of substrate can be bigger, is difficult for producing warpage.
Fig. 1 can find that for traditional P oP encapsulation cross sectional representation, comparison diagram 1 essential difference of the two is that the substrate of the utility model patent bottom encapsulation is provided with groove.Traditional P oP packaging bottom layer substrate is thinner, but the bottom packaged chip directly is bonded on the upper surface of bottom base plate for packaging, and the thickness t 1 that this bottom that causes the integral thickness t2 of conventional P oP packaging bottom layer encapsulation to provide unlike present embodiment encapsulates is thin.And because conventional package bottom base plate for packaging is thin; In the packaging technology flow process, more be easy to generate warpage; Cause to combine difficulty between glob top and the bottom package body, this will certainly produce problems such as fatigue failure, fracture in soldered ball, reduced the reliability of encapsulating products.
Groove on the said bottom base plate for packaging is for trapezoidal, and the semiconductor chip of bottom encapsulation is bonded in bottom portion of groove by Heraeus, perhaps is welded on bottom portion of groove with face-down bonding technique, and semiconductor chip is connected with the bottom portion of groove soldered ball.Be provided with the circuit that is connected usefulness in bottom base plate for packaging and the top layer base plate for packaging.The second surface of bottom base plate for packaging is provided with welded ball array, and welded ball array is that the mode of silk screen printing or plating or vapor deposition is coated with scolder, refluxes to produce welded ball array, and its material is SnAg, Sn, SnAgCu, PbSn.
The semiconductor chip of said top layer encapsulation is the stacked in layers structure, and the semiconductor chip of top layer encapsulation and bonding wire adopt the sealant sealing, and sealant is an epoxy molding plastic.Between top layer encapsulation and the bottom encapsulation is individual layer or double-deck welded ball array; Through reflux technique top layer encapsulation and bottom encapsulation are linked together; Perhaps deposit solder layer after the lower surface pad of top layer base plate for packaging powers on copper plated pillars; Deposit solder layer after the first surface pad of bottom base plate for packaging powers on copper plated pillars; The material of solder layer can be SnAg, Sn, SnAgCu, PbSn, through reflux technique top layer base plate for packaging and bottom base plate for packaging is linked together, and accomplishes the electrical interconnection between top layer packaging body and the bottom packaging body.
The utility model has the advantages that effective raising packaging density, technological process is simple, and substrate rigidity is big, is difficult for producing warpage, and general thickness is thin, and reliability is high.
Description of drawings
Fig. 1 traditional P oP encapsulating structure cutaway view;
The structural representation of Fig. 2 the utility model;
The cutaway view of Fig. 3 the utility model bottom base plate for packaging;
Fig. 4 bottom base plate for packaging passes through the fixedly cutaway view of semiconductor chip of Heraeus;
The sketch map of Fig. 5 bottom semiconductor chip bonding wire;
The cutaway view of Fig. 6 top layer base plate for packaging;
The fixing cutaway view of semiconductor chip on Fig. 7 top layer base plate for packaging;
Fig. 8 is through the cutaway view of the fixing two layers of semiconductor chip of Heraeus;
Fig. 9 passes through the fixedly cutaway view of three-layer semiconductor chip of Heraeus;
The sketch map of Figure 10 top layer semiconductor chip bonding wire;
Figure 11 adopts the sketch map of sealant with top layer semiconductor chip and bonding wire sealing;
Figure 12 plants the sketch map of soldered ball on the pad of top layer base plate for packaging lower surface;
The sketch map that Figure 13 links together top encapsulation and bottom package;
The sketch map of Figure 14 filling sealing agent between top encapsulation and bottom package;
Figure 15 plants the sketch map of soldered ball on bottom package second surface pad;
The structural representation of Figure 16 embodiment two;
The structural representation of Figure 17 embodiment three;
The structural representation of Figure 18 embodiment four;
The structural representation of Figure 19 embodiment five.
Among the figure: 1 Heraeus; 2 semiconductor chips; 3 Heraeus; The 3a wall; 4 semiconductor chips; 5 Heraeus; The 5a wall; 6 semiconductor chips; 7 pads; 8 bonding wires; 9 bonding wires; 10 bonding wires; 11 top layer base plate for packaging upper surface pads; 12 top layer base plate for packaging; 13 top layer base plate for packaging lower surface pad; 14 sealants; 15 soldered balls; 16 bottom base plate for packaging; 17 bottom base plate for packaging second surface pads; 18 soldered balls; 19 bottom base plate for packaging the 3rd surface pads; 20 Heraeus; 21 semiconductor chips; 22 pads; 23 bonding wires; 24 sealants; 25 pads; 26 pads; 27 bottom base plate for packaging first surface pads; 28 soldered balls; 29 underfill materials; 30 semiconductor chips; 31 bottom base plate for packaging the 3rd surface pads; 32 bronze medal posts; 33 solder layers; 34 bronze medal posts; 35 chips, 2 surface pads; 36 underfill materials; 37 welded ball arrays; 38 bottom base plate for packaging first surface pads.
Embodiment
Further specify the embodiment of the utility model below in conjunction with accompanying drawing.
Embodiment one
Fig. 2 is the structural representation of the utility model embodiment one, and this encapsulation comprises the welded ball array of top encapsulation, bottom package, interconnected bases encapsulation and top encapsulation, and the sealant between top layer encapsulation and the bottom encapsulation.The substrate 16 of bottom package is provided with an inverted trapezoidal groove, and semiconductor chip 21 is fixed on bottom portion of groove through Heraeus 20.Top encapsulation comprises at least one semiconductor chip, and top encapsulation has comprised three semiconductor chips among Fig. 2, and three semiconductor chips are stacked in layers through Heraeus and wall to be placed, and wall is the bonding wire headspace.Pad 11 on pad on the semiconductor chip and top encapsulation substrate 12 first surfaces is connected through bonding wire realizes electrical interconnection.Sealant 24 covers the top of the upper surface of top layer base plate for packaging, the semiconductor chip and the lead-in wire of the encapsulation of sealing top layer.The electrical interconnection of top layer encapsulation and bottom encapsulation realizes through welded ball array 15.Realize sealing through sealant 14 between the lower surface of the substrate of top layer encapsulation and the first surface of bottom base plate for packaging and the 3rd surface.The second surface of the substrate 16 of bottom encapsulation arranges that welded ball array is to realize packaging body and outside electrical interconnection.
The packaging technology of present embodiment comprises following steps:
Steps A
Preparation has the bottom base plate for packaging of groove; The upper surface of bottom base plate for packaging 16 is a first surface; The lower surface of bottom base plate for packaging is a second surface, and the surface in the bottom base plate for packaging groove is the 3rd surface, and groove location is arranged on the substrate first surface; This groove is arranged on the center of bottom base plate for packaging; Bottom portion of groove forms the 3rd surface, and substrate can be selected pcb board or FR4 version or BT plate for use, and is as shown in Figure 3.
Step B
On three surfaces of bottom base plate for packaging, prepare pad; Preparation pad 27 on the first surface of bottom base plate for packaging 16, preparation pad 17, the three surface preparation pads 19 on the second surface.Circuit and interconnect pad 27, pad 17, pad 19 in bottom base plate for packaging inside comprises.
Step C
Be installed in the groove semiconductor chip of bottom encapsulation and completion lead-in wire bonding; The bottom portion of groove of bottom base plate for packaging 16 passes through fixedly semiconductor chip 21 of Heraeus 20; Heraeus 20 adopts organic polymer elargol or inorganic polymer elargol; Earlier Heraeus is coated on bottom portion of groove, semiconductor chip 21 is installed then, solidify; The cooling back just can be fixed on the adhesive layer top with semiconductor chip 21, and is as shown in Figure 4.Through bonding wire 23 interconnection semiconductor chip pads 22 and bottom portion of groove pad 19; Bottom portion of groove pad 19 links to each other with the second surface pad 17 of bottom base plate for packaging 16 through bottom base plate for packaging 16 internal circuits, and realization semiconductor chip 21 is connected with external circuit.Bonding wire can adopt gold thread, copper cash or aluminum steel, and bonding technology can adopt hot ultrasonic bonding or thermocompression bonding, and is as shown in Figure 5.The semiconductor chip that the bottom encapsulation is adopted comprises logic chip.
Step D
On the upper and lower surfaces of top layer base plate for packaging, prepare pad; Upper surface at top encapsulation substrate 12 prepares pad 11, prepares pad 13 at the lower surface of top encapsulation substrate 12, and the substrate set inside has interior circuit, and substrate can adopt pcb board or FR4 plate or BT plate, and is as shown in Figure 6.
Step e
Range upon range of being installed on the top layer base plate for packaging of semiconductor chip with the top layer encapsulation; The top layer of present embodiment is encapsulated as three range upon range of dresses; Upper surface at top encapsulation substrate 12 is installed semiconductor chip 2, earlier at top encapsulation substrate 12 upper surfaces coating Heraeus 1, behind the placement semiconductor chip 2; Reflux; Be cooled to room temperature then and can fix chip 2, Heraeus 1 adopts organic polymer elargol or inorganic polymer elargol, and is as shown in Figure 7.Through Heraeus 3 and wall 3a semiconductor chip 4 is fixed on the upper surface of semiconductor chip 2, Heraeus 3 is coated on semiconductor chip 2 upper surfaces, and wall is the bonding wire headspace, and is as shown in Figure 8.Semiconductor chip 6 is fixed on the upper surface of semiconductor chip 4 through Heraeus 5 and wall 5a; Heraeus 5 areas are slightly less than semiconductor chip 4 upper surfaces to expose semiconductor chip 4 upper surface pads; Wall is semiconductor chip 4 bonding wire headspaces, and is as shown in Figure 9.The top encapsulation semiconductor chip adopts memory chip, and selects the number of plies of piling up as required.
Step F
Carry out the lead-in wire bonding of the stacked semiconductor chip of top layer encapsulation; Be connected with pad 11 bondings of top layer base plate for packaging 12 upper surfaces through the upper surface pad 7 of bonding wire 8 semiconductor chip 2; Be connected with pad 11 bondings of top layer base plate for packaging upper surface through the upper surface pad 25 of bonding wire 9 semiconductor chip 4; Be connected with pad 11 bondings of top layer base plate for packaging upper surface through the upper surface pad 26 of bonding wire 10 semiconductor chip 6, shown in figure 10.Bonding wire adopts gold thread, copper cash or aluminum steel, and the bonding mode adopts thermocompression bonding or hot ultrasonic bonding.
Step G
Carry out the top layer sealed package; Through sealant 24 top layer is encapsulated bonding wire 8,9,10 and semiconductor chip 2,4,6 sealed package; Sealant is positioned at top layer base plate for packaging 12 upper surfaces top; Sealant adopts the plastic package process sealing, and sealant can adopt epoxy molding plastic, and is shown in figure 11.
Step H
On the pad of top layer base plate for packaging lower surface, plant soldered ball, carry out the connection between top layer encapsulation and the bottom encapsulation; On top layer base plate for packaging 12 lower surface pad 13, plant soldered ball 15; Scolder can adopt the mode of screen printing technique, plating or vapor deposition to be coated with; Form welded ball array 15 after refluxing, scolder can adopt SnAg, Sn, SnAgCu or PbSn scolder, and is shown in figure 12.Soldered ball 15 on top layer base plate for packaging 12 lower surfaces is welded on the bottom base plate for packaging 16 first surface pads 27, realizes the electrical interconnection between top layer encapsulation and the bottom encapsulation, and is shown in figure 13.
Step I
Carry out the filling sealing between top layer encapsulation and the bottom encapsulation, and on bottom package second surface pad, plant soldered ball; Filling sealing agent 24 between top layer encapsulation and bottom encapsulation, sealant 24 adopts epoxy molding plastics, adopts injection molding way to fill, and is in order to protection welded ball array 15 and bottom packaged chip 21 and go between 23, shown in figure 14.On pad 17, plant soldered ball, form before the soldered ball, earlier scolder is coated on the pad top, the mode of perhaps electroplating through silk-screen printing technique or vapor deposition realizes.Back formation soldered ball refluxes.Scolder adopts SnAg, Sn, SnAgCu or PbSn scolder, and is shown in figure 15.
Embodiment two
Embodiment two is identical with embodiment one; Different is bottom packaged chip 30 active faces down; On active face, make soldered ball 28; Through the mode that hot pressing is welded, hot sonic soldering connects or scolder welds, the pad 31 of soldered ball 28 with bottom base plate for packaging 16 the 3rd surface is interconnected to, realize the transmission of the signal of telecommunication between chip 30 and the substrate 16.After welded ball array 28 and pad 31 welding are accomplished, fill underfill material in the bottom of chip 30, underfill material adopts to be made up of the filler of thermosetting polymer and silicon dioxide, shown in figure 16.
Embodiment three
Embodiment three is identical with embodiment one, and different is after top layer encapsulation making finishes, and on the lower surface pad 13 of top layer base plate for packaging 12, makes soldered ball again, on bottom encapsulation first surface pad 27, makes soldered ball simultaneously.Accomplish after the manufacture craft of soldered ball, adopt welding procedure, the soldered ball on soldered ball on the pad 13 and the pad 27 is linked together through backflow, accomplish the electrical interconnection of top layer encapsulation and bottom encapsulation.Filling sealing agent between top layer encapsulation and bottom encapsulation again is with protection soldered ball 15 and semiconductor chip 21, shown in figure 17 afterwards.
Embodiment four
Embodiment four is identical with embodiment one, and different is to go up 12 making of top layer base plate for packaging to finish, and carries out before the follow-up packaging technology, on the lower surface pad 13 of substrate 11, electroplates a bronze medal post 32, deposits one deck solder layer afterwards again.Simultaneously, after bottom base plate for packaging 16 is made and finished, on bottom base plate for packaging 16 first surface pads 27, electroplate a bronze medal post 34, deposit solder layer afterwards, the material of solder layer can be Sn, SnAg, SnAgCu or PbSn scolder.Adopt reflux technique, solder layer on solder layer on the copper post 32 and the copper post 34 is linked together, accomplish the electrical interconnection of top layer encapsulation and bottom encapsulation.Afterwards, the gap filling sealing agent between top layer encapsulation and bottom encapsulation, shown in figure 18.
Embodiment five
Embodiment five is identical with embodiment one; Different is that semiconductor chip 2 is inverted structure; On the active layer surface pads 35 of semiconductor chip 2, make solder bump 37 earlier; Employing hot pressing is welded or hot sonic soldering connects or the mode of reflow soldering is welded on solder bump 37 on the pad 38 of top layer base plate for packaging upper surface, and the material of salient point 37 can be au bump or Sn, SnAg, SnAgCu or PbSn solder bump.Afterwards, between semiconductor chip 2 and top layer base plate for packaging, fill underfill material 36 again, accomplish and solidify, underfill material is made up of the filler of thermosetting polymer and silicon dioxide, and is shown in figure 19.
Claims (6)
1. stacked semiconductor chip encapsulating structure; Comprise the sealant between welded ball array, top layer encapsulation and the bottom encapsulation between top layer encapsulation, bottom encapsulation, top layer encapsulation and the bottom encapsulation; It is characterized in that said bottom base plate for packaging is provided with a groove, the upper surface of bottom base plate for packaging is a first surface, and the lower surface of bottom base plate for packaging is a second surface; Surface in the bottom base plate for packaging groove is the 3rd surface; The semiconductor chip of bottom encapsulation is arranged in the groove, is equipped with pad on first, second, third surface, and the bottom semiconductor chip links to each other with the 3rd lip-deep pad through bonding wire; Top layer encapsulation by one or several semiconductor chip laminate packaging on the upper surface of top layer base plate for packaging; The upper surface and the lower surface of top layer base plate for packaging are equipped with pad, and the semiconductor chip in the top layer encapsulation links to each other with the pad of top layer base plate for packaging upper surface through bonding wire, and the top layer packed part seals through sealant; Be connected filling sealing agent between top layer base plate for packaging and the bottom base plate for packaging with welded ball array through pad between top layer encapsulation and the bottom encapsulation.
2. stacked semiconductor chip encapsulating structure according to claim 1; It is characterized in that groove on the said bottom base plate for packaging is for trapezoidal; The semiconductor chip of bottom encapsulation is bonded in bottom portion of groove by Heraeus; Perhaps be welded on bottom portion of groove with face-down bonding technique, semiconductor chip is connected through soldered ball with bottom portion of groove.
3. stacked semiconductor chip encapsulating structure according to claim 1; The semiconductor chip that it is characterized in that said top layer encapsulation is the stacked in layers structure; Top layer encapsulates first semiconductor chip and substrate interconnection; The semiconductor chip of top layer encapsulation and bonding wire adopt the sealing of epoxy molding plastic sealant, and the upper surface of top layer base plate for packaging is encapsulated by sealant.
4. stacked semiconductor chip encapsulating structure according to claim 1 is characterized in that being provided with the circuit that is connected usefulness in said bottom base plate for packaging and the top layer base plate for packaging.
5. stacked semiconductor chip encapsulating structure according to claim 1; The second surface that it is characterized in that said bottom base plate for packaging is provided with welded ball array; Welded ball array is that the mode of silk screen printing or plating or vapor deposition is coated with scolder, produces welded ball array through refluxing.
6. stacked semiconductor chip encapsulating structure according to claim 1; It is characterized in that being individual layer or double-deck welded ball array between said top layer encapsulation and the bottom encapsulation; Through backflow top layer encapsulation and bottom encapsulation are linked together; Perhaps deposit solder layer after the lower surface pad of top layer base plate for packaging powers on copper plated pillars; Deposit solder layer after the first surface pad of bottom base plate for packaging powers on copper plated pillars links together top layer base plate for packaging and bottom base plate for packaging through refluxing the electrical interconnection between completion top layer packaging body and the bottom packaging body.
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| CN2012200240478U CN202434509U (en) | 2012-01-18 | 2012-01-18 | Stackable semiconductor chip packaging structure |
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| CN103219324A (en) * | 2012-01-18 | 2013-07-24 | 刘胜 | Stackable semiconductor chip packaging structure and process thereof |
| CN103311192A (en) * | 2013-06-25 | 2013-09-18 | 华进半导体封装先导技术研发中心有限公司 | Thin-gap POP (Package on Package) type packaging structure and packaging method |
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| CN104752491A (en) * | 2013-12-30 | 2015-07-01 | 晟碟半导体（上海）有限公司 | Spacer layer for semiconductor device and semiconductor device |
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- 2012-01-18 CN CN2012200240478U patent/CN202434509U/en not_active Expired - Lifetime
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| CN103219324A (en) * | 2012-01-18 | 2013-07-24 | 刘胜 | Stackable semiconductor chip packaging structure and process thereof |
| WO2013106973A1 (en) * | 2012-01-18 | 2013-07-25 | Liu Sheng | Package-on-package semiconductor chip packaging structure and technology |
| WO2014114003A1 (en) * | 2013-01-28 | 2014-07-31 | Sandisk Information Technology (Shanghai) Co., Ltd. | Semiconductor device including embedded controller die and method of making same |
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| CN103311192A (en) * | 2013-06-25 | 2013-09-18 | 华进半导体封装先导技术研发中心有限公司 | Thin-gap POP (Package on Package) type packaging structure and packaging method |
| CN103426871A (en) * | 2013-07-25 | 2013-12-04 | 上海航天测控通信研究所 | High-density hybrid stacked package structure and production method thereof |
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