CN202434508U - Semiconductor chip stacking and encapsulating structure - Google Patents
Semiconductor chip stacking and encapsulating structure Download PDFInfo
- Publication number
- CN202434508U CN202434508U CN 201120571718 CN201120571718U CN202434508U CN 202434508 U CN202434508 U CN 202434508U CN 201120571718 CN201120571718 CN 201120571718 CN 201120571718 U CN201120571718 U CN 201120571718U CN 202434508 U CN202434508 U CN 202434508U
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- packaging
- base plate
- encapsulating
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a semiconductor chip stacking and encapsulating structure which comprises a plurality of semiconductor chips, an encapsulating substrate and a plastic packaging material. The semiconductor chip stacking and encapsulating structure is characterized in that from top to bottom, an active surface of the lowermost semiconductor chip A faces downwards, the semiconductor chip A is connected to a circuit layer of the encapsulating substrate through a welding ball array, the lower surface of the semiconductor chip A is filled with underfill materials, the semiconductor chip B is bonded on the back of the semiconductor chip A by virtue of a bonding layer, the semiconductor chip C, the semiconductor chip D and the other semiconductor chips above the semiconductor chip D are stacked above the semiconductor chip B in a layered way, bonding pads on the semiconductor chip B, the semiconductor chip C, the semiconductor chip D and the other semiconductor chips above the semiconductor chip D are connected with the circuit layer on the encapsulating substrate through bonding wires, and encapsulating chips of the stacking and encapsulating structure are stacked and arranged in the layered way. The semiconductor chip stacking and encapsulating structure has the advantages of being simple in manufacturing process, meeting the requirement on high encapsulating density, reducing the encapsulating cost, and improving the encapsulating reliability.
Description
Technical field
The utility model relates to a kind of structure of semiconductor device, and particularly a kind of semiconductor chip piles up encapsulating structure.
Background technology
The integrated level of semiconductor product was doubled by the mole law in per 18 months.Along with the deep development of semiconductor industry, Moore's Law receives increasing obstruction, realize that the cost that Moore's Law pays is increasingly high, yet people stops never but for the semiconductor product performance demands.At present, the approach of seeking to enhance product performance through the direction that changes the semiconductor product packing forms is a new direction, and the three-dimensional systematic encapsulation also produces thereupon.
Three-dimensional stacked encapsulation can be in littler space integrated more semiconductor chip, adopt the product of three-dimensional stacked encapsulation to have higher performance, higher reliability, and lower price.At present, adopt the product of three-dimensional stacked encapsulation, for example memory can be realized bigger memory space, and has realized suitability for industrialized production.
Summary of the invention
The purpose of the utility model is to the defective that exists in the prior art, provides a kind of semiconductor chip to pile up encapsulating structure.
The utility model comprises several semiconductor chips; Base plate for packaging, capsulation material; It is characterized in that down by the active surface of the lowermost semiconductor chip A of order up and down; Semiconductor chip A is connected on the circuit layer of base plate for packaging through welded ball array; Semiconductor chip A lower surface filling underfill material to improve the reliability of soldered ball, is bonded in the semiconductor chip A back side by adhesive layer with semiconductor chip B; Semiconductor chip C, semiconductor chip D and above semiconductor chip are stacked in layers above semiconductor chip B, through bonding wire circuit layer on the pad on semiconductor chip B, semiconductor chip C, semiconductor chip D and the above semiconductor chip and the base plate for packaging are linked to each other.
Said semiconductor chip A adopts inverted structure, and semiconductor chip B, semiconductor chip C, semiconductor chip D and above semiconductor chip adopt positive assembling structure.Semiconductor chip A is connected with base plate for packaging through array of solder balls, and the spacing of welded ball array is 0.050～0.500mm, and the soldered ball diameter is 0.050～0.500mm; The composition of soldered ball is Pb/Sn; SnAgCu, SnAg, welded ball array can be distribution fully or part distributes.Through capsulation material all semiconductor chips and bonding wire are sealed on the base plate for packaging.
One deck or multi-lager semiconductor chip can optionally be piled up in the top of said semiconductor chip B, adopt adhesive layer and wall to fix between the semiconductor chip, reserve the space of bonding wire through wall.
Pad, the bonding wire of said all semiconductor chip surface is metals such as gold, copper or aluminium.Adhesive layer can adopt the organic polymer elargol, perhaps the inorganic polymer elargol.Base plate for packaging adopts silicon substrate, ceramic substrate, plastic base.
The technological process that the utility model has the advantages that the utility model is simple, cost is low; Be fit to large-scale industrial production; The three-dimensional stacked encapsulating structure of semiconductor chip of the utility model has the reliability height simultaneously, can satisfy the requirement of high integration to the semiconductor properties of product.
Description of drawings
The semiconductor chip of Fig. 1 the utility model piles up the generalized section of encapsulating structure;
The structural representation of Fig. 2 base plate for packaging;
Fig. 3 adopts flip chip semiconductor chip A to be fixed on the structural representation of base plate for packaging upper surface;
Fig. 4 fills the structural representation of underfill material at semiconductor chip A lower surface;
Fig. 5 is at the fixing structural representation of semiconductor chip B of the upper surface of semiconductor chip A;
The structural representation of Fig. 6 solid semiconductor chip C on the upper surface of semiconductor chip B;
Fig. 7 fixing structural representation of semiconductor chip D on the upper surface of semiconductor chip C;
Fig. 8 fixing structural representation of semiconductor chip E on the upper surface of semiconductor chip D;
The structural representation that Fig. 9 is electrically connected through the bonding wire realization between semiconductor chip and base plate for packaging;
Figure 10 is through the structural representation of plastic package process with semiconductor chip and bonding wire sealing;
Figure 11 makes the sketch map of welded ball array at the base plate for packaging lower surface;
The structural representation of Figure 12 embodiment two;
The structural representation of Figure 13 embodiment three.
Among the figure: 1 semiconductor chip A; 2 semiconductor chip B; 3 adhesive layers; 4 epoxy molding plastics; 5 inserts; 6 base plate for packaging; The 6c interconnection circuit; The pad of 7 base plate for packaging upper surfaces; The pad of 8 chip B; 9 bonding wires; The pad of 10 base plate for packaging upper surfaces; 11 base plate for packaging lower surface pad; The welded ball array of 12 base plate for packaging lower surfaces; 13 semiconductor chip A lower surface array of solder balls; The pad of 14 base plate for packaging upper surfaces; 15 bonding wires; The pad of 16 chip C; 17 adhesive layers; The 17a wall; 18 semiconductor chip C; 19 adhesive layers; The 19a wall; 20 semiconductor chip D; 21 adhesive layers; The 21a wall; 22 semiconductor chip E; 23 bonding wires; The pad of 24 chip D; 25 bonding wires; The pad of 26 chip E.
Embodiment
Embodiment one
Further specify present embodiment below in conjunction with accompanying drawing:
Pressing up and down, the active surface of the lowermost semiconductor chip A of order is connected to semiconductor chip A on the circuit layer of base plate for packaging 6 through welded ball array-13 down.Said base plate for packaging 6 adopts silicon substrate, ceramic substrate, plastic base.The spacing of welded ball array 13 is 0.050～0.500mm, and the soldered ball diameter is 0.050～0.500mm, and the composition of soldered ball is Pb/Sn, and SnAgCu, SnAg, welded ball array can be distribution fully or part distributes.Semiconductor chip A lower surface filling underfill material 5 is to improve the reliability of soldered ball 13.By adhesive layer 3 semiconductor chip B is bonded in the semiconductor chip A back side; Semiconductor chip C, semiconductor chip D and above semiconductor chip are stacked in layers above semiconductor chip B; Semiconductor chip A adopts inverted structure, and semiconductor chip B, semiconductor chip C, semiconductor chip D and semiconductor chip E adopt positive assembling structure.Through bonding wire pad 7, pad 10 on the circuit layer on the pad 8 on semiconductor chip B, semiconductor chip C, semiconductor chip D and the semiconductor chip E, pad 16, pad 24, pad 26 and the base plate for packaging 6 are linked to each other, the packaged chip of stack package structure is stacked in layers and arranges.Can optionally pile up one deck or multi-lager semiconductor chip more than the semiconductor chip B, present embodiment piles up the three-layer semiconductor chip on semiconductor chip B.Adopt adhesive layer 3,17,19,21 and wall 17a, 19a, 21a to fix between the semiconductor chip, adhesive layer 3,17,19,21 can adopt the organic polymer elargol, perhaps the inorganic polymer elargol.Reserve the space of bonding wire through wall 17a, 19a, 21a.Capsulation material is sealed in all semiconductor chips and bonding wire on the base plate for packaging.The pad of all semiconductor chip surface, bonding wire are that gold, copper or aluminum metallic material are made.
Present embodiment realizes that specifically the processing step of the three-dimensional stacked encapsulation of semiconductor chip is following:
(1) as shown in Figure 2; The used base plate for packaging 6 of preparation encapsulation; Material therefor can be silicon substrate, ceramic substrate, plastic base such as BT; FR4, composite material such as AlSiC, MCPCB, wherein the lower surface 6b of the upper face 6a of base plate for packaging and base plate for packaging comprises the pad of the interconnect function that electrifies, base plate for packaging inside comprises inner multilayer interconnection circuit 6c.
(2) as shown in Figure 3; Salient point 13 under the preparation semiconductor chip A lower surface; Adopt then scolder welding, hot pressing welding, or hot sonic soldering mode such as connect and chip lower surface salient point be welded on the pad 14 of base plate for packaging 6 upper surface 6a; Semiconductor chip A links to each other through pad on array of solder balls 13 and the base plate for packaging 6, and 6 internal circuit 6c link to each other with base plate for packaging lower surface pad 11 via base plate for packaging.
(3) as shown in Figure 4, the filling underfill material.At the peripheral injection of semiconductor chip A lower surface inserts 5, inserts 5 is made up of the filler of thermosetting polymer and silicon dioxide.Because the capillarity in slit between semiconductor chip A lower surface and the base plate for packaging 6, filler is inhaled into the space between semiconductor chip A and base plate for packaging 6 upper surfaces.Be heated to then about 130 ℃, keep accomplishing in 3～4 hours and solidify.
(4) as shown in Figure 5, through adhesive layer 3 semiconductor chip B is fixed on the surface of semiconductor chip A, adhesive can adopt macromolecule paster material or scolder.
(5) as shown in Figure 6, through adhesive layer 17 and wall 17a semiconductor chip C is fixed on the upper surface of semiconductor chip B, wall 17a is the bonding wire headspace.
(6) as shown in Figure 7, through adhesive layer 19 and wall 19a chip D is fixed on the upper surface of chip C, wall 19a is the bonding wire headspace.
(7) through adhesive layer 21 and wall 21a semiconductor chip E is fixed on the upper surface of semiconductor chip D like Fig. 8, wall 21a is the bonding wire headspace.
(8) as shown in Figure 9, the pad 8,16,24 of semiconductor chip B, semiconductor chip C, semiconductor chip D and semiconductor chip E upper surface and 26 and base plate for packaging 6 between the pad 7, pad 10 welding bonding wire 9,15,23,25 realize being electrically connected.The bonding wire material can adopt gold thread, aluminum steel or copper cash, and bonding wire craft can adopt ultrasonic bonding, thermocompression bonding or hot ultrasonic bonding technology.
(9) shown in figure 10, through plastic package process all semiconductor chips and bonding wire are sealed, encapsulant 4 can be selected epoxy molding plastic (EMC) etc. for use.
(10) shown in figure 11, preparation welded ball array 12 on pad 11, scolder can adopt plumber's solder, golden tin solder or Sn-Ag-Cu lead-free scolder.Salient point preparation technology can adopt silk-screen printing technique, vapor deposition or electroplate, and reflux technique forms welded ball array 12 then.
Embodiment two
Embodiment two is identical with embodiment one, and different is that present embodiment has adopted the two-layer packing forms that piles up, referring to Figure 12.
Embodiment three
Embodiment three is identical with embodiment one, and different is the packing forms that present embodiment adopts three level stack, referring to Figure 13.
Claims (5)
1. a semiconductor chip piles up encapsulating structure; Comprise several semiconductor chips; Base plate for packaging, capsulation material; It is characterized in that semiconductor chip A being connected on the circuit layer of base plate for packaging semiconductor chip A lower surface filling underfill material through welded ball array down by the active surface of the lowermost semiconductor chip A of order up and down; By adhesive layer semiconductor chip B is bonded in the semiconductor chip A back side; Semiconductor chip C, semiconductor chip D and above semiconductor chip are stacked in layers above semiconductor chip B, through bonding wire circuit layer on the pad on semiconductor chip B, semiconductor chip C, semiconductor chip D and the above semiconductor chip and the base plate for packaging are linked to each other, and the packaged chip of stack package structure is stacked in layers and arranges.
2. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that said semiconductor chip A is an inverted structure, and semiconductor chip B, semiconductor chip C, semiconductor chip D and above semiconductor chip are positive assembling structure.
3. a kind of semiconductor chip according to claim 1 piles up encapsulating structure; It is characterized in that said semiconductor chip A is connected with base plate for packaging through array of solder balls; The spacing of welded ball array is 0.050～0.500mm, adopts Pb/Sn, SnAgCu; The soldered ball diameter that the SnAg composition is made is 0.050～0.500mm, and welded ball array is distribution fully or part distributes.
4. a kind of semiconductor chip according to claim 1 piles up encapsulating structure; One deck or multi-lager semiconductor chip are piled up in the top that it is characterized in that said semiconductor chip B; Fix through adhesive layer and wall between the semiconductor chip, reserve the space of bonding wire through wall.
5. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that said capsulation material is sealed in all semiconductor chips and bonding wire on the base plate for packaging.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120571718 CN202434508U (en) | 2011-12-31 | 2011-12-31 | Semiconductor chip stacking and encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120571718 CN202434508U (en) | 2011-12-31 | 2011-12-31 | Semiconductor chip stacking and encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202434508U true CN202434508U (en) | 2012-09-12 |
Family
ID=46783934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120571718 Expired - Lifetime CN202434508U (en) | 2011-12-31 | 2011-12-31 | Semiconductor chip stacking and encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202434508U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187404A (en) * | 2011-12-31 | 2013-07-03 | 刘胜 | Semiconductor chip stacking and packaging structure and process thereof |
| CN107123623A (en) * | 2013-03-04 | 2017-09-01 | 日月光半导体制造股份有限公司 | Semiconductor package assembly and a manufacturing method thereof including antenna substrate |
-
2011
- 2011-12-31 CN CN 201120571718 patent/CN202434508U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187404A (en) * | 2011-12-31 | 2013-07-03 | 刘胜 | Semiconductor chip stacking and packaging structure and process thereof |
| CN107123623A (en) * | 2013-03-04 | 2017-09-01 | 日月光半导体制造股份有限公司 | Semiconductor package assembly and a manufacturing method thereof including antenna substrate |
| US11664580B2 (en) | 2013-03-04 | 2023-05-30 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna substrate and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102867800B (en) | Functional chip is connected to packaging part to form package on package | |
| CN104229720B (en) | Chip layout and the method for manufacturing chip layout | |
| TWI355061B (en) | Stacked-type chip package structure and fabricatio | |
| US8138023B2 (en) | Method for forming laminated structure and method for manufacturing semiconductor device using the method thereof | |
| US7649248B2 (en) | Stack package implementing conductive support | |
| KR101190920B1 (en) | Stacked semiconductor package and method of manufacturing thereof | |
| CN103187404A (en) | Semiconductor chip stacking and packaging structure and process thereof | |
| TW201248808A (en) | Semiconductor device and manufacturing method thereof, and semiconductor module using the same | |
| CN101477979B (en) | Multi-chip encapsulation body | |
| CN103219324A (en) | Stackable semiconductor chip packaging structure and process thereof | |
| CN202394958U (en) | Wafer-level semiconductor packaging structure | |
| CN202434509U (en) | Stackable semiconductor chip packaging structure | |
| CN103904066A (en) | Flip chip stacking packaging structure and packaging method | |
| CN101872749B (en) | Recess chip packaging structure and laminated packaging structure using same | |
| CN101930956B (en) | Chip packaging structure and manufacturing method thereof | |
| CN202434508U (en) | Semiconductor chip stacking and encapsulating structure | |
| CN104681499B (en) | Package stack structure and method for fabricating the same | |
| CN104766838A (en) | Package stack structure and method for fabricating the same | |
| CN202394859U (en) | Semiconductor encapsulating structure | |
| CN103915423A (en) | Three-dimensional stack-packaging structure and method for chips | |
| CN205376514U (en) | Three -dimensional poP stacked package structure | |
| CN104934379A (en) | Package stack structure and method for fabricating the same | |
| CN105428251A (en) | Stacked packaging method for semiconductor | |
| US8558380B2 (en) | Stack package and method for manufacturing the same | |
| TWI387068B (en) | Cavity chip package structure and package-on-package using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120912 |
|
| CX01 | Expiry of patent term |