TWI387068B - Cavity chip package structure and package-on-package using the same - Google Patents

Description

Pocket chip package structure and stacked package structure using recessed chip package structure

The present invention relates to a package structure for a semiconductor wafer, and more particularly to a recessed chip package structure.

The development of multi-chip module packaging technology has been promoted for functional requirements such as mobility and high performance of electronic products. The multi-chip modular packaging technology combines two or more semiconductor wafers into a single package structure, whereby the multi-chip package is packaged into a single package structure, which not only reduces the size of the original integrated circuit package. It is a volume, and the multi-chip package structure can reduce the length of the connection line between the wafers, reduce the signal delay, and access time to improve the electrical function.

However, the conventional multi-chip module is disposed on a flat substrate, and after being wire-bonded and encapsulated, a thick package is formed. Although the structure of the multi-chip module can reduce the volume required for the original individual wafers, the stacked multi-chips still have limited thickness, which makes the use of multi-chip modules limited in size, resulting in high development. Performance of mobile electronic devices.

In addition, in the foregoing multi-wafer module, each of the wafers is electrically connected to the circuit of the planar substrate by a metal wire. However, the wafer located near the top of the multi-chip module is prone to affect the quality of its signal transmission due to its long metal line.

In view of the above problems, it is necessary to develop a package structure that can further reduce the size and cause poor signal transmission for functional requirements such as mobility and high performance of electronic products.

The present invention discloses a recessed chip package structure, by which the mobility of an electronic product using the structure can be increased and the performance of the electronic product can be improved without causing poor signal transmission.

A first embodiment of the recessed chip package structure of the present invention includes a first wafer, a substrate, and a plurality of connection points. The first wafer includes a first active surface, a first back surface, and a plurality of first pads disposed on the first active surface. The substrate includes a first surface and a second surface opposite to the first surface, wherein the first surface has a recess, and the first wafer is disposed in the recess. The connection points are disposed on the surface of the first surface and the bottom of the recess and are electrically connected to the plurality of first pads.

An embodiment of the stacked package structure of the present invention comprises a first package component and a second package component of the recessed chip package structure of the first embodiment. The first package component further includes a plurality of second pads disposed on the second surface of the substrate in the first package component and a plurality of second metal conductive materials respectively disposed on the plurality of second pads, for example a solder ball or a bump, and the second package component is fixed to the plurality of second metal conductive materials and electrically connected to the first package component.

A second embodiment of the recessed chip package structure of the present invention includes a plurality of wafers, a substrate, and a plurality of connection points. Each of the plurality of wafers includes an active surface, a back surface, and a plurality of pads disposed on the active surface. The substrate includes a first surface and a second surface opposite to the first surface, wherein the first surface has a recess and at least one step surface surrounding the recess, and the plurality of wafer stacks are received in the substrate Inside the pocket. The connection points are disposed on the surface of the first surface, the bottom of the recess, and the step surface, wherein the pads of the wafer are electrically connected to the connection points.

An embodiment of the stacked package structure of the present invention comprises a first package component and a second package component of the recessed chip package structure of the second embodiment. The first package component further includes a plurality of second pads disposed on the second surface of the substrate in the first package component and a plurality of second metal conductive materials respectively disposed on the plurality of second pads, for example a solder ball or a bump, and the second package component is fixed to the plurality of second metal conductive materials and electrically connected to the first package component.

1 shows a schematic view of a wire bonded die pad package structure 10a of a first embodiment of the present invention. The recessed chip package structure 10a disclosed in this embodiment comprises a first wafer 12, a second wafer 14, an adhesive layer 16, and a substrate 18a. The substrate 18a includes a first surface 20, a second surface 22 opposite to the first surface 20, and a recess 24. The recess 24 is disposed on the first surface 20 for configuring a package wafer. The height of the recessed chip package structure 10a is lowered to achieve the purpose of volume reduction. A plurality of connection points 26a and 26b and a solder pad 28 are further disposed on the first surface 20, and a corresponding metal conductive material 30, such as a solder ball or a bump, may be formed on the solder pad 28. A plurality of pads 38 may be further disposed on the second surface 22 of the substrate 18a.

The first wafer 12 and the second wafer 14 respectively include an active surface (122 and 142) and a back surface (124 and 144), and the active surfaces (122 and 142) have a plurality of pads (126 and 146) thereon. The first wafer 12 and the second wafer 14 are disposed in a stacked manner in the recessed chip package structure 10a, wherein the first wafer 12 is attached to the bottom 32 of the recess 24, and then the adhesive layer 16 is disposed on the first On the active surface 122 of a wafer 12, then the second wafer 14 is disposed on the adhesive layer 16. The electrical connection of the recessed chip package structure 10a is performed by the pads 126 of the first wafer 12 and the pads 146 of the second wafer 14 corresponding to the connection points on the first surface 20 26a and 26b are electrically connected.

In this embodiment, the depth d of the recess 24 is determined according to different designs. In other words, the depth d of the recess 24 is better for the first wafer 12, the second wafer 14 and the substrate 18a. Sexual performance. In order to consider the electrical performance, a bump 36a may be disposed on the connection point 26b corresponding to the pad 146 of the second wafer 14, and the bumps may be, for example, stud bumps or other metal bumps. In another embodiment, the recessed chip package structure 10a does not need to include the bumps 36a.

The first wafer 12 and the second wafer 14 are adhered by an adhesive layer 16. In the embodiment of the present invention, the adhesive layer 16 can cover approximately the active surface 122 of the entire first wafer 12, and a portion of the wires 34 connected to the bonding pads 126 are buried therein. The first wafer 12 and the second wafer 14 are combined by first attaching the adhesive layer 16 to the back surface 144 of the second wafer 14. After the first wafer 12 is completed, the adhesive layer 16 faces the first wafer. The second wafer 14 is attached thereto in a manner of 12. In one embodiment, the adhesive layer 16 can be a film-on-film (FOW) layer that reduces the package height and provides wire protection for improved wire stability. The combination of the first chip and the second chip may be a combination of a memory chip and a memory chip, a combination of a memory chip and a control chip, a combination of a memory chip and a special-purpose integrated circuit ASIC chip, and a memory. The combination of a body chip and a DSP chip; wherein the memory chip can be in the form of SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM.

Fig. 2 is a view showing the wire bonding chip package structure 10b of the second embodiment of the present invention. The recessed chip package structure 10b disclosed in the second embodiment of the present invention has a similar structure to the recessed chip package structure 10a disclosed in the first embodiment of the present invention, but in the second embodiment, the first surface 20 of the substrate 18b is provided. The upper pocket 24 has a larger bottom area and a deeper depth d' than the recess 24 in the first embodiment, so that the second wafer surface can be aligned with one of the surfaces of the substrate. Similarly, the depth d' of the recess 24 can be designed to provide a better electrical performance of the first wafer, the second wafer 14, and the substrate. The pad 126 on the first wafer 12 is connected to the connection point 26a provided on the bottom 32 of the cavity 24 by a corresponding wire 34. For the electrical performance, the connection point 26a on the bottom 32 may be provided with a bump. 36b, such as a junction bump or other metal bump. In another embodiment, the recessed chip package structure 10b does not need to include the bumps 36b.

Fig. 3 is a view showing a recessed chip package structure 10c by wire bonding according to a third embodiment of the present invention. The recessed chip package structure 10c disclosed in the third embodiment of the present invention comprises a first wafer 12, a second wafer 14, a third wafer 15, a plurality of adhesive layers 16, and a substrate 18c. The first wafer 12, the second wafer 14 and the third wafer 15 respectively comprise an active surface (122, 142 and 152), and each of the active surfaces (122, 142 and 152) comprises a plurality of pads (126, 146). And 156). The substrate 18c includes a first surface 20, a second surface 22 opposite to the first surface 20, and a recess 24, and the recess 24 is disposed on the first surface 20. The first wafer 12, the second wafer 14 and the third wafer 15 are stacked and received in the recess 24, wherein the active surfaces (122, 142 and 152) of the first wafer 12, the second wafer 14 and the third wafer 15 Each of them faces away from the bottom 32 of the pocket 24 and an adhesive layer 16 is disposed between two adjacent wafers. Since the first wafer 12, the second wafer 14 and the third wafer 15 are arranged one on top of the other, the pads (126, 146 and 156) are arranged in a stepwise manner for shortening the connection to the pads (126, 146 and 156). The length of the wire 34, the first surface 20 may be provided with a plurality of stepped surfaces (40a and 40b) surrounding the cavity 24, and corresponding to the pads (126, 146) on each of the step surfaces (40a and 40b). The connection points (26a and 26b) and the first surface 20 are also provided with connection points 26c corresponding to the pads 156, thereby achieving the purpose of shortening the length of the wires 34. The height (or number of steps) of each step surface (40a and 40b) can be matched with the corresponding height (or number) of layers of the stacked wafers, so that the pads (126, 146 and 156) of the stacked wafers can be A preferred electrical connection path is connected to the corresponding connection point (26a, 26b and 26c). A plurality of pads 28 may be further disposed on the first surface 20, and the corresponding metal conductive materials 30 may be formed on the pads 28, such as solder balls or bumps. A plurality of pads 38 may be additionally disposed on the second surface 22 of the substrate 18c.

4 is a schematic view showing a flip chip bonded package structure 10d according to an embodiment of the present invention. The recessed chip package structure 10d disclosed in this embodiment includes a first wafer 42 and a substrate 18d. The substrate 18d includes a first surface 20, a second surface 22 opposite to the first surface 20, and a recess 24 disposed on the first surface 20. The first wafer 42 includes an active surface 422 having a plurality of pads 426. The bottom of the recess 24 has a plurality of connecting points 26a. The connecting points 26a correspond to the pads 426, and the corresponding connecting points 26a and the pads 426 are electrically connected by a bump 44. In this embodiment, the bumps 44 are tin-lead bumps, lead-free bumps, junction bumps, gold bumps, metal bumps, elastic bumps, or composite metal bumps. A plurality of pads 28 may be additionally disposed on the first surface 20, and the corresponding metal conductive materials 30 may be formed on the pads 28, such as solder balls or bumps. A plurality of pads 38 may be further disposed on the second surface 22 of the substrate 18d.

5 and 6 show schematic views of flip chip bonded recessed chip package structures (10e and 10f) of other embodiments of the present invention. The recessed chip package structures (10e and 10f) illustrated in Fig. 5 and circle 6 have a similar configuration to the recessed chip package structure 10d illustrated in Fig. 4, but the technical methods of the flip chip bonding of the three are different. In the recessed chip package structure 10e illustrated in FIG. 5, the bumps 44 of the pads 426 of the first wafer 42 and the connection points 26a of the bottoms of the recesses are copper pillars, and the copper pillars protruding from the solder pads 426 Soldering to the corresponding connection point 26a, preferably a solder material 27a (element above the connection point 26a) is utilized to enhance bonding. In other embodiments, the surface of the copper post may also be provided with a metal layer composed of gold, and the copper post 44 is bonded to the joint 26a by thermocompression or ultrasonic bonding without the need for the solder material 27a. In the recessed chip package structure 10f illustrated in FIG. 6, the bumps 44 of the pads 426 of the first wafer 42 and the connection points 26a of the bottoms of the recesses are gold bumps.

Fig. 7 is a view showing a multi-wafer stacked pit chip package structure 10g of the first embodiment of the present invention. The recessed chip package structure 10g disclosed in this embodiment includes a first wafer 42, a second wafer 46, and a substrate 18e. The substrate 18e includes a first surface 20, a second surface 22 opposite to the first surface 20, and a recess 24. The recess 24 is disposed on the first surface 20 and has a plurality of connection points on the bottom portion 32 thereof. 26a. The active surface 422 of the first wafer 42 includes a plurality of pads 426 corresponding to the connection points 26a, wherein the connection points 26a and the corresponding pads 426 are electrically connected by flip chip technology. The back surface 464 of the second wafer 46 is attached to the back surface 424 of the first wafer 42. The active surface 462 includes a plurality of solder pads 466. The solder pads 466 are electrically connected to the substrate 18e by a wire bonding technique. A surface 20 is circumferentially disposed at a junction 26b of the pocket 24. The first surface 20 further includes a plurality of pads 28, and the corresponding metal conductive material 30 is formed on the pads 28. A plurality of pads 38 may be disposed on the second surface 22 of the substrate 18e.

Figure 8 is a view showing a multi-wafer stacked recessed chip package structure 10h of the second embodiment of the present invention. The recessed chip package structure 10h disclosed in this embodiment includes a first wafer 42, a second wafer 48, and a substrate 18f. The substrate 18f includes a first surface 20, a second surface 22 opposite to the first surface 20, and a recess 24. The recess 24 is disposed on the first surface 20 and has a plurality of connection points at the bottom portion 32 thereof. 26a. A stepped surface 40a is disposed around the recess 24, wherein the stepped surface 40a is provided with a plurality of connecting points 26b. The active surface 422 of the first wafer 42 includes a plurality of pads 426 corresponding to the connection points 26a, wherein the connection points 26a and the corresponding pads 426 are electrically connected by flip chip technology. The active surface 482 of the second wafer 48 is provided with a plurality of pads 486 corresponding to the connection points 26b. The connection points 26b and the corresponding pads 486 are electrically connected by flip chip technology. The first surface 20 further includes a plurality of pads 28, and the corresponding metal conductive material 30 is formed on the pads 28. A plurality of pads 38 may be disposed on the second surface 22 of the substrate 18f. The combination of the first chip and the second chip may be a combination of a memory chip and a memory chip, a combination of a memory chip and a control chip, a combination of a memory chip and a special-purpose integrated circuit ASIC chip, and a memory. The combination of a body chip and a DSP chip; wherein the memory chip can be in the form of SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM.

Figure 9 is a view showing a multi-wafer stacked recessed chip package structure 10i according to a third embodiment of the present invention. The recessed chip package structure 10i disclosed in this embodiment includes a first wafer 42, a second wafer 48, a third wafer 50, and a substrate 18f. The substrate 18f includes a first surface 20, a second surface 22 opposite to the first surface 20, and a recess 24. The recess 24 is circumferentially provided with a stepped surface 40a. The first wafer 42 and the second wafer 48 are electrically connected to the bottom of the cavity 24 and the step surface 40a by flip chip technology, respectively, as shown in the embodiment of FIG. The third wafer 50 is attached to the second wafer 48 with its back surface 504, and the bonding pads 506 on the active surface 502 of the third wafer 50 are electrically connected to the connection point 26c on the first surface 20 by a wire bonding technique. The connection point 26c may further be provided with, for example, bumps 36b, such as junction bumps or tin-lead bumps or lead-free bumps, to enhance electrical connection characteristics. In another embodiment, the recessed chip package structure 10i may not need to include the bumps 36b.

The first surface 20 further includes a plurality of pads 28, and the corresponding metal conductive material 30 is formed on the pads 28. A plurality of pads 38 may be disposed on the second surface 22 of the substrate 18f.

Figure 10 is a view showing a multi-wafer stacked recessed chip package structure 10j of a fourth embodiment of the present invention. The recessed chip package structure 10j disclosed in this embodiment includes a first wafer 42, a second wafer 48, a third wafer 50, a fourth wafer 52, an adhesive layer 54, and a substrate 18g. The substrate 18g includes a first surface 20, a second surface 22 opposite the first surface 20, and a recess 24. The recess 24 is peripherally provided with a plurality of stepped surfaces 40a and 40b. The first wafer 42 and the second wafer 48 are electrically connected to the bottom of the recess 24 and the stepped surface 40a by flip chip technology, respectively. The third wafer 50 is attached to the second wafer 48 as shown in FIG. 9 and electrically connected to the connection point 26c on the step surface 40b by a wire bonding technique, and the adhesive layer 54 covers a portion of the third wafer. . In this embodiment, the adhesive layer 54 can be a film-on-line (FOW) layer, which can reduce the package height and provide wire protection to improve the stability of the wire. The connection point 26c may further be provided with, for example, bumps 36b such as junction bumps or tin-lead bumps or lead-free bumps to enhance electrical connection characteristics. The fourth wafer 52 is adhered to the active surface 502 of the third wafer 50 by an adhesive layer 54 and electrically connected to the connection point 26d on the first surface 20 by a wire bonding technique. The first surface 20 further includes a plurality of pads 28, and the corresponding metal conductive material 30 is formed on the pads 28. A plurality of pads 38 may be disposed on the second surface 22 of the substrate 18g. The combination of the first wafer, the second wafer, the third wafer and the fourth wafer may be a combination of a memory wafer and a memory wafer, a combination of a memory wafer and a control wafer, a memory chip and a special purpose product. A combination of a body circuit ASIC chip, a combination of a memory chip and a DSP chip; wherein the memory chip can be in the form of SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM.

Figure 11 is a view showing a package on package 60a having a recessed chip package structure according to a first embodiment of the present invention. The stacked package structure 60a of the present embodiment includes a first package component 62a and a second package component 64. The first package component 62a is provided with a recessed chip package structure including a wafer 66 and a substrate 18a. The first surface 20 of the substrate 18a has a recess 24, and the wafer 66 is disposed on the recess 24, and the connection of the solder pad 664 on the active surface 662 of the wafer 66 to the first surface 20 is electrically connected by a wire bonding technique. Point 26a, preferably, the pad 664 can be further provided with a bump, such as a wire bump, to improve wire bonding capability and electrical connection characteristics. In another embodiment, the recessed chip package structure 10j may not need to include the bump.

The second surface 22 of the substrate 18a includes a plurality of pads 68, and the pads 68 are respectively provided with a plurality of corresponding metal conductive materials 70. In this embodiment, the second package component 64 has the same structure as the first package 62a, and details are not described herein. The first package component 62a and the second package component 64 are electrically connected by using the metal conductive materials 70. In other embodiments, the structure of the second package may also be different from the first package 62a.

Fig. 12 is a view showing a laminated package structure 60b having a recessed chip package structure according to a second embodiment of the present invention. The stacked package structure 60b of the present embodiment includes a first package component 62b and a second package component 64. The first package component 62b and the second package component 64 are provided with a recessed chip package structure 10c as shown in FIG. 3, and the pad 38 on the second surface 22 is provided with a plurality of corresponding metal conductive materials 70. The first package component 62b and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62b.

Figure 13 is a view showing a laminated package structure 60c having a recessed chip package structure according to a third embodiment of the present invention. The stacked package structure 60c of the present embodiment includes a first package component 62c and a second package component 64. The first package component 62c and the second package component 64 are provided with a recessed chip package structure 18d as shown in FIG. 4, and the pad 38 on the second surface 22 is provided with a plurality of corresponding plurality of metal conductive materials 70. The first package component 62c and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62c.

Fig. 14 is a view showing a laminated package structure 60d having a recessed chip package structure according to a fourth embodiment of the present invention. The stacked package structure 60d of the present embodiment includes a first package component 62d and a second package component 64. The first package component 62d and the second package component 64 are provided with a recessed chip package structure 10e as shown in FIG. 5, and the pad 38 on the second surface 22 is provided with a plurality of corresponding plurality of metal conductive materials 70. The first package component 62d and the second package component 64 are electrically connected by using the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62d.

Figure 15 is a view showing a laminated package structure 60e having a recessed chip package structure according to a fifth embodiment of the present invention. The stacked package structure 60e of the present embodiment includes a first package component 62e and a second package component 64. The first package component 62e and the second package component 64 are provided with a recessed chip package structure 10f as shown in FIG. 6, and the pad 38 on the second surface 22 is provided with a plurality of corresponding plurality of metal conductive materials 70. The first package component 62e and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62d.

Fig. 16 is a view showing a laminated package structure 60f having a recessed chip package structure according to a sixth embodiment of the present invention. The stacked package structure 60f of the present embodiment includes a first package component 62f and a second package component 64. The first package component 62f and the second package component 64 are provided with a recessed chip package structure 10g as shown in FIG. 7, and the pad 38 on the second surface 22 is provided with a plurality of corresponding plurality of metal conductive materials 70. The first package component 62f and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62f.

Fig. 17 is a view showing a laminated package structure 60g having a recessed chip package structure according to a seventh embodiment of the present invention. The stacked package structure 60g of the present embodiment includes a first package component 62g and a second package component 64. The first package component 62g and the second package component 64 are provided with a recessed chip package structure 10h as shown in FIG. 8, and the pad 38 on the second surface 22 of the substrate 18f is provided with a plurality of corresponding plurality of metal conductive materials. 70. The first package component 62g and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62f.

Fig. 18 is a view showing a laminated package structure 60h having a recessed chip package structure according to an eighth embodiment of the present invention. The stacked package structure 60h of the present embodiment includes a first package component 62h and a second package component 64. The first package component 62h and the second package component 64 are provided with a recessed chip package structure 10i as shown in FIG. 9, and the pad 38 on the second surface 22 of the substrate 18f is provided with a plurality of corresponding plurality of metal conductive materials. 70. In the stacked package structure of another embodiment, the first package component 62h may not need to include the bump 36b on the connection point.

The first package component 62h and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62f.

Fig. 19 is a view showing a laminated package structure 60i having a recessed chip package structure according to a ninth embodiment of the present invention. The stacked package structure 60i of the present embodiment includes a first package component 62i and a second package component 64. The first package component 62i and the second package component 64 are provided with a recessed chip package structure 10j as shown in FIG. 10, and the pad 38 on the second surface 22 of the substrate 18g is provided with a plurality of corresponding plurality of metal conductive materials. 70. The first package component 62i and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62f. In the stacked package structure of another embodiment, the first package component 62i may not need to include the bumps 36b on the connection point.

In one embodiment, the second package component 64 disclosed in FIGS. 11-19 may also have a recessed chip package structure. The combination of the first package component and the second package component may be a combination of a memory chip package component and a memory chip package component, a combination of a memory chip package component and a control chip package component, and a memory chip package component. Combination with a special purpose integrated circuit ASIC chip package component, a combination of a memory chip package component and a DSP chip package component; wherein the memory chip package component can be in the form of SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM .

In the above embodiments, the material of the substrate may be organic material, ceramic, glass, enamel or metal.

In summary, the recessed chip package structure disclosed in the present invention can reduce the height after chip packaging, thereby increasing the mobility of the electronic product using the structure. The design of the preferred electrical connection path in the recessed chip package structure can improve the performance of the electronic product without causing poor signal transmission. At the same time, the present invention discloses that the adhesive layer can be a film-on-line (FOW) layer, thereby reducing the package height and providing wire protection to improve the stability of the wire.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

10a to 10j. . . Pocket chip package structure

12. . . First wafer

14. . . Second chip

15. . . Third chip

16. . . Adhesive layer

18a to 18g. . . Substrate

20. . . First surface

twenty two. . . Second surface

twenty four. . . Pocket

26a, 26b, 26c, 26d. . . Junction

27a. . . Solder material

28. . . Solder pad

30. . . Metal conductive material

32. . . bottom

34. . . wire

36a, 36b. . . Bump

38. . . Solder pad

40a, 40b. . . Step surface

42. . . First wafer

44. . . Bump

46, 48. . . Second chip

50. . . Third chip

52. . . Fourth chip

54. . . Adhesive layer

60a to 60i. . . Cascaded package structure

62a to 62i. . . First package component

64. . . Second package component

66. . . Wafer

68. . . Solder pad

70. . . Metal conductive material

122, 142, 152, 422, 462, 502. . . Active surface

124, 144, 444, 504. . . back

126, 146, 156, 426, 466, 486, 506. . . Solder pad

662. . . Active surface

664. . . Solder pad

1 is a schematic view showing a wire-bonded recessed chip package structure of a first embodiment of the present invention;

2 is a schematic view showing a wire-bonded recessed chip package structure according to a second embodiment of the present invention;

3 is a schematic view showing a recessed chip package structure using wire bonding according to a third embodiment of the present invention;

4 is a schematic view showing a flip chip wafer package structure of a flip chip bonding according to an embodiment of the present invention;

5 and FIG. 6 are schematic diagrams showing a flip chip bonded package structure of another embodiment of the present invention;

7 is a schematic view showing a recessed chip package structure of a multi-wafer stack according to a first embodiment of the present invention;

8 is a schematic view showing a recessed chip package structure of a multi-wafer stack according to a second embodiment of the present invention;

9 is a schematic view showing a recessed chip package structure of a multi-wafer stack according to a third embodiment of the present invention;

10 is a schematic view showing a recessed chip package structure of a multi-wafer stack according to a fourth embodiment of the present invention;

11 is a schematic view showing a stacked package structure of a recessed chip package structure according to a first embodiment of the present invention;

12 is a schematic view showing a stacked package structure of a recessed chip package structure according to a second embodiment of the present invention;

13 is a schematic view showing a stacked package structure of a recessed chip package structure according to a third embodiment of the present invention;

14 is a schematic view showing a stacked package structure of a recessed chip package structure according to a fourth embodiment of the present invention;

15 is a schematic view showing a stacked package structure of a recessed chip package structure according to a fifth embodiment of the present invention;

16 is a schematic view showing a stacked package structure of a recessed chip package structure according to a sixth embodiment of the present invention;

Figure 17 is a view showing a laminated package structure of a recessed chip package structure according to a seventh embodiment of the present invention;

Figure 18 is a view showing a stacked package structure of a recessed chip package structure according to an eighth embodiment of the present invention;

Figure 19 is a view showing a laminated package structure of a recessed chip package structure according to a ninth embodiment of the present invention.

10a. . . Pocket chip package structure

12. . . First wafer

14. . . Second chip

16. . . Adhesive layer

18a. . . Substrate

20. . . First surface

twenty two. . . Second surface

twenty four. . . Pocket

26a, 26b. . . Junction

28. . . Solder pad

30. . . Metal conductive material

32. . . bottom

34. . . wire

36a. . . Bump

38. . . Solder pad

122, 142. . . Active surface

124, 144. . . back

126, 146. . . Solder pad

Claims (28)

A recessed chip package structure comprising: a first wafer, a first active surface, a first back surface, and a plurality of first pads disposed on the first active surface; a substrate comprising a first surface And a second surface opposite to the first surface, wherein the first surface has a recess, and the first wafer is disposed on the recess, and the first surface may be provided with a plurality of step surfaces surrounding the recess And providing a connection point corresponding to the first pad on each step surface; and a plurality of connection points disposed on the surface of the first surface and the bottom of the recess; wherein the plurality The first pads are electrically connected to the plurality of connection points. The recessed chip package structure of claim 1, further comprising a plurality of bumps, wherein the plurality of first pads and the plurality of connection points are electrically connected to each other by the plurality of bumps. The recessed chip package structure according to claim 2, wherein the bump is a tin-lead bump, a lead-free bump, a copper pillar, a gold bump, a polymer bump or a junction bump, an elastic bump, or a composite metal bump. . The recessed chip package structure of claim 2, further comprising a second wafer and a plurality of first leads, wherein the second wafer comprises a second active surface, a second back surface, and the second active surface a plurality of second pads, the second back surface and the first back surface are joined, and the plurality of second pads and the plurality of first connection points are electrically connected to each other by the plurality of first wires Connected. The recessed chip package structure of claim 1, further comprising a plurality of first pads disposed on the first surface and a plurality of first metal conductive materials respectively disposed on the plurality of first pads. The recessed chip package structure of claim 1, further comprising a second wafer, a plurality of wires, and an adhesive layer, wherein the second wafer includes a second active surface, a second back surface, and the second surface a plurality of second pads on the active surface, wherein the second back surface and the first active surface are joined by the adhesive layer, and the plurality of first pads and the plurality of second pads are The plurality of wires are electrically connected to the plurality of connection points. The recessed wafer package structure of claim 6, wherein the adhesive layer is a film-on-silicone (FOW) layer. According to the recessed chip package structure of claim 7, the film covering wire bonding layer covers a portion of the wire. According to the recessed chip package structure of claim 4 or 6, the combination of the chips may be a combination of a memory chip and a memory chip, a combination of a memory chip and a control chip, a memory chip and a special-purpose integrated circuit. A combination of an ASIC chip, a combination of a memory chip and a DSP chip; wherein the memory chip can be in the form of SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM. A stacked package structure comprising: a first package component of any of the recessed chip package structures of claims 1 to 8, wherein the first package component further comprises a plurality of second portions disposed on the second surface of the substrate a pad and a plurality of second metal conductive materials respectively disposed on the plurality of second pads; and a second package component; The second package component is fixed to the plurality of second metal conductive materials and electrically connected to the first package component. The stacked package structure of claim 10, wherein the second package component has any one of the recessed chip package structures of claims 1 to 8. According to the layered package structure of claim 10, the combination of the first package component and the second package component may be a combination of a memory chip package component and a memory chip package component, a memory chip package component and a control chip. a combination of package components, a combination of a memory chip package component and a special purpose integrated circuit ASIC chip package component, or a combination of a memory chip package component and a DSP chip package component; wherein the memory chip package component can be a SRAM , DRAM, Flash, Mask ROM, EPROM or EEPROM. A recessed chip package structure comprising: a plurality of wafers, each of the wafers comprising an active surface, a back surface, and a plurality of pads disposed on the active surface; a substrate comprising a first surface and a first surface a second surface of the surface, wherein the first surface has a recess and at least one stepped surface surrounding the recess, and the plurality of wafer stacks are received in the recess, and the first surface may be disposed around the first surface a plurality of stepped surfaces of the recesses, wherein the stepped surfaces are provided with connection points corresponding to the pads; and a plurality of connection points are disposed on the first surface, the bottom of the recesses, and at least the stepped surfaces a surface of the plurality; wherein the plurality of pads are electrically connected to the plurality of connection points. The recessed chip package structure of claim 13, further comprising a plurality of metal wires, wherein the plurality of pads of the plurality of wafers are respectively The plurality of metal wires are electrically connected to the plurality of connection points on the step surface, the plurality of connection points on the first surface, and/or the plurality of connection points of the bottom of the recess. The recessed chip package structure of claim 14 further comprising at least one adhesive layer, wherein the active side and the back side of the adjacent wafer are joined by the adhesive layer. The recessed wafer package structure of claim 15, wherein the adhesive layer is a film covering the wire bond layer. According to the recessed chip package structure of claim 16, the film covering wire bonding layer covers a portion of the metal wire. The recessed chip package structure of claim 13, further comprising a plurality of bumps, wherein the plurality of pads and the plurality of connection points are electrically connected to each other by the plurality of bumps. The recessed chip package structure of claim 18, wherein the bump is a tin-lead bump, a lead-free bump, a copper pillar, a gold bump, a polymer bump or a junction bump, an elastic bump, or a composite metal bump. . The recessed chip package structure of claim 13, further comprising a plurality of metal wires and a plurality of bumps, wherein a plurality of the plurality of pads of the plurality of transistors are electrically connected to each other by the plurality of metal wires The plurality of bonding pads, the plurality of pads of the plurality of transistors are electrically connected to the corresponding plurality of connection points by the plurality of bumps. According to claim 3, the recessed chip package structure further comprises at least one thin film covering wire bond layer, and the active surface and a back surface of one of the adjacent ones of the wafers are joined by the film covering wire bonding layer. According to the recessed chip package structure of claim 21, wherein the film is covered The wire bonding layer covers a portion of the metal wire. According to claim 3, the recessed chip package structure further comprises at least one adhesive layer, and the two opposite sides of the two adjacent wafers are joined by the adhesive layer. The recessed chip package structure of claim 13 further comprising a plurality of first pads disposed on the first surface and a plurality of first metal conductive members respectively disposed on the plurality of first pads. According to the recessed chip package structure of claim 13, wherein the combination of the chips can be a combination of a memory chip and a memory chip, a combination of a memory chip and a control chip, a memory chip and a special-purpose integrated circuit ASIC. A combination of chips or a combination of a memory chip and a DSP chip; wherein the memory chip can be in the form of SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM. A stacked package structure comprising: a first package component of any of the recessed chip package structures of claims 13 to 24, wherein the first package component further comprises a plurality of second portions disposed on the second surface of the substrate a pad and a plurality of second metal conductive materials respectively disposed on the plurality of second pads; and a second package component; wherein the second package component is fixed to the plurality of second metal conductive materials, and The first package component is electrically connected. The stacked package structure of claim 26, wherein the second package component has any one of the recessed chip package structures of claims 13 to 24. According to the layered package structure of claim 26, the combination of the first package component and the second package component may be a combination of a memory chip package component and a memory chip package component, and a memory chip package component. Combination with a control chip package component, a combination of a memory chip package component and a special purpose integrated circuit ASIC chip package component, or a combination of a memory chip package component and a DSP chip package component; wherein the memory chip package component is in a form Can be SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM.