TW201037800A - Cavity chip package structure and package-on-package using the same - Google Patents

Cavity chip package structure and package-on-package using the same Download PDF

Info

Publication number
TW201037800A
TW201037800A TW098112436A TW98112436A TW201037800A TW 201037800 A TW201037800 A TW 201037800A TW 098112436 A TW098112436 A TW 098112436A TW 98112436 A TW98112436 A TW 98112436A TW 201037800 A TW201037800 A TW 201037800A
Authority
TW
Taiwan
Prior art keywords
wafer
recessed
pads
chip package
package structure
Prior art date
Application number
TW098112436A
Other languages
Chinese (zh)
Other versions
TWI387068B (en
Inventor
An-Hong Liu
Cheng-Ting Wu
Wu-Chang Tu
Po-Kai Hou
Original Assignee
Chipmos Technoligies Inc
Chipmos Technologies Bermuda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technoligies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technoligies Inc
Priority to TW098112436A priority Critical patent/TWI387068B/en
Publication of TW201037800A publication Critical patent/TW201037800A/en
Application granted granted Critical
Publication of TWI387068B publication Critical patent/TWI387068B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)

Abstract

A cavity chip packaging structure comprises a first chip, a substrate and a plurality of bonding pads. The first chip comprises an active surface, a back surface and a plurality of contacts. The substrate comprises a first surface and a second surface opposite to the first surface, wherein the first surface comprises a cavity and the chip is received in the cavity. The bonding pads are disposed on either or both the first surface and the bottom surface of the cavity, and are electrically connected to the corresponding contacts.

Description

201037800 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體晶片之封裝結構，特別係關 於一種凹穴晶片封裝結構。 【先前技術】 對於電子產品之移動性及高性能等功能需求，促進了 多晶片模組化（Multichip Module)之封裝技術的發展。多晶 ❹ 片模組化封裝技術係將兩個或兩個以上之半導體晶片組人 在單一封裝結構中，藉由此多晶片封裝成單一封裝結構之 技術，不僅可縮減原有積體電路封裝後之所佔體積，並可 因多晶片封裝結構可減少晶片間連接線路之長度、降低訊 號延遲、以及存取時間而提昇電性功能。 然而，傳統的多晶片模組係設置於一平面基板，經打 線及膠體封裝後，形成一厚的封裝體。雖然多晶片模組之 結構可將原本個別獨立之晶片所需之體積加以減縮，可是 ❹ 纟i之夕日曰片仍因具有突出之厚度而使利用多晶片模組讓 體積縮小之成效受限，造成發展高性能之移動電子裝置之 困擾。 另，在刖述之多晶片模組中’各晶片以金屬線電性連 接至平面基板之電路。然，位於多晶片模組靠近頂部處之 日日片，由於其金屬線路變長，故易影響其訊號傳遞之品質 鑑於上述之問題，有必要44· Φ 立σ ..^ 要針對電子產品之移動性及高 性月b等功能需求開發能# 更進一步縮小體積且不會造成訊號201037800 VI. Description of the Invention: [Technical Field] The present invention relates to a package structure of a semiconductor wafer, and more particularly to a recessed chip package structure. [Prior Art] The development of multi-chip module packaging technology has been promoted for functional requirements such as mobility and high performance of electronic products. Polycrystalline germanium module packaging technology combines two or more semiconductor chips into a single package structure, and the technology of multi-chip packaging into a single package structure can not only reduce the original integrated circuit package. The latter volume, and the multi-chip package structure can reduce the length of the connection line between the wafers, reduce the signal delay, and access time to improve the electrical function. However, the conventional multi-chip module is disposed on a flat substrate, and after being wired and colloidally packaged, a thick package is formed. Although the structure of the multi-wafer module can reduce the volume required for the original individual wafers, the 曰 之 之 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍 仍Caused by the development of high-performance mobile electronic devices. Further, in the multi-wafer module described above, each of the wafers is electrically connected to the circuit of the planar substrate by a metal wire. However, the solar wafer located near the top of the multi-chip module, because of its long metal line, is easy to affect the quality of its signal transmission. In view of the above problems, it is necessary to be 44· Φ 立 σ..^ For electronic products Mobility and high-performance month b and other functional requirements development can further reduce the size and will not cause signals

137401.DOC 201037800 傳遞不良之封裝結構。 【發明内容】 本發明揭示-種凹穴晶片封裝結構，利用該凹穴晶片 封裝結構可增加使用此結構之電子產品之移動性及提高該 電子產品之性能，且不會造成訊號傳遞不良。 本發明之凹穴晶片封裝結構之第一實施例包含一個第 晶片、一基板以及複數個連接點。該第一晶片包含—第 Ο 動面 第责面和设於該第一主動面上之複數個第 焊塾。該基板包含-第—表面及—相對於該第—表面之 第—表面，其中該第—表面具有一凹穴，且該第一晶片係 置於該凹八内。該些連接點設於該第一表面及該凹穴之 底部中至少一者之表面，並與該複數個第一焊墊電性相連 0 本發明之層4封震結構之一實施命含一具前述第— 實施例之凹穴晶片封裝結構之第一封裝元件及一第二封裝 〇 70件。第—封裝70件中另包含設於該第-封裝元件内之基 第表面上之複數弟一焊塾及分別設於該複數個第二 悍墊上之複數個第二金屬導電料，例如是錫球或凸塊，而 第—封裝兀件係固定於該複數個第二金厲導電料並和第 一封裝元件電性相連。 a I發明之凹穴晶片封裝結構之第二實施例包含複數個 曰曰曰片、-基板以及複數個連接點。各該複數個晶片包含一 人動面月面和设於該主動面上之複數個烊墊。基板包 第表面及-相對於該第一表面之第二表面，其中該137401.DOC 201037800 Passing bad package structure. SUMMARY OF THE INVENTION The present invention discloses a recessed chip package structure, by which the mobility of an electronic product using the structure can be increased and the performance of the electronic product can be improved without causing poor signal transmission. A first embodiment of the recessed chip package structure of the present invention comprises a first wafer, a substrate, and a plurality of connection points. The first wafer includes a first surface of the first surface and a plurality of first pads disposed on the first active surface. The substrate includes a - surface and a first surface opposite the first surface, wherein the first surface has a recess and the first wafer is disposed within the recess. The connection points are disposed on the surface of at least one of the first surface and the bottom of the recess, and are electrically connected to the plurality of first pads. The first package component and the second package package 70 of the recessed chip package structure of the foregoing first embodiment. The first package 70 further includes a plurality of solder pads disposed on the base surface of the first package component and a plurality of second metal conductive materials respectively disposed on the plurality of second die pads, such as tin The ball or the bump, and the first package member is fixed to the plurality of second gold conductive materials and electrically connected to the first package component. A second embodiment of the recessed chip package structure of the invention includes a plurality of dies, a substrate, and a plurality of connection points. Each of the plurality of wafers includes a moving surface and a plurality of mattresses disposed on the active surface. a substrate surface and a second surface opposite to the first surface, wherein the

137401.DOC -6 - 201037800 第7表面具有一凹穴及圍繞於該凹穴之至少—個階梯表面 ’並該複數個晶>1係堆疊收容於該凹穴内。該些連接點設 於該第一表面、該凹穴之底部及該階梯表面中至少—者2 表面，其中晶片之該些焊墊與該些連接點係電性相連。 本發明之層疊封裳結構之一實施例包含—具前述第二 實施例之凹穴晶片封裝結構之第一封裝元件及一第二封裝 兀件。第一封裝元件中另包含設於該第一封裝元件内之基 Ο 板之第二表面上之複數第二坪塾及分別設於該複數個第: 焊墊上之複數個第二金屬導電料，例如是錫球或凸塊，而 第二封裝元件係固定於該複數個第二金屬導電料，並和第 一封裝元件電性相連。 【實施方式】 圖1顯不本發明之第一實施例之打線接合之凹穴晶片 封裝結構IGa之示意I本實施例揭示之凹穴晶片封裝結構 l〇a包含-第-晶片12、—第二晶片14、—黏膠層Μ及一基 板…。基板18a包含-第―表面2〇、―相對於該第一表面 20之第二表面22及一* 凹八24，凹穴24設於該第一表面20上 ，其係用於配置封裝晶片，藉以使凹穴晶片封裝結構_之 南度降低’以達體積縮小之目的。第一表面2〇上另設置複 數個連接點26a和26b與焊塾28，谭墊28上可形成相對應之 金屬導電料30,例如是錫球或凸塊。基板W之第二表面22 上另可設有複數個焊墊38。 第一晶片12與第二晶片14分別包含一主動面（122和 142)及-背面（124和144) ’該些主動面⑴沐⑹上137401.DOC -6 - 201037800 The seventh surface has a recess and at least one stepped surface surrounding the recess and the plurality of crystal > 1 stacks are received in the recess. The connection points are disposed on the first surface, the bottom of the recess, and at least the surface of the step surface, wherein the pads of the wafer are electrically connected to the connection points. An embodiment of the laminated package structure of the present invention comprises a first package component and a second package component of the recessed chip package structure of the second embodiment. The first package component further includes a plurality of second pads disposed on the second surface of the base plate in the first package component and a plurality of second metal conductive materials respectively disposed on the plurality of pads: For example, it is a solder ball or a bump, and the second package component is fixed to the plurality of second metal conductive materials and electrically connected to the first package component. [Embodiment] FIG. 1 shows a schematic diagram of a wire-bonded recessed chip package structure IGa according to a first embodiment of the present invention. The recessed chip package structure 10a includes a first-wafer 12, a first Two wafers 14, an adhesive layer and a substrate. The substrate 18a includes a first surface 2, a second surface 22 opposite to the first surface 20, and a recess 84. The recess 24 is disposed on the first surface 20 for configuring the package wafer. In order to reduce the south of the cavity chip package structure to achieve the purpose of volume reduction. A plurality of connection points 26a and 26b are further disposed on the first surface 2, and a soldering pad 28 is formed on the pad 28, and the corresponding metal conductive material 30 is formed on the pad 28, such as a solder ball or a bump. A plurality of pads 38 may be further disposed on the second surface 22 of the substrate W. The first wafer 12 and the second wafer 14 respectively include an active surface (122 and 142) and a back surface (124 and 144). The active surfaces (1) are on the (6)

137401.DOC 201037800 具有複數個焊墊（126和146)。第一晶片12與第二晶片14 係以堆疊的方式設置於凹穴晶片封裝結構1〇a中，其中第一 晶片12係貼設於該凹穴24之底部32，接著黏膠層16設於該 第一晶片12之主動面122上，然後第二晶片14設於黏膠層16 上。而凹穴晶片封裝結構1〇&之電性連接之方式係以第一晶 片12之該些焊墊126和第二晶片14之該些焊墊146相對應地 與第一表面20上之該些連接點26a和26b電性相連。 0 於本實施例十，凹穴24之深度d係依照不同設計而定， 換言之，較佳之凹穴24之深度d可使該些第一晶片、第二 晶片14與基板18a間有較佳之電性表現。為考量電性表現， 與第二晶片14之焊墊146相對應之連接點26b上可設置一凸 塊36a，該些凸塊例如可是結線凸塊（stud bump)或者其他金 屬凸塊。於另一實施例中，該凹穴晶片封裝結構1〇a也可不 需包含該凸塊36a。 第一晶片12與第二晶片14間以黏膠層16黏接。於本案 Ο 實施例中，黏膠層16可約略覆蓋住整個第一晶片12之主動 面122 ’且將連接於焊墊126之導線34之部份埋入於其中。 第一晶片12與第二晶片14之組合方式係先將黏膠層16貼 附於第二晶片14之背面144，待第一晶片12完成打線製程 後，再以黏膠層16面向第一晶片12之方式將第二晶片14 貼附於其上。在一實施例中，黏膠層16可為薄膜覆蓋銲線 (Film on Wire; F0W)層，可降低封裝高度與提供導線 保護之功效而提昇導線之穩定度。上述該些第一晶片與第 二晶片之組合態樣可以為記憶體晶片與記憶體晶片之組 201037800 合、記憶體晶片與控制晶片之組合、記憶體晶片與特殊用 途積體電路ASIC晶片之組合、記憶體晶片與DSp晶片之組 合；其中該記憶體晶片之型態可為SRAM、DRAM、 、Mask ROM、EPROM 或者 EEPROM。 圖2顯示本發明之第二實施例之打線接合之凹穴晶片 封裝結構10b之示意圖。本發明第二實施例揭示之凹穴晶 片封裝結構1 Ob係與本發明第一實施例揭示之凹穴晶片封 〇 裝結構1〇a具類似結構，惟第二實施例中，設於基板18b 之第一表面20上之凹穴24較第一實施例中之凹穴24具有 大的底部面積與較深之深度d，，使第二晶片表面可與基板 之一表面切齊。同樣地，凹穴24之深度出可設計使該第一 晶片、第二晶片14與基板具有較佳之電性表現。第一晶片 12上之知塾126以相對應之導線34連接至設於凹穴24之底 部32上之連接點26a，為考量電性表現，底部32上之連接 點26a更可設有一凸塊36b，例如是結線凸塊或者其他金屬 〇 凸塊。於另一實施例中’該凹穴晶片封裝結構1 Ob也可不 需包含該凸塊36b。 圖3顯示本發明之第三實施例之利用打線接合之凹穴 晶片封裝結構1 〇c之示意圖。本發明第三實施例揭示之凹 穴晶片封裝結構10c包含第一晶片12、第二晶片14、第三 晶片15、複數層黏膠層16及一基板18(：。第一晶片12、第 二晶片14與第三晶片15分別包含一主動面（122、142和152 )’而各該些主動面（122、142和152)上包含複數個焊 塑* (126、146和156)·。基板18c包含第一表面20、一相對137401.DOC 201037800 has a plurality of pads (126 and 146). The first wafer 12 and the second wafer 14 are disposed in a stacked manner in the recessed chip package structure 1a, wherein the first wafer 12 is attached to the bottom 32 of the recess 24, and then the adhesive layer 16 is disposed on The active surface 122 of the first wafer 12 is then disposed on the adhesive layer 16 of the second wafer 14. The electrical connection of the recessed chip package structure 1 & is such that the pads 126 of the first wafer 12 and the pads 146 of the second wafer 14 correspond to the first surface 20 The connection points 26a and 26b are electrically connected. 0, in the tenth embodiment, the depth d of the recess 24 is determined according to different designs. In other words, the preferred depth d of the recess 24 can provide better electrical power between the first wafer, the second wafer 14 and the substrate 18a. Sexual performance. In order to consider the electrical performance, a bump 36a may be disposed on the connection point 26b corresponding to the pad 146 of the second wafer 14, and the bumps may be, for example, stud bumps or other metal bumps. In another embodiment, the recessed chip package structure 1a may not need to include the bumps 36a. The first wafer 12 and the second wafer 14 are adhered by an adhesive layer 16. In the embodiment of the present invention, the adhesive layer 16 can cover approximately the active surface 122' of the entire first wafer 12 and embed a portion of the wires 34 connected to the bonding pads 126 therein. The first wafer 12 and the second wafer 14 are combined by first attaching the adhesive layer 16 to the back surface 144 of the second wafer 14. After the first wafer 12 is completed, the adhesive layer 16 faces the first wafer. The second wafer 14 is attached thereto in a manner of 12. In one embodiment, the adhesive layer 16 can be a film-on-film (F0W) layer that reduces the package height and provides wire protection for improved wire stability. The combination of the first chip and the second chip may be a combination of a memory chip and a memory chip 201037800, a combination of a memory chip and a control chip, and a combination of a memory chip and a special-purpose integrated circuit ASIC chip. The combination of a memory chip and a DSp chip; wherein the memory chip can be in the form of SRAM, DRAM, Mask ROM, EPROM or EEPROM. Fig. 2 is a view showing the wire bonded die pad package structure 10b of the second embodiment of the present invention. The recessed wafer package structure 1 Ob disclosed in the second embodiment of the present invention has a similar structure to the recessed wafer package mounting structure 1A of the first embodiment of the present invention, but in the second embodiment, it is disposed on the substrate 18b. The recess 24 on the first surface 20 has a larger bottom area and a deeper depth d than the recess 24 in the first embodiment, so that the second wafer surface can be aligned with one of the surfaces of the substrate. Similarly, the depth of the recess 24 can be designed to provide a better electrical performance of the first wafer, the second wafer 14 and the substrate. The 126 on the first wafer 12 is connected to the connection point 26a provided on the bottom 32 of the cavity 24 by a corresponding wire 34. For the electrical performance, the connection point 26a on the bottom 32 may be provided with a bump. 36b, such as a junction bump or other metal dome bump. In another embodiment, the recessed chip package structure 1 Ob does not need to include the bumps 36b. Fig. 3 is a view showing a recessed chip package structure 1c of the third embodiment of the present invention. The recessed chip package structure 10c disclosed in the third embodiment of the present invention comprises a first wafer 12, a second wafer 14, a third wafer 15, a plurality of adhesive layers 16 and a substrate 18 (: the first wafer 12, the second The wafer 14 and the third wafer 15 respectively include an active surface (122, 142, and 152)' and each of the active surfaces (122, 142, and 152) includes a plurality of solder moldings* (126, 146, and 156). 18c includes a first surface 20, a relative

137401.DOC 201037800 於該第一表面20之第二表面22及一凹穴μ，凹穴24設於該 第一表面20上。第一晶片12、第二晶片14與第三晶片15 相疊設置且收容於凹穴24中，其中第一晶片12、第二晶片 14與第三晶片15之主動面（122、142和152)均背向凹穴 24之底部32且兩相鄰晶片間設有黏膠層16。由於第一晶片 12、第二晶片14與第三晶片15係相疊設置，使其焊墊（i26 、146和156)呈階梯式分布，為縮短連接至焊墊（126、 ❹ 146和156 )之導線34之長度，第一表面20上可設圍繞凹穴 24之複數階梯表面（4〇a和4〇b)，且於各階梯表面（4〇a 和40b )上設有相對應於該些焊墊（126、ι46 )之連接點 (26a和26b)，又第一表面20上亦設有相對應於焊墊156 之連接點26c’藉此達成縮短導線34之長度之目的。各階 梯表面（40a和40b)之高度（或階梯級數）可與相疊晶片 之相對應之階層高度（或數量）配合設置，使各相疊晶片 之焊墊（126、146和156)可以較佳的電連接路徑連接至 〇 相對應之連接點（26a、26b和26c)。第一表面20上可另 設置複數個焊墊28’焊墊28上可形成相對應之金屬導電料 30例如是錫球或者凸塊。基板i8c之第二表面22上則可另 設有複數個焊墊38。 圖4顯示本發明之一實施例之覆晶接合之凹穴晶片封 裝結構10d之示意圖。本實施例揭示之凹穴晶片封裝結構 l〇d包含一第一晶片42及一基板I8d。基板18d包含一第— 表面20、一相對於該第一表面20之第二表面22及設於該第 一表面20上之一凹穴24。第一晶片42包含一主動面422， 137401.DOC -10- 201037800 該主動面422具有複數個焊墊426。凹穴24之底部具有複數 個連接點26a，該些連接點26a係與該些焊墊426相對應， 且各相對應之連接點26a與焊塾426間以一凸塊44電性相 連。於本實施例中，該凸塊44係錫鉛凸塊、無鉛凸塊、結 線凸塊、金凸塊、金屬態樣之兩分子凸塊、彈性凸塊或者 疋複合金屬凸塊。第一表面20上可另設置複數個焊塾28 ’而焊塾28上可形成相對應之金屬導電料3〇例如是錫球或 0 者凸塊。基板18d之第二表面22上則另可設有複數個焊墊 38 ° 圖5和圖6顯示本發明之其他實施例之覆晶接合之凹 八晶片封裝結構（1 〇6和丨〇f)之示意圖。圖5和圖6例示之 凹穴晶片封裝結構（1(^和10f)與圖4例示之凹穴晶片封 裝結構10d具有類似之構造，惟三者之覆晶接合之技術方 法不同。圖5例示之凹穴晶片封裝結構1〇e内，其第一晶片 42之焊墊426與凹穴底部之連接點26a電性連接之凸塊料 〇 域柱，該些從焊塾426凸伸之銅柱係焊接於相對應之連 接點26a，較佳地更可以利用一焊錫材料27&(連接點上 方之元件）以增進接合。於其他實施例中，該銅柱表面也 可配置一層由金所組成的金屬層，利用熱壓合或者是超音 S鍵、。方式使鋼柱44與連接點26&接合，而不需要焊錫材 料27a。而圖6例示之凹穴晶片封裝結構10f内，其第一晶 片42之焊塾426與凹穴底部之連接點^電性連接之凸塊 44為金凸塊。 圖7顯示本發明夕# ^ ^ 月之第一實施例之多晶片堆疊之凹穴晶 201037800 片封裝結構10g之示意圖。本實施例揭示之凹穴晶片封裝 結構l〇g包含-第-晶片42、-第二晶片46及一基板18e 。基板18e包含一第一表面20、一相對於該第一表面2〇之 第二表面22及一凹穴24，該凹穴24設於該第一表面2〇上且 其底部32設有複數個連接點26a。第一晶片42之主動面422 上包含複數個與連接點26a相對應之焊墊426,其中連接點 26a和相對應之焊墊426間係以覆晶技術電性相連。第二晶 〇 片46之背面464貼附於第一晶片42之背面424，其主動面 462上包含複數個焊墊466,而該些焊墊466係以打線技術 電性相連於設於基板18e之第一表面2〇且周設於凹穴24之 連接點26b。第一表面20另包含複數個焊墊28，而焊墊28 上可形成相對應之金屬導電料30。基板18e之第二表面22 上可設有複數個焊墊38。 圖8顯示本發明之第二實施例之多晶片堆疊之凹穴晶 片封裝結構1 Oh之示意圖。本實施例揭示之凹穴晶片封裝 © 結構10h包含一第一晶片42、一第二晶片48及一基板I8f。 基板18f包含一第一表面20、一相對於該第一表面2〇之第 二表面22及一凹穴24，該凹穴24設於該第一表面2〇上且其 底部32設有複數個連接點26a。該凹穴24旁周設階梯表面 40a ’其中該階梯表面40a設有複數個連接點261)。第一晶 片42之主動面422上包含複數個與連接點26a相對應之焊 墊426，其中連接點26a和相對應之焊墊426間係以覆晶技 術電性相連。第二晶片48之主動面482上設有複數個與連 接點26b相對應之焊墊486，其中連接點26b和相對應之焊 13740I.DOC •12- 201037800 墊486間係以覆晶技術電性相連。第一表面2〇另包含複數 個焊墊28，而焊墊28上可形成相對應之金屬導電料3〇。基 板18f之第二表面22上可設有複數個焊墊38。上述該些第 一晶片與第二晶片之組合態樣可以為記憶體晶片與記憶 體曰曰片之組合、記憶體晶片與控制晶片之組合、記憶體晶 片與特殊用途積體電路ASIC晶片之組合、記憶體晶片與 DSP晶片之組合；其中該記憶體晶片之型態可為sram、 0 DRAM、Flash、Mask ROM、EPROM或者 EEPROM。 圖9顯示本發明之第三實施例之多晶片堆疊之凹穴晶 片封裝結構1 Οι之示意圖。本實施例揭示之凹穴晶片封裝 結構10i包含一第一晶片42、一第二晶片48、一第三晶片 50及一基板18f。基板18f包含一第一表面2〇、一相對於該 第一表面20之第二表面22及一凹穴24,該凹穴24旁周設階 梯表面40a。第一晶片42與第二晶片48係如圖8實施例所示 ，分別以覆晶技術電性相連於凹穴2 4之底部與階梯表面 〇 40a。第三晶片50以其背面504貼附於第二晶片48,且第三 晶片50之主動面502上之焊墊506係以打線技術電性連接 至第一表面20上之連接點26c。連接點26c上更例如可設有 凸塊36b，例如是結線凸塊或者是錫鉛凸塊或者無鉛凸塊 ，以增進電連接特性。於另一實施例中，該凹穴晶片封裝 結構10i也可不需包含該凸塊36b。 第一表面20另包含複數個焊墊28,而焊墊28上可形成 相對應之金屬導電料30。基板18f之第二表面22上可設有 複數個焊墊38。 I3740I.DOC -13- 201037800 圖10顯不本發明之第四實施例之多晶片堆疊之凹穴 曰曰片封裝結構1⑴之不意圖。本實施例揭示之凹穴晶片封 裝結構1〇j包含一第一晶片42、一第二晶片48、一第三晶 片50、一第四晶片52、一黏膠層54及一基板18g。基板18g 包含—第一表面20、一相對於該第一表面2〇之第二表面22 八24 ’該凹八24旁周設複數階梯表面4〇3和4〇b。第 一晶片42和第二晶片48分別以覆晶技術電性相連於凹穴 〇 24之底部與階梯表面40a。第三晶片50如圖9所示貼附於第 一曰日片48 ’並以打線技術電性連接至階梯表面40b上之連 接點26c，而黏膠層54包覆第三晶片之打線的一部份。本 實施例中，黏膠層54可為薄膜覆蓋導線（Fiim 〇n wire ; FOW )層，可降低封裝高度與提供導線保護之功效而提昇 導線之穩定度。連接點26c上更例如可設有凸塊36b例如是 結線凸塊或者是錫鉛凸塊或者無鉛凸塊，以增進電連接特 性。第四晶片52以黏膠層54黏著於第三晶片50之主動面 6 502上，並以打線技術電性連接至第一表面20上之連接點 26d。第一表面20另包含複數個焊墊28，而焊墊28上可形 成相對應之金屬導電料30。基板l8g之第二表面22上可設 有複數個焊墊38。上述該些第一晶片、第二晶片、第三晶 片與第四晶片之組合態樣可以為記憶體晶片與記憶體晶 片之組合、記憶體晶片與控制晶片之組合、記憶體晶片與 特殊用途積體電路ASIC晶片之組合、記憶體晶片與DSP 晶片之組合；其中該記憶體晶片之型態可為SRAM、DRAM 、Flash、Mask ROM、EPROM或者EEPROM 〇 137401 .DOC -14 - 201037800 圖11顯示本發明第一實施例之具凹穴晶片封裝結構 之層疊封裝結構（Package on Package ) 60a之示意圖。本 實施例之層疊封裝結構6〇a包含第一封裝元件62a及第二 封裝70件64。第一封裝元件62a係具凹穴晶片封裝結構， 其包含一晶片66及一基板18a。基板18a之第一表面20上具 一凹穴24，晶片66配置於該凹穴24，並以打線技術將晶片 66上位於主動面662之焊墊664電性連接於第一表面別上 〇 之連接點26a，較佳地，該焊墊664更可配置有一凸塊例如 疋結線凸塊，以增進打線接合能力跟電連接特性。於另一 實施例中，該凹穴晶片封裝結構丨也可不需包含該凸塊 〇 基板18 a之第二表面22包含複數個焊墊68，該些焊墊 68分別設有相對應之複數個金屬導電料70。在本實施例中 ’第二封裝元件64與第一封裝件62a結構相同，在此不多 贅述。利用該些金屬導電料7〇,第一封裝元件62a及第二 〇 封裝兀件64得電性連接。於其他實施例中，第二封裝件之 架構也可不同於第一封裝件62a。 圖12顯示本發明第二實施例之具凹穴晶片封裝結構 之層疊封裝結構60b之示意圖。本實施例之層疊封裝結構 60b包含第一封裝元件62b及第二封裝元件64。第一封裝元 件62b與第二封裝元件64係具如圖3所示之凹穴晶片封裝 結構10c’其第二表面22上之焊墊38設有複數個對應之金 屬導電料70。第一封裝元件62b及第二封裝元件64利用該 些金屬導電料70電性連接。於其他實施例中，第二封裝元137401. DOC 201037800 is disposed on the second surface 22 of the first surface 20 and a recess μ, and the recess 24 is disposed on the first surface 20. The first wafer 12, the second wafer 14 and the third wafer 15 are disposed on top of each other and are received in the recess 24, wherein the active surfaces (122, 142 and 152) of the first wafer 12, the second wafer 14 and the third wafer 15 are Each of them faces away from the bottom 32 of the pocket 24 and an adhesive layer 16 is disposed between two adjacent wafers. Since the first wafer 12, the second wafer 14 and the third wafer 15 are arranged one on top of the other, the pads (i26, 146 and 156) are arranged in a stepwise manner for shortening the connection to the pads (126, 146 and 156). The length of the wire 34, the first surface 20 may be provided with a plurality of stepped surfaces (4〇a and 4〇b) surrounding the cavity 24, and corresponding to the step surfaces (4〇a and 40b) The connection points (26a and 26b) of the pads (126, ι46) and the first surface 20 are also provided with connection points 26c' corresponding to the pads 156 to thereby shorten the length of the wires 34. The height (or number of steps) of each step surface (40a and 40b) can be matched with the corresponding height (or number) of layers of the stacked wafers, so that the pads (126, 146 and 156) of the stacked wafers can be A preferred electrical connection path is connected to the corresponding connection point (26a, 26b and 26c). A plurality of pads 28' may be disposed on the first surface 20. The pads 28 may be formed with corresponding metal conductive materials 30 such as solder balls or bumps. A plurality of pads 38 may be additionally disposed on the second surface 22 of the substrate i8c. Fig. 4 is a view showing a flip chip bonded recessed wafer package structure 10d according to an embodiment of the present invention. The recessed chip package structure disclosed in this embodiment includes a first wafer 42 and a substrate I8d. The substrate 18d includes a first surface 20, a second surface 22 opposite the first surface 20, and a recess 24 disposed on the first surface 20. The first wafer 42 includes an active surface 422, 137401.DOC-10-201037800. The active surface 422 has a plurality of pads 426. The bottom of the recess 24 has a plurality of connecting points 26a. The connecting points 26a correspond to the pads 426, and the corresponding connecting points 26a and the soldering pads 426 are electrically connected by a bump 44. In this embodiment, the bumps 44 are tin-lead bumps, lead-free bumps, junction bumps, gold bumps, metal-like two-member bumps, elastic bumps or germanium composite metal bumps. A plurality of solder bumps 28' may be additionally disposed on the first surface 20 and a corresponding metal conductive material 3 such as a solder ball or a bump may be formed on the solder bump 28. The second surface 22 of the substrate 18d may be further provided with a plurality of pads 38°. FIG. 5 and FIG. 6 show the flip chip eight-chip package structures (1 〇 6 and 丨〇 f) of other embodiments of the present invention. Schematic diagram. The recessed chip package structure (1 (^ and 10f) illustrated in Figures 5 and 6 has a similar configuration to the recessed chip package structure 10d illustrated in Figure 4, but the technical methods of the flip chip bonding of the three are different. In the recessed chip package structure 1 〇e, the bump 426 of the first wafer 42 and the connection point 26a of the bottom of the recess are electrically connected to the bump column, and the copper pillars protruding from the solder 426 Soldering at the corresponding connection point 26a, preferably a solder material 27 & (element above the connection point) is used to enhance the bonding. In other embodiments, the surface of the copper post may also be provided with a layer of gold. The metal layer is bonded to the connection point 26& by means of thermocompression or supersonic S-bonding, without the need for the solder material 27a. The first embodiment of the recessed chip package structure 10f illustrated in FIG. The bump 44 electrically connected to the connection point of the solder bump 426 of the wafer 42 and the bottom of the recess is a gold bump. Fig. 7 shows the recessed crystal 201037800 of the multi-wafer stack of the first embodiment of the present invention. Schematic diagram of the chip package structure 10g. The cavity chip seal disclosed in this embodiment The structure 〇g includes a first wafer 42, a second wafer 46, and a substrate 18e. The substrate 18e includes a first surface 20, a second surface 22 opposite the first surface 2, and a recess 24. The recess 24 is disposed on the first surface 2〇 and has a plurality of connection points 26a at the bottom portion 32. The active surface 422 of the first wafer 42 includes a plurality of pads 426 corresponding to the connection points 26a, wherein the connection The surface 26a and the corresponding pad 426 are electrically connected by a flip chip technique. The back surface 464 of the second wafer 46 is attached to the back surface 424 of the first wafer 42 and the active surface 462 includes a plurality of pads 466. The pads 466 are electrically connected to the first surface 2 of the substrate 18e and are circumferentially disposed at the connection point 26b of the cavity 24. The first surface 20 further includes a plurality of pads 28, and A corresponding metal conductive material 30 can be formed on the solder pad 28. A plurality of solder pads 38 can be disposed on the second surface 22 of the substrate 18e. Figure 8 shows a multi-chip stacked recessed chip package of the second embodiment of the present invention. Schematic diagram of structure 1 Oh. The cavity chip package © structure disclosed in this embodiment 10h includes a first wafer 42, a The second substrate 48 and the substrate I8f. The substrate 18f includes a first surface 20, a second surface 22 opposite to the first surface 2, and a recess 24. The recess 24 is disposed on the first surface 2 The bottom portion 32 is provided with a plurality of connecting points 26a. The recess 24 is circumferentially provided with a stepped surface 40a', wherein the stepped surface 40a is provided with a plurality of connecting points 261). The active surface 422 of the first wafer 42 includes a plurality of pads 426 corresponding to the connection points 26a, wherein the connection points 26a and the corresponding pads 426 are electrically connected by flip chip technology. The active surface 482 of the second wafer 48 is provided with a plurality of pads 486 corresponding to the connection points 26b, wherein the connection points 26b and the corresponding solders 13740I.DOC • 12- 201037800 pads 486 are flip-chip technology Connected. The first surface 2 〇 further includes a plurality of pads 28, and the corresponding metal conductive material 3 is formed on the pad 28. A plurality of pads 38 may be disposed on the second surface 22 of the substrate 18f. The combination of the first wafer and the second wafer may be a combination of a memory chip and a memory chip, a combination of a memory chip and a control chip, and a combination of a memory chip and a special-purpose integrated circuit ASIC chip. The combination of the memory chip and the DSP chip; wherein the type of the memory chip can be sram, 0 DRAM, Flash, Mask ROM, EPROM or EEPROM. Fig. 9 is a view showing the structure of a recessed wafer package structure 1 of a multi-wafer stack according to a third embodiment of the present invention. The recessed chip package structure 10i disclosed in this embodiment comprises a first wafer 42, a second wafer 48, a third wafer 50 and a substrate 18f. The substrate 18f includes a first surface 2?, a second surface 22 opposite to the first surface 20, and a recess 24. The recess 24 is provided with a step surface 40a. The first wafer 42 and the second wafer 48 are electrically connected to the bottom of the recess 24 and the step surface 〇 40a by a flip chip technique, respectively, as shown in the embodiment of FIG. The third wafer 50 is attached to the second wafer 48 with its back surface 504, and the bonding pads 506 on the active surface 502 of the third wafer 50 are electrically connected to the connection point 26c on the first surface 20 by a wire bonding technique. Further, for example, bumps 36b may be provided on the connection point 26c, such as junction bumps or tin-lead bumps or lead-free bumps to enhance electrical connection characteristics. In another embodiment, the recessed chip package structure 10i may not need to include the bumps 36b. The first surface 20 further includes a plurality of pads 28, and a corresponding metal conductive material 30 is formed on the pads 28. A plurality of pads 38 may be disposed on the second surface 22 of the substrate 18f. I3740I.DOC -13- 201037800 FIG. 10 shows a schematic view of the recessed chip package structure 1 (1) of the multi-wafer stack of the fourth embodiment of the present invention. The recessed wafer package structure 1A includes a first wafer 42, a second wafer 48, a third wafer 50, a fourth wafer 52, an adhesive layer 54, and a substrate 18g. The substrate 18g includes a first surface 20, a second surface 22 opposite to the first surface 2, and a plurality of stepped surfaces 4〇3 and 4〇b. The first wafer 42 and the second wafer 48 are electrically connected to the bottom of the pocket 24 and the step surface 40a by flip chip technology, respectively. The third wafer 50 is attached to the first day piece 48' as shown in FIG. 9 and electrically connected to the connection point 26c on the step surface 40b by a wire bonding technique, and the adhesive layer 54 covers the wire of the third wafer. Part. In this embodiment, the adhesive layer 54 can be a film-covered wire (Fim 〇n wire; FOW) layer, which can reduce the package height and provide wire protection to improve the stability of the wire. The connection point 26c may further be provided with, for example, bumps 36b such as junction bumps or tin-lead bumps or lead-free bumps to enhance electrical connection characteristics. The fourth wafer 52 is adhered to the active surface 6 502 of the third wafer 50 by an adhesive layer 54 and electrically connected to the connection point 26d on the first surface 20 by a wire bonding technique. The first surface 20 further includes a plurality of pads 28, and the corresponding metal conductive material 30 is formed on the pads 28. A plurality of pads 38 may be disposed on the second surface 22 of the substrate 18g. The combination of the first wafer, the second wafer, the third wafer and the fourth wafer may be a combination of a memory wafer and a memory wafer, a combination of a memory wafer and a control wafer, a memory chip and a special purpose product. Combination of a body circuit ASIC chip, a combination of a memory chip and a DSP chip; wherein the memory chip type can be SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM 〇 137401. DOC -14 - 201037800 Figure 11 shows A schematic diagram of a package on package 60a having a recessed chip package structure of the first embodiment of the invention. The stacked package structure 6A of the present embodiment includes a first package component 62a and a second package 70 member 64. The first package component 62a is provided with a recessed chip package structure including a wafer 66 and a substrate 18a. The first surface 20 of the substrate 18a has a recess 24, and the wafer 66 is disposed on the recess 24, and the bonding pad 664 on the active surface 662 of the wafer 66 is electrically connected to the first surface by a wire bonding technique. Preferably, the pad 664 is further provided with a bump, such as a splicing bump, to improve wire bonding capability and electrical connection characteristics. In another embodiment, the recessed chip package structure 丨 does not need to include the bump 〇 substrate 18 a. The second surface 22 includes a plurality of pads 68 , and the pads 68 are respectively provided with a plurality of corresponding pads Metal conductive material 70. In the present embodiment, the second package component 64 has the same structure as the first package member 62a, and will not be described here. The first package component 62a and the second package package member 64 are electrically connected by using the metal conductive materials 7〇. In other embodiments, the structure of the second package may also be different from the first package 62a. Fig. 12 is a view showing a laminated package structure 60b having a recessed chip package structure according to a second embodiment of the present invention. The stacked package structure 60b of the present embodiment includes a first package component 62b and a second package component 64. The first package component 62b and the second package component 64 are provided with a recessed chip package structure 10c' as shown in FIG. 3, and the pads 38 on the second surface 22 are provided with a plurality of corresponding metal conductive materials 70. The first package component 62b and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the second package element

137401.DOC •15· 201037800 件64之架構也可不同於第一封裴元件62b。 圖13顯不本發明第三實施例之具凹穴晶片封裝結構 之層疊封裝結構60c之示意圖。本實施例之層疊封裝=構 6〇c包含第一封裝元件62c及第二封裝元件㈣。第一封裝元 件62c及第二封裝元件64係具如圖4所示之凹穴晶片^妒 結構18d，其第二表面22上之焊塾38設有複數個對應之複 數個金屬導電料70。第一封裝元件62c及第二封裝元件以 〇 利用該些金屬導電料70電性連接。於其他實施例中，第二 封裝元件64之架構也可不同於第一封裝元件62e。 圖14顯示本發明第四實施例之具凹穴晶片封裝結構 之層疊封裝結構60d之示意圖。本實施例之層疊封裝結構 ’60d包含第一封裝元件62d及第二封裝元件料。第一封裝元 件62d及第二封裝元件64係具如圖5所示之凹穴晶片封裝 結構l〇e’其第二表面22上之焊墊38設有複數個對應之複 數個金屬導電料70〇第一封裝元件62d及第二封裝元件料 Ο 利用該些金屬導電料70電性連接。於其他實施例中，第二 封裝元件64之架構也可不同於第一封裝元件62d。 圖15顯不本發明第五實施例之具凹穴晶片封裝結構 之層疊封裝結構60e之示意圖。本實施例之層疊封裝結構 60e包含第一封裝元件62e及第二封裝元件64。第—封^元 件62e及第二封裝元件64係具如圖6所示之凹穴晶片封裝 結構l〇f’其第二表面22上之焊墊38設有複數個對應之複 數個金屬導電料70。第一封裝元件62e及第二封裝元件料 利用該些金屬導電料70電性連接。於其他實施例中，第二 137401.DOC •16- 201037800 封裝元件64之架構也可不同於第一封装元件㈣。 圖16顯示本發明第六實施例之具凹穴晶片封裝結構 之層疊封裝結構60f之示意圖。本實施例之層疊封裝結構 6〇f包含第-封裝元件62f及第二封裝元件64。第一封裝元 件62f及第二封裝元件64係具如圖7所示之凹穴晶片封裝 結構l〇g，其第二表面22上之焊墊38設有複數個對應之複 數個金屬導電料7G。第—封裝元件62f及第二封裝元件 〇 利用該些金屬導電料70電性連接。於其他實施例中，第二 封裝元件64之架構也可不同於第一封裝元件62f。 圖17顯示本發明第七實施例之具凹穴晶片封裝結構 之層疊封裝結構60g之示意圖。本實施例之層疊封裝結構 6〇g包含第一封裝元件62g及第二封裝元件以。第一封裝元 件62g及第二封裝元件64係具如圖8所示之凹穴晶片封裝 結構l〇h’其基板18f之第二表面22上之焊墊％設有複數個 對應之複數個金屬導電料7〇β第一封裝元件62g及第二封 © 裝元件64利用該些金屬導電料70電性連接。於其他實施例 中，第二封裝元件64之架構也可不同於第一封裝元件62f 〇 圖1 8顯示本發明第八實施例之具凹穴晶片封裝結構 之層疊封裝結構6〇h之示意圖。本實施例之層疊封裝結構 60h包含第一封裝元件62h及第二封裝元件6[第一封裝元 件62h及第二封裝元件64係具如圖9所示之凹穴晶片封裝 結構1〇1，其基板18f之第二表面22上之焊墊38設有複數個 對應之複數個金屬導電料7〇。於另一實施例之層疊封裝結The structure of 137401.DOC •15· 201037800 piece 64 may also be different from the first sealing element 62b. Figure 13 is a schematic view showing a laminated package structure 60c having a recessed chip package structure according to a third embodiment of the present invention. The package package of the present embodiment includes a first package component 62c and a second package component (4). The first package component 62c and the second package component 64 are provided with a recessed wafer structure 18d as shown in FIG. 4, and the solder bumps 38 on the second surface 22 are provided with a plurality of corresponding plurality of metal conductive materials 70. The first package component 62c and the second package component are electrically connected by using the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62e. Fig. 14 is a view showing a laminated package structure 60d having a recessed chip package structure according to a fourth embodiment of the present invention. The stacked package structure '60d' of this embodiment includes a first package component 62d and a second package component material. The first package component 62d and the second package component 64 are provided with a recessed chip package structure 10'' as shown in FIG. 5, and the pad 38 on the second surface 22 is provided with a plurality of corresponding plurality of metal conductive materials 70. The first package component 62d and the second package component material are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62d. Fig. 15 is a view showing a laminated package structure 60e having a recessed chip package structure according to a fifth embodiment of the present invention. The stacked package structure 60e of this embodiment includes a first package component 62e and a second package component 64. The first sealing element 62e and the second packaging element 64 are provided with a recessed chip package structure 10f as shown in FIG. 6, and the bonding pad 38 on the second surface 22 is provided with a plurality of corresponding plurality of metal conductive materials. 70. The first package component 62e and the second package component are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second 137401.DOC•16-201037800 package component 64 may also be different than the first package component (4). Fig. 16 is a view showing a laminated package structure 60f having a recessed chip package structure according to a sixth embodiment of the present invention. The stacked package structure 6〇f of the present embodiment includes a first package element 62f and a second package element 64. The first package component 62f and the second package component 64 are provided with a recessed chip package structure 10 as shown in FIG. 7, and the pad 38 on the second surface 22 is provided with a plurality of corresponding plurality of metal conductive materials 7G. . The first package component 62f and the second package component 〇 are electrically connected by the metal conductive materials 70. In other embodiments, the architecture of the second package component 64 can also be different than the first package component 62f. Fig. 17 is a view showing a laminated package structure 60g having a recessed chip package structure according to a seventh embodiment of the present invention. The stacked package structure 6〇g of the present embodiment includes a first package component 62g and a second package component. The first package component 62g and the second package component 64 are provided with a recessed chip package structure l〇h' as shown in FIG. 8. The pad % on the second surface 22 of the substrate 18f is provided with a plurality of corresponding plurality of metals. The conductive material 7〇β first package component 62g and the second package component 64 are electrically connected by the metal conductive materials 70. In other embodiments, the structure of the second package component 64 may also be different from that of the first package component 62f. FIG. 18 shows a schematic diagram of the package structure 6h of the recessed chip package structure of the eighth embodiment of the present invention. The stacked package structure 60h of the present embodiment includes a first package component 62h and a second package component 6 [the first package component 62h and the second package component 64 are provided with a recessed chip package structure 〇1 as shown in FIG. The pad 38 on the second surface 22 of the substrate 18f is provided with a plurality of corresponding plurality of metal conductive materials 7〇. Cascading package junction in another embodiment

137401.DOC -17- 201037800 構中，該第-封裝元件62h也可不需包含該連接點上的凸 塊 3 6 b 〇 第一封裝元件62h及第二封裝元件64利用該些金屬導 電料70電性連接。於其他實施例中，第二封襄元件64之架 構也可不同於第一封裝元件62f。 圖19顯示本發明第九實施例之具凹穴晶片封裝結構 之層疊封裝結構60i之示意圖。本實施例之 〇 崎含第-封裝元件-及第二封裝元件“。第_封= 件62ι及第二封裝元件64係具如圖1〇所示之凹穴晶片封裝 結構其基板18g之第二表面22上之焊墊38設有複數個 對應之複數個金屬導電料70。第一封裝元件62i及第二封 裝元件64利用該些金屬導電料7〇電性連接。於其他實施例 中，第二封裝元件64之架構也可不同於第—封裝元件62f 。於另一實施例之層疊封裝結構中，該第一封裝元件62i 也可不需包含該連接點上的凸塊36b。 〇 -實施例 具有凹穴晶片封裝結構。上述該些第—封裝元件與第二封 裝元件之組合態樣可以為記憶體晶片封裝元件與記憶體 晶片封裝元件之組合、記憶體晶片封裝元件與控制晶片封 裝元件之組合、記憶體晶片封裝元件與特殊用途積體電路 ASIC晶片封跋元件之組合、記憶體晶片封裝元件與DSp 晶片封裝元件之組合；其中該記憶體晶片封裝元件之型態 可為 SRAM、DRAM、Flash、Mask R〇M、EpR〇M 或者 EEPROM 0 137401.DOC •18- 201037800 上述各實施例中，基板之材質可為有機材質、陶瓷、 玻璃、矽或金屬等。 综上所述’藉由本發明揭示之凹穴晶片封裝結構可降 低晶片封裝後之高度’故可增加運用此結構之電子產品之 移動性。凹穴晶片封裝結構中具較佳電連接路徑之設計， 故可提高該電子產品之性能且不會造成訊號傳遞不良。同 時本發明揭示黏膠層可為薄膜覆蓋銲線（Film 〇n Wire ; 0 FOW)層，因此可降低封裝高度與提供導線保護之功效而 提昇導線之穩定度。 本發明之技術内容及技術特點已揭示如上，然而熟悉 本項技術之人士仍可能基於本發明之教示及揭示而作種 種不背離本發明精神之替換及修飾。因此，本發明之保護 範圍應不限於實施例所揭示者’而應包括各種不背離本發 明之替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡要說明】 〇 圖1顯示本發明之第一實施例之打線接合之凹穴晶片 封裝結構之示意圖； 圖2顯示本發明之第二實施例之打線接合之凹穴晶片 封裝結構之示意圖； 圖3顯示本發明之第三實施例之利用打線接合之凹穴 晶片封裝結構之示意圖； 圖4顯示本發明之一實施例之覆晶接合之凹穴晶片封 裝結構之示意圖； 圖5和圖6顯示本發明之其他實施例之覆晶接合之凹穴 U740J.DOC •19- 201037800 > 晶片封裝結構之示意圖； 圖7顯示本發明之第一實施例之多晶片堆疊之凹穴晶 片封裝結構之不意圖， 圖8顯示本發明之第二實施例之多晶片堆疊之凹穴晶 片封裝結構之示意圖； 圖9顯示本發明之第三實施例之多晶片堆疊之凹穴晶 片封裝結構之示意圖； 圖10顯示本發明之第四實施例之多晶片堆疊之凹穴晶 0 片封裝結構之示意圖； 圖11顯示本發明第一實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖； 圖12顯示本發明第二實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖； 圖13顯示本發明第三實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖； p 圖14顯示本發明第四實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖； 圖15顯示本發明第五實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖； 圖16顯示本發明第六實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖； 圖17顯示本發明第七實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖； 圖18顯示本發明第八實施例之具凹穴晶片封裝結構之 137401.DOC -20- 201037800 層疊封裝結構之示意圖；及 圖19顯示本發明第九實施例之具凹穴晶片封裝結構之 層疊封裝結構之示意圖。 【主要元件符號說明】 10a至10j 凹穴晶片封裝結構 12 弟·一晶片 14 第二晶片 15 弟二晶片137401.DOC -17- 201037800, the first package component 62h does not need to include the bumps 3 6 b on the connection point. The first package component 62h and the second package component 64 are electrically powered by the metal conductive materials 70. Sexual connection. In other embodiments, the structure of the second packaging element 64 can also be different than the first packaging element 62f. Fig. 19 is a view showing a laminated package structure 60i having a recessed chip package structure according to a ninth embodiment of the present invention. The akisaki-containing first package element and the second package element of the present embodiment are provided with a recessed chip package structure as shown in FIG. 1A and a substrate 18g thereof. The solder pads 38 on the two surfaces 22 are provided with a plurality of corresponding plurality of metal conductive materials 70. The first package components 62i and the second package components 64 are electrically connected by the metal conductive materials 7〇. In other embodiments, The structure of the second package component 64 may also be different from the first package component 62f. In another embodiment of the package structure, the first package component 62i may not need to include the bumps 36b on the connection point. The example has a recessed chip package structure, and the combination of the first package component and the second package component may be a combination of a memory chip package component and a memory chip package component, a memory chip package component, and a control chip package component. Combination of memory chip package component and special purpose integrated circuit ASIC chip package component, combination of memory chip package component and DSp chip package component; wherein the memory chip The type of component can be SRAM, DRAM, Flash, Mask R〇M, EpR〇M or EEPROM 0 137401.DOC • 18- 201037800 In the above embodiments, the material of the substrate can be organic material, ceramic, glass, germanium. Or metal, etc. In summary, the recessed chip package structure disclosed by the present invention can reduce the height of the package after the package is packaged, thereby increasing the mobility of the electronic product using the structure. The recessed chip package structure has better power. The design of the connection path can improve the performance of the electronic product without causing poor signal transmission. At the same time, the present invention discloses that the adhesive layer can be a film covering wire (Fif 〇n Wire; 0 FOW) layer, thereby reducing the package height. And improving the stability of the wire by providing the wire protection effect. The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various embodiments based on the teachings and disclosure of the present invention without departing from the spirit of the present invention. The invention is not limited to the scope of the invention, and should include various alternatives and modifications without departing from the invention. The following is a description of the scope of the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a wire-bonded recessed chip package structure according to a first embodiment of the present invention; FIG. 2 is a view showing a second embodiment of the present invention. FIG. 3 is a schematic view showing a recessed wafer package structure using wire bonding according to a third embodiment of the present invention; FIG. 4 is a view showing a flip chip bonded recess according to an embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 and FIG. 6 are views showing a flip chip U740J.DOC of the other embodiments of the present invention. FIG. 7 shows a first embodiment of the present invention. FIG. FIG. 8 is a schematic view showing a recessed chip package structure of a multi-wafer stack according to a second embodiment of the present invention; FIG. 9 is a view showing a multi-wafer of a third embodiment of the present invention; Schematic diagram of a stacked chip package structure; FIG. 10 is a schematic view showing a recessed wafer 0 package structure of a multi-wafer stack according to a fourth embodiment of the present invention; 11 is a schematic view showing a laminated package structure of a recessed chip package structure according to a first embodiment of the present invention; FIG. 12 is a schematic view showing a package package structure of a recessed chip package structure according to a second embodiment of the present invention; FIG. 14 is a schematic view showing a laminated package structure of a recessed chip package structure according to a fourth embodiment of the present invention; FIG. 15 is a view showing a fifth embodiment of the present invention; FIG. 16 is a schematic view showing a laminated package structure of a recessed chip package structure according to a sixth embodiment of the present invention; FIG. 17 is a view showing a recessed package structure of a seventh embodiment of the present invention; FIG. 18 is a schematic view showing a laminated package structure of a 137401.DOC-20-201037800 having a recessed chip package structure according to an eighth embodiment of the present invention; and FIG. 19 is a ninth embodiment of the present invention. A schematic diagram of a stacked package structure with a recessed chip package structure. [Main component symbol description] 10a to 10j pocket chip package structure 12 brother · one chip 14 second chip 15

❹ 16 黏膠層 18a至18g 基板 20 第一表面 22 第二表面 24 凹穴 26a、26b、26c、26d 連接黑占 27a 焊錫材料 28 焊墊 30 金屬導電料 3 2 底部 34 導線 36a、36b 凸塊 38 焊墊 40a、40b 階梯表面 42 第一晶片 44 凸塊 46、48第二晶片 137401.DOC -21- 201037800 50 第二晶片 52 第四晶片 54 黏膠層 60a至60i 層疊封裝結構 62a至62i 第一封裝元件 64 第二封裝元件 66 晶片 68 焊墊 70 金屬導電料 122、142、152、422、462、502 主動面 124 、 144 、 444 、 504 背面 126、146、156、426、466、486、506 焊#· 662 主動面 664 焊墊❹ 16 Adhesive layers 18a to 18g Substrate 20 First surface 22 Second surface 24 Recesses 26a, 26b, 26c, 26d Connection black 27a Solder material 28 Pad 30 Metal conductive material 3 2 Bottom 34 Conductors 36a, 36b Bumps 38 pads 40a, 40b step surface 42 first wafer 44 bumps 46, 48 second wafer 137401. DOC - 21 - 201037800 50 second wafer 52 fourth wafer 54 adhesive layers 60a to 60i laminated package structures 62a to 62i a package component 64 second package component 66 wafer 68 solder pad 70 metal conductive material 122, 142, 152, 422, 462, 502 active surface 124, 144, 444, 504 back surface 126, 146, 156, 426, 466, 486, 506 welding #· 662 active surface 664 pad

13740l.DOC •22-13740l.DOC •22-

Claims (1)

201037800 七、申請專利範圍： 1. 一種凹穴晶片封裝結構，包含： 一個第一晶片，包含一第一主動面、一第一背面和設 於該第一主動面上之複數個第一烊塾； 一基板，包含一第一表面及一相對於該第一表面之第 二表面，其中該第一表面具有一凹穴，並該第一晶片係配 置於該凹穴；以及 複數個連接點，設於該第一表面及該凹穴之底部中至 Ο 少一者之表面； 其中，該複數個第一焊墊與該複數個連接點係電性相 連。 2. 根據請求項i之凹六晶片封裝結構，其另包含複數個凸 塊，其中該複數個第一焊墊與該複數個連接點係藉由該複 數個凸塊而彼此電性相連。 3. 根據請求項2之凹穴晶片封裝結才鼻，其中該凸塊係錫錯凸 塊、無鉛凸塊、銅柱、金凸塊、高分子凸塊或結線凸塊、 〇 彈性凸塊或者是複合金屬凸塊。。 4. 根據請求項2之凹穴晶片封裝結構，其另包含一個第二晶 片及複數個第一導線，其中該第二晶片包含一第二主動 面 弟一责面和設於該第二主動面上之複數個第二焊 墊又該第—背面和該第一背面相接合，並該複數個第二 焊墊與該複數個第一連接點係藉由該複數個第一導線而 .彼此電性相連。 5. 根據請求項！之凹穴晶片封裝結構，其另包含設於該第一 表面上之複數個第一焊墊及分別設於該複數個第一焊墊 23 201037800 上之複數個第一金屬導電料。 6_根據請求項1之凹穴晶片封裝結構，其另包含一個第二晶 片、複數個導線及一黏膠層，其中該第二晶片包含一第二 主動面 第二背面和設於該第二主動面上之複數個第二 焊墊’又該第二背面和該第一主動面藉由該黏膠層相接 合，並該複數個第一焊墊及該複數個第二焊墊係藉由該複 數個導線與該複數個連接點電性相連。 7. 根據請求項6之凹穴晶片封裝結構，其中該黏膠層係一薄 ® 膜覆蓋銲線（Film on Wire ; FOW)層。 8. 根據請求項7之凹穴晶片封裝結構，該薄膜覆蓋銲線層係 包覆該導線之一部份。 9. 根據請求項4或6之凹穴晶片封裝結構，該些晶片之組合態 樣可以為s己憶體晶片與記憶體晶片之組合、記憶體晶片與 控制晶片之組合、記憶體晶片與特殊用途積體電路ASIC 晶片之組合、記憶體晶片與DSp晶片之組合；其中該記憶 體晶片之型態可為SRAM、DRAM、Flash、Mask ROM、 〇 EPROM 或者 EEPROM。 10. —種層疊封裝結構，包含： 一具請求項1至8之任一凹穴晶片封裝結構之第一封裝 元件’其中該第一封叢元件另包含設於該基板之該第二表 面上之複數第二焊墊及分別設於該複數個第二焊墊上之 複數個第二金屬導電料；以及 一第二封裝元件； 其中，該第二封裝元件係固定於該複數個第二金屬導 電料，並和該第一封裝元件電性相連。 24 201037800 11. 且^據請求項10之層疊封裝結構中該第二封裝 …月求項1至8之任一凹穴晶片封裝結構。 12·，據請求㈣之層㈣裝結構，其巾該㈣—封 第二封裝元件之組合態樣可以為記憶體晶片封裝 2 4憶體晶片封裝元件之組合、記憶體晶片封襄元件 ，、制晶片封裝元件之組合、記憶體晶片封敎元件與特 用途積體電路ASIC晶片封裝元件之組合、或記憶體晶片201037800 VII. Patent application scope: 1. A recessed chip package structure comprising: a first wafer comprising a first active surface, a first back surface, and a plurality of first defects disposed on the first active surface a substrate comprising a first surface and a second surface opposite to the first surface, wherein the first surface has a recess, and the first wafer is disposed in the recess; and a plurality of connection points, And providing a surface of the first surface and the bottom of the recess to at least one of the plurality of first pads; wherein the plurality of first pads are electrically connected to the plurality of connection points. 2. The recessed six-chip package structure of claim i, further comprising a plurality of bumps, wherein the plurality of first pads and the plurality of connection points are electrically connected to each other by the plurality of bumps. 3. According to claim 2, the recessed chip package is formed into a nose, wherein the bump is a tin bump, a lead-free bump, a copper pillar, a gold bump, a polymer bump or a wire bump, a 〇 elastic bump or It is a composite metal bump. . 4. The recessed chip package structure of claim 2, further comprising a second wafer and a plurality of first leads, wherein the second wafer includes a second active face and a second active surface The plurality of second pads further engage the first back surface and the first back surface, and the plurality of second pads and the plurality of first connection points are electrically connected to each other by the plurality of first wires Sexual connection. 5. According to the request item! The recessed chip package structure further includes a plurality of first pads disposed on the first surface and a plurality of first metal conductive materials respectively disposed on the plurality of first pads 23 201037800. 6_ The recessed chip package structure of claim 1, further comprising a second wafer, a plurality of wires and an adhesive layer, wherein the second wafer comprises a second active surface second back surface and is disposed on the second And the plurality of second pads and the first active surface are joined by the adhesive layer, and the plurality of first pads and the plurality of second pads are The plurality of wires are electrically connected to the plurality of connection points. 7. The recessed wafer package structure of claim 6, wherein the adhesive layer is a thin ® film-on-silicone (FOW) layer. 8. The recessed wafer package structure of claim 7, the film covering wire bonding layer covering a portion of the wire. 9. According to the recessed chip package structure of claim 4 or 6, the combination of the wafers may be a combination of a memory cell and a memory chip, a combination of a memory chip and a control chip, a memory chip and a special The combination of the integrated circuit ASIC chip, the combination of the memory chip and the DSp chip; wherein the memory chip can be in the form of SRAM, DRAM, Flash, Mask ROM, 〇EPROM or EEPROM. 10. A package structure comprising: a first package component of any of the recessed chip package structures of claims 1 to 8 wherein the first bush component further comprises a second surface disposed on the substrate a plurality of second pads and a plurality of second metal conductive materials respectively disposed on the plurality of second pads; and a second package component; wherein the second package component is fixed to the plurality of second metal conductive And electrically connected to the first package component. 24 201037800 11. The method according to claim 10, wherein the second package has any one of the recessed chip package structures of the second package. 12, according to the request (4) layer (four) mounting structure, the towel (4) - sealing the second package component combination can be a memory chip package 24 memory chip package component combination, memory chip package component, Combination of chip package components, combination of memory chip package components and special purpose integrated circuit ASIC chip package components, or memory chips 、裝το件與DSP晶片封裝元件之組合；其中該記憶體晶片 封裝兀件之型態可為SRAM、DRAM、&⑽、 EPROM 或者 EEPROM。 13’ 一種凹穴晶片封裝結構，包含： 背面和設於 複數個晶片，各該晶片包含一主動面 該主動面上之複數個焊墊； 基板，包含一第一表面及一相對於該第一表面之第 一表面，其中該第一表面具有一凹穴及圍繞於該凹穴之 至少一個階梯表面，並該複數個晶片係堆疊收容於該凹 穴内；以及 複數個連接點，設於該第一表面、該凹穴之底部及該 階梯表面中至少一者之表面； 其中該複數個焊墊與該複數個連接點係電性相連。 14*根據請求項13之凹穴晶片封裝結構，其另包含複數個 金屬導線’其中該複數個晶片之複數個焊墊分別藉由該複 數個金屬導線電性相連至對應之該階梯表面上之該複數 個連接點、該第一表面上之該複數個連接點及/或該凹穴 之該底部之該複數個連接點。 25 201037800 15.根據請求:ΠΐΐΑηπΑα , 項14之凹八晶片封裝結構’其另包含至少一 黏爆"層，兩相翻#曰u 相鄰該s曰片之該主動面及該背面藉由該黏膠層 相接合。 才據月长項i 5之凹穴晶片封裝結構，其中該黏膠層係 一薄膜覆蓋銲線層。 7根據咕求項16之凹穴晶片封裝結構，該薄膜覆蓋銲線 層係包覆該金屬導線之一部份。 Ο Ο 18.根據請求項13之凹穴晶片封裝結構，其另包含複數個 凸塊，其中該複數個焊塾與該複數個連接點係#由該複數 個凸塊而彼此電性相連。 19. 根據”月求項！ 8之凹穴晶片封裝結構，其中該凸塊係錫 錯凸塊、無錯凸塊、銅柱、金凸塊、高分子凸塊或結線凸 塊、彈性凸塊或者是複合金屬凸塊。 20. 根據請求項13之凹穴晶片封裝結構，其另包含複數個 金屬導線及複數個凸塊，其中一部分之該複數個晶片之該 複數個焊塾藉由該複數個金屬導線電性相連至對應之該 複數個連接點，另-部份之該複數個晶片之該複數個焊塾 藉由該複數個凸塊電性相連至對應之該複數個連接點。 21_根據請求項20之凹穴晶片封褒結構，其另包含至少一 薄膜覆蓋銲線層，兩才目鄰該晶片之一該主動面及一該背面 藉由該薄膜覆蓋銲線層相接合。 22. 根據請求項21之凹穴晶片封裝結構，其中該薄膜覆蓋 銲線層係包覆該金屬導線之一部份。 23. 根據請求項20之凹穴晶片封裴結構，其另包含至少一 黏著層，兩相鄰該晶片之兩該背面藉由該黏著層相接合。 26 201037800 • > 根據明求項13之凹穴晶片封裝結構，其另包含設於該 第表面上之複數個第一焊墊及分別設於該複數個第一 焊墊上之複數個第一金屬導電材。 25·根據請求項13之凹穴晶片封裝結構，其中該些晶片之 組合態樣可以為記憶體晶片與記憶體晶片之組合、記憶體 晶片與控制晶片之組合、記憶體晶片與特殊用途積體電路 ASIC晶片之組合或記憶體晶片與DSp晶片之組合·，其中該 6己憶體晶片之型態可為SRAM、DRAM、Flash、Mask 》 ROM、EPR〇m或者 EEPROM。 26. 一種層疊封裝結構，包含： 一具請求項13至24之任一凹穴晶片封裝結構之第一封 裝元件’其中該第一封裝元件另包含設於該基板之該第二 表面上之複數第二焊墊及分別設於該複數個第二焊墊上 之複數個第二金屬導電材；以及 一第二封裝元件； 其中’該第二封裝元件係固定於該複數個第二金屬導 》 電材’並和該第一封裝元件電性相連。 27. 根據請求項26之層疊封裝結構，其中該第二封裝元件 具請求項13至24之任一凹穴晶片封裝結構。 28. 根據請求項26之層疊封裝結構，其中該些第—封裝元 件與該第二封裝元件之組合態樣可以為記憶體晶片封裝 元件與記憶體晶片封裝元件之組合、記憶體晶片封裝元件 與控制晶片封裝元件之組合、記憶體晶片封裝元件與特殊 用途積體電路ASIC晶片封裝元件之組合、或記憶體晶片 封裝元件與DSP晶片封裝元件之組合；其中該記憶體晶片 27 201037800 封裝元件之型態可為SRAM、DRAM、Flash、Mask ROM、 EPROM 或者 EEPROM。 oThe combination of the device and the DSP chip package component; wherein the memory chip package component can be SRAM, DRAM, & (10), EPROM or EEPROM. 13' A recessed chip package structure comprising: a back surface and a plurality of wafers, each of the wafers comprising a plurality of pads on the active surface; the substrate comprising a first surface and a first surface a first surface of the surface, wherein the first surface has a recess and at least one stepped surface surrounding the recess, and the plurality of wafer stacks are received in the recess; and a plurality of connection points are disposed in the first surface a surface, a bottom of the recess, and a surface of at least one of the step surfaces; wherein the plurality of pads are electrically connected to the plurality of connection points. 14* The recessed chip package structure of claim 13, further comprising a plurality of metal wires, wherein a plurality of pads of the plurality of transistors are electrically connected to the corresponding step surface by the plurality of metal wires respectively The plurality of connection points, the plurality of connection points on the first surface, and/or the plurality of connection points of the bottom of the cavity. 25 201037800 15. According to the request: ΠΐΐΑηπΑα, item 14 of the concave eight-chip package structure 'which further comprises at least one viscous " layer, two-phase flip #曰u adjacent to the active surface of the s-chip and the back side by The adhesive layers are joined. According to the recessed chip package structure of the moon length item i 5, wherein the adhesive layer is a film covering the wire bonding layer. 7. The recessed wafer package structure of claim 16, wherein the thin film overlay wire layer covers a portion of the metal wire.凹 Ο 18. The recessed chip package structure of claim 13, further comprising a plurality of bumps, wherein the plurality of solder bumps and the plurality of bumps are electrically connected to each other by the plurality of bumps. 19. According to the "monthly project! 8 recessed chip package structure, wherein the bump is tin bump, no bump, copper pillar, gold bump, polymer bump or knot bump, elastic bump Or a composite metal bump. 20. The recessed chip package structure of claim 13, further comprising a plurality of metal wires and a plurality of bumps, wherein a plurality of the plurality of solder pads of the plurality of wafers are by the plurality The plurality of metal wires are electrically connected to the plurality of connection points, and the plurality of solder pads of the plurality of the plurality of pads are electrically connected to the corresponding plurality of connection points by the plurality of bumps. The recessed wafer package structure of claim 20, further comprising at least one film covering wire bond layer adjacent to the active surface of the wafer and the back surface being joined by the film covering wire bond layer. 22. The recessed chip package structure of claim 21, wherein the thin film overlying wire bond layer covers a portion of the metal wire. 23. The recessed wafer package structure of claim 20, further comprising at least one Adhesive layer, two adjacent to the wafer The back surface is bonded by the adhesive layer. 26 201037800 • > The recessed chip package structure of claim 13 further comprising a plurality of first pads disposed on the first surface and respectively disposed on the plurality The plurality of first metal conductive materials on the first bonding pad. The recessed chip package structure according to claim 13, wherein the combination of the chips can be a combination of a memory chip and a memory chip, and a memory chip Combination with a control chip, a combination of a memory chip and a special-purpose integrated circuit ASIC chip, or a combination of a memory chip and a DSp chip, wherein the type of the 6-reproduced chip can be SRAM, DRAM, Flash, Mask ROM, EPR〇m or EEPROM 26. A stacked package structure comprising: a first package component of any of the recessed chip package structures of claims 13 to 24, wherein the first package component further comprises a substrate a plurality of second pads on the second surface and a plurality of second metal conductive materials respectively disposed on the plurality of second pads; and a second package component; wherein the second seal The component is fixed to the plurality of second metal conductors and electrically connected to the first package component. 27. The package structure according to claim 26, wherein the second package component has the requirements of claims 13 to 24. A cavity chip package structure. 28. The package structure of claim 26, wherein the combination of the first package component and the second package component is a combination of a memory chip package component and a memory chip package component a combination of a memory chip package component and a control chip package component, a combination of a memory chip package component and a special purpose integrated circuit ASIC chip package component, or a combination of a memory chip package component and a DSP chip package component; wherein the memory Wafer 27 201037800 The package component type can be SRAM, DRAM, Flash, Mask ROM, EPROM or EEPROM. o 2828
TW098112436A 2009-04-15 2009-04-15 Cavity chip package structure and package-on-package using the same TWI387068B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW098112436A TWI387068B (en) 2009-04-15 2009-04-15 Cavity chip package structure and package-on-package using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW098112436A TWI387068B (en) 2009-04-15 2009-04-15 Cavity chip package structure and package-on-package using the same

Publications (2)

Publication Number Publication Date
TW201037800A true TW201037800A (en) 2010-10-16
TWI387068B TWI387068B (en) 2013-02-21

Family

ID=44856816

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098112436A TWI387068B (en) 2009-04-15 2009-04-15 Cavity chip package structure and package-on-package using the same

Country Status (1)

Country Link
TW (1) TWI387068B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
TWI582864B (en) * 2015-12-09 2017-05-11 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof
US10812017B1 (en) * 2019-08-02 2020-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor package structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW498507B (en) * 2001-06-28 2002-08-11 Advanced Semiconductor Eng Multi-chip packaging module
TW200612345A (en) * 2004-10-07 2006-04-16 Advanced Flash Memory Card Technology Co Ltd Structure of memory card and producing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9449941B2 (en) 2011-07-07 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting function chips to a package to form package-on-package
TWI581400B (en) * 2011-07-07 2017-05-01 台灣積體電路製造股份有限公司 Package-on-packages and method of forming the same
TWI582864B (en) * 2015-12-09 2017-05-11 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof
CN106856174A (en) * 2015-12-09 2017-06-16 南茂科技股份有限公司 Semiconductor packaging structure and manufacturing method thereof
CN106856174B (en) * 2015-12-09 2019-04-30 南茂科技股份有限公司 Semiconductor packaging structure and manufacturing method thereof
US10812017B1 (en) * 2019-08-02 2020-10-20 Advanced Semiconductor Engineering, Inc. Semiconductor package structure
US11296651B2 (en) 2019-08-02 2022-04-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure

Also Published As

Publication number Publication date
TWI387068B (en) 2013-02-21

Similar Documents

Publication Publication Date Title
TW544901B (en) Semiconductor device and manufacture thereof
TWI335658B (en) Stacked structure of chips and wafer structure for making same
US7462930B2 (en) Stack chip and stack chip package having the same
TWI290365B (en) Stacked flip-chip package
TWI277187B (en) Semiconductor device and manufacturing method for the same
JP5215244B2 (en) Semiconductor device
KR20030075860A (en) Structure for stacking semiconductor chip and stacking method
JP2009099697A (en) Semiconductor apparatus and method of manufacturing the same
JP4896010B2 (en) Multilayer semiconductor device and manufacturing method thereof
TW200531188A (en) Land grid array packaged device and method of forming same
CN101872757A (en) Recess chip packaging structure and laminated packaging structure using same
TWI225291B (en) Multi-chips module and manufacturing method thereof
TWI406376B (en) Semiconductor chip package
CN101872749B (en) Recess chip packaging structure and laminated packaging structure using same
TW201021179A (en) Flip-chip chip-scale package structure
TWI246170B (en) Super-thin high speed flip chip package
TW201037800A (en) Cavity chip package structure and package-on-package using the same
TW200529388A (en) Chip package
TWI442522B (en) Cavity chip package structure and package-on-package using the same
JP2007214238A (en) Semiconductor device and its manufacturing method
TW200529387A (en) Chip package structure
TW200903662A (en) Multichip stack structure and method for fabricating the same
TWI409933B (en) Chip stacked package structure and its fabrication method
US20180158764A1 (en) 3d chip assemblies using stacked leadframes
TW201208035A (en) Multi-chip stacked assembly with ground connection of EMI shielding