CN103000649B - A kind of cmos image sensor encapsulating structure and manufacture method thereof - Google Patents
A kind of cmos image sensor encapsulating structure and manufacture method thereof Download PDFInfo
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Abstract
A kind of cmos image sensor encapsulating structure and manufacture method thereof, belong to sensor field.Optics interactive areas is positioned at the central authorities of silicon substrate front first surface, above optics interactive areas, be formed with metal interconnecting layer, and micro lens arrays is placed on above metal interconnection layer, has the first protective layer outside metal interconnection layer; Make the silicon through hole and the redistribution layer that do not penetrate silicon substrate at first surface, the I/O around optics interactive areas connects silicon through hole by redistribution layer; Silicon through hole hole wall makes passivation layer and fills; Redistribution layer has the second protective layer; Silicon substrate, with sheet glass bonding, establishes cavity between sheet glass and silicon substrate; The second surface of silicon substrate is thinning exposes silicon through hole; Silicon substrate second surface makes line layer and silicon through hole is connected to pad pad, line layer makes welding resisting layer and exposes pad pad; Soldered ball is on pad pad.Present invention improves the lamination problem in encapsulating structure between glass and silicon substrate, improve reliability, encapsulating structure is applicable to more large size chip.
Description
Technical field
The present invention relates to semiconductor components and devices manufacturing technology field.The invention provides the manufacture method of a kind of cmos image sensor encapsulating structure and described cmos image sensor.
Background technology
Imageing sensor belongs to the photoelectric cell class in opto-electronics.Being a kind of semiconductor module, is a kind of equipment optical imagery being converted into electronic signal, and electronic signal is stored after can being used to do and processing further or be digitized, or for image transfer is shown to another display unit.It is widely used in digital camera and other electro-optical devices.Nowadays imageing sensor is mainly divided into charge coupled device (CCD) and cmos image sensor (CIS, CMOS Image Sensor).Although ccd image sensor is better than cmos image sensor in picture quality and noise etc., cmos sensor can with traditional semiconductor fabrication techniques manufacture, and production cost is lower.Simultaneously because parts number used is relatively less and signal transmission distance is short, cmos image sensor possesses the advantages such as low in energy consumption, electric capacity, inductance and stray delay reduction.
Compared with ccd image sensor, cmos image sensor has drive pattern and can realize various scan type more easily; Meanwhile, signal processing circuit (IC) to be integrated in one single chip thus to make miniaturized cmos image sensor become possibility.In addition, by using extensively compatible CMOS technology, cmos image sensor contributes to lower power consumption and reduces manufacturing cost.Therefore, cmos image sensor has and applies widely.
Figure 1 shows that the encapsulation schematic diagram of a traditional cmos image sensor (CIS).Shown cmos sensor is logical to be comprised: ceramic bases 2, ceramic bases 2 top surface is provided with integrated circuit 4 (IC), and bond layer 3 is positioned between integrated circuit 4 (IC) and ceramic bases 2.There is the pad 6 on the IC surface made at integrated circuit 4 (IC) on the surface, 7 to be connected with the pad 8 of the substrate surface in ceramic bases 2 by going between.Image sensitive district 5 is positioned at the top of integrated circuit 4 (IC), and image sensitive district 5 comprises can accept optics interactive elements (as photosensitive electric diode, the photodiode) array that light produces the signal of telecommunication.Be installed on framework 1 with the glass lens 10 that described optics interactive elements is corresponding, framework 1 is connected with ceramic bases 2 by bonding agent 9.
Cmos sensor structure shown in Fig. 1 has the aspect much can improved.The first, because this encapsulation employs bulky glass lens 10, this is totally unfavorable to the volume reducing encapsulation, therefore can reduce by adopting lenticule the volume encapsulated.Second, ceramic bases 2 can be changed to silicon substrate, by making redistribution layer (RDL) in surface of silicon, the I/O (not shown on figure) at integrated circuit 4 (IC) edge being connected with the pad 8 on surface, base, further can reducing the size of encapsulating structure like this.3rd, shown encapsulating structure can not with the lower wafer level processing of cost and surface mounting technology.
Growing along with CMOS technology, integrated level is also more and more higher, and this just makes the area in image sensing district more and more come to realize more large-area photosensitive region.And for employing glass with this CIS encapsulating structure of wafer bonding, larger sight-seeing area area can cause glass also more and more serious with the lamination between silicon substrate.
For overcoming the above problems, the invention provides a kind of cmos image sensor (CIS) encapsulating structure.By at the raised structures of glass with the bond area setting table stepwise between Semiconductor substrate, strengthen Semiconductor substrate with the bonding reliability between glass, thus the lamination problem improved in existing encapsulating structure between glass and silicon substrate, improve package reliability, make this encapsulating structure be applicable to the larger chip size packages of chip size simultaneously.Embodiments of the present invention additionally provide the manufacture method that a kind of described cmos image sensor (CIS) encapsulates simultaneously, by making silicon through hole (TSV) in silicon substrate front, and be connected by the I/O of circuit redistribution layer with periphery, optics interactive areas, the back side of silicon substrate is connected to through TSV.Not only reduce the volume size after encapsulation by enforcement of the present invention, reduce packaging cost, improve packaging efficiency, and more meet the requirement of high-density packages; Simultaneously due to because data transfer path is short, stability is high, this be encapsulated in reduce energy consumption while also improve speed and the stability of transfer of data.
Summary of the invention
A first aspect of the present invention is: cmos image sensor (CIS) encapsulating structure providing a kind of improvement, with cmos image sensor (CIS) encapsulation that applicable chip size is larger.
Cmos image sensor of the present invention comprises: silicon substrate 200, and the front of described silicon substrate 200 is the first surface 201 being formed with micro lens 230, metal interconnecting layer 220 and optics interactive areas 210, and the back side of described silicon substrate 200 is second surface 202.Wherein optics interactive areas 210 is positioned at the central authorities of silicon substrate 200 front first surface 201; metal interconnecting layer 220 is formed above optics interactive areas 210; micro lens 230 array is placed on above metal interconnecting layer 220, is formed with the first protective layer 235 outside metal interconnecting layer 220.By making the silicon through hole 260 (TSV) and redistribution layer (RDL) that do not penetrate silicon substrate 200 at first surface 201, the I/O around optics interactive areas 210 is connected to silicon through hole 260 (TSV) by redistribution layer (RDL).Silicon through hole 260 (TSV) hole wall is manufactured with and makes passivation layer 265 and with electroplating technology, hole filled.Redistribution layer (RDL) has by polymeric material the second protective layer 240 of step projection or groove structure.Silicon substrate 200 is bonded together by polymer bonds rubber alloy 255 with between sheet glass 250, forms cavity by exposure imaging between sheet glass 250 and silicon substrate 200.By grinding the second surface 202 of silicon substrate 200, the technique such as etching, carry out thinning to silicon substrate and expose silicon through hole 260 (TSV).By making line layer on the second surface 202 of silicon substrate 200, silicon through hole 260 (TSV) being connected to pad pad 290, line layer making welding resisting layer 280 (SMF) and exposes pad pad 290 to protect the line layer on second surface 202.Soldered ball 295 is produced on pad pad 290.
Described protective layer material is silicon nitride.Described polymeric material is for be made up of resin, solvent, Photoactive compounds and additive etc.
A second aspect of the present invention there is provided a kind of manufacture method manufacturing described cmos image sensor, comprises the following steps:
The first step: silicon substrate is provided
Described silicon substrate comprises and is formed with micro lens, the first surface of integrated circuit (IC) and optics interactive areas and the second surface relative to first surface.
Second step: etch TSV hole at the first surface of silicon substrate
In this step, be first coated with one deck photoresist in silicon substrate front, form etching window through exposure imaging; Adopt dry method etch technology to form TSV hole, described dry method etch technology comprises deep reaction ion etching (DRIE).
3rd step: form one deck passivation layer with the first surface of silicon substrate in TSV hole
In TSV hole, form one deck passivation layer by using plasma chemical vapour deposition (CVD) (PECVD) with the front of silicon substrate, described passivation material is polymer dielectric material.
4th step: the I/O exposing periphery, optics interactive areas
Carry out exposure imaging by the passivation layer deposited silicon substrate first surface and form etching window, adopt dry etching to expose the I/O of periphery, optics interactive areas.
5th step: plating is filled TSV and realized electrical interconnects
By electroplating technology, the TSV holes filling of formation is covered first surface, thus silicon through hole (TSV) is connected with the I/O of optics interactive areas periphery form redistribution layer (RDL), realize electrical interconnects.
6th step: form protective layer and settle micro lens
When the first surface of silicon substrate forms the second protective layer, by exposure imaging and etch process at silicon substrate with the projection of bonding region forming station stepwise of glass or the second protective layer of groove structure; Then above the first surface metal interconnecting layer of silicon substrate, micro lens is settled.
7th step: silicon substrate carries out bonding with glass
In this step, first polymer bonds rubber alloy is coated on the glass surface crossed through pretreatment cleaning, pretreatment cleaning comprises pickling neutralization, plasma cleaning etc.; Then on polymer bonds rubber alloy, cavity is formed through exposure imaging etc. technique; Be coated with one deck resin glue finally by polymer bonds rubber alloy surface and utilize key and board that silicon substrate is carried out bonding with glass.
8th step: grinding etching is carried out to silicon substrate second surface
In this step, first grinding is carried out to the second surface of silicon substrate thinning; Secondly destressing plasma etching is carried out to the second surface of the silicon substrate after grinding, removing because grinding the internal stress remained in wafer, reducing the warpage of wafer and exposing silicon through hole (TSV).
9th step: the line layer making silicon substrate second surface
In this step, first at silicon substrate backside deposition one layer insulating; Then by sputtering layer of metal and by the formation of its patterning to form line layer and pad pad; Final online road floor be coated with one deck welding resisting layer (SMF) and expose pad pad and the circuit of protection formation.
Tenth step: make soldered ball
By planting ball technique, soldered ball is formed with on pad pad.
In the 7th described step, polymer latex can also be selected as dry film (Dry Film), described dry film forms by by resin, solvent, Photoactive compounds and additive etc., then can save the bonding having carried out same wafer on polymer latex surface by being coated with this step process of bonded adhesives, dry film used just directly can carry out bonding with wafer without painting bonded adhesives, decreases technological process.
The present invention is by making projection or the groove structure of step in silicon substrate front, effectively increase glass with the bond strength between silicon substrate, improve glass with the layering between wafer, improve the reliability of encapsulation, make described encapsulation be applicable to the larger CIS encapsulation of chip size.According to the embodiment of the present invention, the manufacture method of the described cmos image sensor provided, first have employed dry film as the bonding material between glass and wafer simultaneously; Secondly the destressing plasma etching taked after thinning to wafer can effectively to be removed in wafer due to the internal stress that grinding produces, and improves the warpage situation of wafer, thus further facilitates later technological operation.These steps decrease the yield also improving product while technological process improves product reliability production efficiency and reduce production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of a traditional cmos sensor (CIS).
Fig. 2 is the schematic diagram that the cmos image sensor drawn according to embodiments of the invention encapsulates.
Fig. 3 (a) is the manufacturing process generalized section of the cmos sensor according to embodiments of the invention drafting to (j).
In figure: 1. framework, 2. ceramic bases, 3. bond layer, 4. integrated circuit, 5. image sensitive district, the pad on 6.IC surface, 7. go between, 8. the pad of substrate surface, 9. bonding agent, 10. glass lens, 200. silicon substrate, 201. first surface, 202. second surface, 210. optics interactive areas, 220. metal interconnecting layer, 225. hole, 230. micro lens, 235. first protective layers, 240. second protective layers, 250. sheet glass, 255. polymer bonds rubber alloies, 260. silicon through holes, 261.TSV hole, 265. passivation layer, 270. insulating barrier, 280. welding resisting layer, 290. pad pads, 295. soldered ball.
Embodiment
The present invention carrys out the adhesion of reinforcing glass sheet 250 with silicon substrate 200 by the projection or groove structure making step on the first surface 201 of silicon substrate 200, improve glass with the lamination problem between silicon substrate, improve the reliability of encapsulation and be applicable to larger cmos image sensor (CIS) encapsulation of chip size.Fig. 2 is that the CIS of the step raised structures of making on the first surface 201 of silicon substrate 200 drawn according to embodiments of the invention encapsulates schematic diagram.
Shown in Fig. 2, the cmos image sensor (CIS) of embodiment of the present invention comprises: silicon substrate 200, the front of described silicon substrate 200 is the first surface 201 being formed with micro lens 230, metal interconnecting layer 220 and optics interactive areas 210, and the back side of described silicon substrate 200 is second surface 202.Wherein optics interactive areas 210 is positioned at the central authorities of first surface 201 above silicon substrate 200; metal interconnecting layer 220 is formed above optics interactive areas 210; micro lens 230 array is placed on above metal interconnecting layer 220, is formed with the first protective layer 235 outside metal interconnecting layer 220.By making the silicon through hole 260 (TSV) and redistribution layer (RDL) that do not penetrate silicon substrate 200 at first surface 201, the I/O around optics interactive areas 210 is connected to silicon through hole 260 (TSV) by redistribution layer (RDL).Silicon through hole 260 (TSV) hole wall is manufactured with and makes passivation layer 265 and with electroplating technology, hole filled.And in redistribution layer (RDL), the second protective layer 240 of step projection or groove structure is manufactured with polymeric material.Silicon substrate 200 is bonded together by polymer bonds rubber alloy 255 with between sheet glass 250, is formed with cavity by exposure imaging between sheet glass 250 and silicon substrate 200.By grinding the second surface 202 of silicon substrate 200, the technique such as etching, carry out thinning to silicon substrate and expose silicon through hole 260 (TSV).By making line layer on the second surface 202 of silicon substrate 200, silicon through hole 260 (TSV) being connected to pad pad 290, line layer making welding resisting layer 280 (SMF) and exposes pad pad 290 to protect the line layer on second surface 202.Soldered ball 295 is produced on pad pad 290.
The manufacturing process of the cmos image sensor of the present embodiment is described in detail below in conjunction with Fig. 3 (a) to (j).Fig. 3 (a) is the manufacturing process generalized section of the cmos image sensor according to embodiments of the invention drafting to (j).
First please refer to Fig. 3 (a), provide silicon substrate 200, the front of described silicon substrate 200 is the first surface 201 for the formation of there being electronic device, and the back side of silicon substrate 200 is second surface 202.Figure comprises: optics interactive areas 210, metal interconnecting layer 220 and the first protective layer 235.Optics interactive areas 210 is positioned at the central authorities of silicon substrate 200 first surface 201; metal interconnecting layer 220 is formed above optics interactive areas 210; micro lens 230 array is placed on above metal interconnecting layer 220, is formed with the first protective layer 235 outside metal interconnecting layer 220.Wherein in optics interactive areas 210, array has multiple photodiode and is connected respectively multiple transistor (not shown)s of bright diode.
Next please refer to Fig. 3 (b), etch TSV hole 261 at silicon substrate first surface 201.
This step comprises following steps: (a) is coated with one deck photoresist by photoresist spinner at silicon substrate first surface 201, and carries out exposure imaging to need the position of drilling to form etching window to photoresist; B () adopts dry method etch technology to form TSV hole 261, described dry method etch technology comprises deep reaction ion etching (DRIE).
Next please refer to Fig. 3 (c), in TSV hole 261, form one deck passivation layer 265 with silicon substrate front 201.
The making of passivation layer 265 can using plasma chemical vapour deposition (CVD) (PECVD), and the material of passivation layer 265 can be oxide (as silicon dioxide), also can be nitride (as silicon nitride).
Next please refer to Fig. 3 (d), expose the I/O of periphery, optics interactive areas 210.
Exposure imaging is carried out by the passivation layer 265 deposited silicon substrate first surface 201, form etching window in peripheral I/O (not shown) corresponding position, Optical Region 210, then adopt dry etching formation hole 225 to expose the I/O of periphery, optics interactive areas 210.
Next please refer to Fig. 3 (e), plating is filled.
Completed to the filling of TSV hole 261 and hole 225 to form silicon through hole 260 (TSV) structure by electroplating technology, packing material can be the conductive substrates of metal or alloy material; By carrying out patterning to form redistribution layer (RDL) to plating in the conductive substrates of silicon substrate first surface 201, realize the electric connection of I/O to silicon through hole 260 (TSV) of periphery, optics interactive areas 210.
Next please refer to Fig. 3 (f), form the second protective layer 240 at silicon substrate first surface 201 and settle micro lens 230.
This step comprises following steps: (a) makes the second protective layer 240 at silicon substrate first surface 201; B () forms etching window by exposure imaging on the second protective layer 240; C (), by being etched in second protective layer 2240 of silicon substrate 200 with sheet glass 250 bonding region with the projection of forming station stepwise or groove structure, forms open optical groove in order to place micro lens 230 by carrying out etching to optics interactive areas 210 and metal interconnecting layer 220 top; D () makes the array of micro lens 230 in open optical groove.
Next please refer to Fig. 3 (g), silicon substrate 200 carries out bonding with sheet glass 250.
This step comprises following steps: (a) carries out preliminary treatment cleaning to sheet glass 250, and preliminary treatment cleaning comprises pickling neutralization, plasma cleaning etc.; B () by forming one layer of polymeric bonding glue 255 at glass surface, and carries out exposure imaging to form the polymer bonds rubber alloy 255 of band cavity structure to polymer bonds rubber alloy 255; C silicon substrate 200 is carried out bonding with sheet glass 250 by bonding machine platform by ().
Next please refer to Fig. 3 (h), grinding etching is carried out to silicon substrate second surface 202.
This step comprises following steps: (a) grinds silicon substrate second surface 202, and the thickness of silicon substrate 200 is down to 100 ~ 150 microns from 600 ~ 700 microns; B () carries out destressing plasma etching to silicon substrate second surface 202, thus remove the internal stress due to grinding generation in silicon substrate 200, improves the warpage of structure, and exposes silicon through hole 260 (TSV).
Next please refer to Fig. 3 (i), make the line layer of silicon substrate second surface 202.
This step comprises following steps: (a) deposits a layer insulating 270 at silicon substrate second surface 202, and exposes silicon through hole 260 (TSV) by exposure imaging; B () adopts physical vapour deposition (PVD) (PVD) to sputter the conductive substrates of layer of metal or alloy on insulating barrier 270 surface, and by exposure imaging, its patterning is formed to form line layer and pad pad 290, silicon through hole 260 (TSV) is connected with pad pad 290; C () makes one deck welding resisting layer 280 (SMF) and pad pad 290 is come out on silicon substrate second surface 202 line layer.
Next please refer to Fig. 3 (j), make soldered ball 295.
By planting ball technique, soldered ball 295 is formed on pad pad 290.
To be object be effectively illustrates and describe the present invention in the description of the embodiment that the present invention carries out, but only should not be construed as by example the scope of the present invention limiting and defined by claims by this.Technical staff belonging to any this area without departing from the spirit and scope of the present invention, can make possible variation and amendment.Therefore protection of the present invention covers the amendment in the essence of an invention that defines of claim and scope.
Claims (4)
1. a cmos image sensor encapsulating structure, it is characterized in that: it comprises silicon substrate (200), the front of described silicon substrate (200) is for being formed with the first surface (201) of micro lens (230), metal interconnecting layer (220) and optics interactive areas (210), and the back side of described silicon substrate (200) is second surface (202); Wherein optics interactive areas (210) are positioned at the central authorities in silicon substrate (200) front first surface (201), metal interconnecting layer (220) is formed in the top of optics interactive areas (210), micro lens (230) array is placed on metal interconnecting layer (220) top, and metal interconnecting layer (220) outside is formed with the first protective layer (235); By making the silicon through hole (260) and the redistribution layer that do not penetrate silicon substrate (200) at first surface (201), optics interactive areas (210) I/O is around connected to silicon through hole (260) by redistribution layer; Silicon through hole (260) hole wall is manufactured with and makes passivation layer (265) and with electroplating technology, hole filled; Redistribution layer has by polymeric material second protective layer (240) of staircase structural model; Be bonded together by polymer bonds rubber alloy (255) between silicon substrate (200) same to sheet glass (250), between sheet glass (250) and silicon substrate (200), be provided with the cavity that exposure imaging is formed; Grind by the second surface (202) to silicon substrate (200), etch, to silicon substrate (200) carry out thinning after expose silicon through hole (260); Silicon through hole (260) is connected to pad pad (290) by the upper line layer that makes of the second surface (202) in silicon substrate (200), line layer makes welding resisting layer (280) and exposes pad pad (290) to protect the line layer on second surface (202); Soldered ball (295) is produced on pad pad (290).
2. a kind of cmos image sensor encapsulating structure according to claim 1, is characterized in that: the staircase structural model on described second protective layer (240) is projection or groove structure.
3. a manufacture method for the cmos image sensor encapsulating structure described in manufacturing claims 1, is characterized in that: comprise the following steps:
The first step: silicon substrate is provided;
Described silicon substrate comprises and is formed with micro lens, the first surface of integrated circuit (IC) and optics interactive areas and the second surface relative to first surface;
Second step: etch TSV hole at the first surface of silicon substrate;
In this step, be first coated with one deck photoresist in silicon substrate front, form etching window through exposure imaging; Adopt dry method etch technology to form TSV hole, described dry method etch technology comprises deep reaction ion etching;
3rd step: form one deck passivation layer with the first surface of silicon substrate in TSV hole;
In TSV hole, form one deck passivation layer by using plasma chemical vapour deposition (CVD) with the front of silicon substrate, described passivation material is polymer dielectric material;
4th step: the I/O exposing periphery, optics interactive areas;
Carry out exposure imaging by the passivation layer deposited silicon substrate first surface and form etching window, adopt dry etching to expose the I/O of periphery, optics interactive areas;
5th step: plating is filled TSV and realized electrical interconnects;
By electroplating technology, the TSV holes filling of formation is covered first surface, thus silicon through hole (TSV) is connected with the I/O of optics interactive areas periphery form redistribution layer (RDL), realize electrical interconnects;
6th step: form protective layer and settle micro lens;
When the first surface of silicon substrate forms the second protective layer, by exposure imaging and etch process at silicon substrate with the projection of bonding region forming station stepwise of glass or the second protective layer of groove structure; Then above the first surface metal interconnecting layer of silicon substrate, micro lens is settled;
7th step: silicon substrate carries out bonding with glass;
In this step, first polymer bonds rubber alloy is coated on the glass surface crossed through pretreatment cleaning, pretreatment cleaning comprises pickling neutralization, plasma cleaning etc.; Then on polymer bonds rubber alloy, cavity is formed through exposure imaging etc. technique; Be coated with one deck resin glue finally by polymer bonds rubber alloy surface and utilize key and board that silicon substrate is carried out bonding with glass;
8th step: grinding etching is carried out to silicon substrate second surface;
In this step, first grinding is carried out to the second surface of silicon substrate thinning; Secondly destressing plasma etching is carried out to the second surface of the silicon substrate after grinding, removing because grinding the internal stress remained in wafer, reducing the warpage of wafer and exposing silicon through hole;
9th step: the line layer making silicon substrate second surface;
In this step, first at silicon substrate backside deposition one layer insulating; Then by sputtering layer of metal and by the formation of its patterning to form line layer and pad pad; Final online road floor be coated with one deck welding resisting layer (SMF) and expose pad pad and the circuit of protection formation;
Tenth step: make soldered ball;
By planting ball technique, soldered ball is formed with on pad pad.
4. manufacture method according to claim 3, it is characterized in that: in the 7th described step, polymer bonds rubber alloy is replaced with dry film, described dry film is the material including free resin, solvent, Photoactive compounds and additive, now save the bonding having carried out same wafer on polymer bonds rubber alloy surface by being coated with this step process of bonded adhesives, dry film used without painting bonded adhesives just direct same wafer carry out bonding, decrease technological process.
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| EP3503190A1 (en) * | 2017-12-22 | 2019-06-26 | Pioneer Materials Inc. Chengdu | Cmos image sensor encapsulation structure and method for manufacturing the same |
| EP3503191A3 (en) * | 2017-12-22 | 2019-07-03 | Pioneer Materials Inc. Chengdu | Cmos image sensor encapsulation structure and method for manufacturing the same |
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| CN103000649A (en) | 2013-03-27 |
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