CN109638031B - High-pixel CIS wafer-level fan-out type packaging structure and manufacturing method thereof - Google Patents
High-pixel CIS wafer-level fan-out type packaging structure and manufacturing method thereof Download PDFInfo
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- CN109638031B CN109638031B CN201811548617.1A CN201811548617A CN109638031B CN 109638031 B CN109638031 B CN 109638031B CN 201811548617 A CN201811548617 A CN 201811548617A CN 109638031 B CN109638031 B CN 109638031B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 238000002161 passivation Methods 0.000 claims abstract description 28
- 229910000679 solder Inorganic materials 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 238000003466 welding Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 description 16
- 230000008054 signal transmission Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004313 glare Effects 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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- 238000005476 soldering Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
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Abstract
The invention discloses a high-pixel CIS wafer-level fan-out type packaging structure, which comprises: a transparent substrate having a chip cavity and a photosensitive area cavity; a first wiring layer disposed on the upper surface of the transparent substrate and the inner surface of the chip cavity; the first passivation layer covers the upper surface of the transparent substrate, the inner surface of the chip cavity and the first wiring layer except for the bonding pad; a die bond structure disposed on a pad of the first routing layer of the die cavity region; a CIS chip located in the chip cavity and flip-chip bonded to the chip bonding structure; a second passivation layer covering the back surface of the CIS chip and the top surface of the transparent substrate; a second routing layer electrically interconnected with the first routing layer; and an external solder ball.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a high-pixel CIS wafer level fan-out type packaging structure and a manufacturing method thereof.
Background
The market of the CIS (CMOS Image Sensor) is more and more widely used, and the pixel and sensitivity of the CIS are higher and higher as the technology is developed. The packaging of the CIS has a significant influence on the performance, reliability and life of the product, and meanwhile, in combination with the cost of the packaging, the wafer level packaging gradually becomes the mainstream of the CIS packaging.
There are two main types of conventional CIS packages. 1) The CIS wafer level packaging technology has the structure that glass is bonded on the front side, and pins are led out through TSV holes on the back side. This technique has the following problems: due to the problems of refractive index and the like, thick glass on the surface of the packaging structure is easy to generate influences such as light dazzling and the like on incident light; the back TSV technology has large signal transmission loss; with the increase of pixels, the data processing amount of a single chip is also increased, the number of IO pins of the chip is also increased, and the conventional Fan-in scheme is limited by the size of the chip and cannot realize multi-pin lead-out; high pixel CIS packages also require an increase in the front glass to photosurface distance. The conventional wafer level packaging distance is generally 30/40um, and the requirement of high pixel packaging cannot be met. 2) COB wire bonding packaging technology. The problems with this technique are as follows: dust control is very difficult, an ultra-high clean room grade is required, and manufacturing maintenance cost is high; the product design is customized, the period is long, and the flexibility is not enough; high efficiency packaging at the wafer level cannot be achieved.
The invention provides a novel high-pixel CIS wafer level Fan-out type packaging structure and a manufacturing method thereof, aiming at the problems that the existing CIS wafer level packaging has a light glare phenomenon and large signal transmission loss, a Fan-in scheme cannot meet multi-pin packaging, glass and a photosensitive surface are relatively close to each other and cannot meet the requirement of high-pixel packaging, and COB lead bonding packaging has the defects of high manufacturing cost, customized product design, long period, insufficient flexibility, incapability of realizing wafer level high-efficiency packaging and the like.
Disclosure of Invention
Aiming at the problems that the existing CIS wafer level packaging has light glare phenomenon, large signal transmission loss, a Fan-in scheme can not meet multi-pin packaging, glass and a photosensitive surface are close to each other and can not meet the requirement of high-pixel packaging, and COB lead bonding packaging has overhigh manufacturing cost, customized product design, long period, insufficient flexibility, can not realize wafer level high-efficiency packaging and the like, the invention provides a high-pixel CIS wafer level Fan-out type packaging structure according to one aspect of the invention, which comprises the following steps:
a transparent substrate having a chip cavity and a photosensitive area cavity;
a first wiring layer disposed on the upper surface of the transparent substrate and the inner surface of the chip cavity;
the first passivation layer covers the upper surface of the transparent substrate, the inner surface of the chip cavity and the first wiring layer except for the bonding pad;
a die bond structure disposed on a pad of the first routing layer of the die cavity region;
a CIS chip located in the chip cavity and flip-chip bonded to the chip bonding structure;
a second passivation layer covering the back surface of the CIS chip and the top surface of the transparent substrate;
a second routing layer electrically interconnected with the first routing layer; and
and the solder balls are externally connected.
In one embodiment of the present invention, the material of the transparent substrate is glass.
In one embodiment of the invention, the bottom surface of the transparent substrate is provided with an infrared filter film.
In one embodiment of the invention, the inner surface of the chip cavity, the vertical inner surface of the photosensitive area cavity and part of the bottom surface are provided with anti-reflection films.
In an embodiment of the invention, the photosensitive area cavity is located inside the chip cavity, and a depth of the photosensitive area cavity is greater than a depth of the chip cavity.
In one embodiment of the present invention, the material of the first passivation layer is PI.
In an embodiment of the present invention, the second wiring layer implements a fan-out function of the CIS chip IO.
In one embodiment of the invention, the high-pixel CIS wafer-level fan-out package structure further comprises a solder resist layer disposed outside the second wiring layer.
According to another embodiment of the invention, a method for manufacturing a high-pixel CIS wafer level fan-out package structure is provided, which includes:
providing a transparent substrate with a bottom surface infrared filter film;
forming a chip cavity on the upper surface of the transparent substrate;
forming a photosensitive area cavity on the bottom surface of the chip cavity;
forming anti-reflection films on the cavity of the photosensitive area, the inner wall of the cavity of the chip and the upper surface of the transparent substrate;
removing part of the anti-reflection film at the bottom of the photosensitive area cavity to form a light path;
forming a first wiring layer and a first passivation layer on the chip cavity and the anti-reflection film on the front surface of the transparent substrate;
forming a chip welding structure at the position of the first wiring layer bonding pad in the chip cavity area;
bonding a CIS die to the die bond structure; and
and sequentially forming a second passivation layer, a second wiring layer, a solder mask layer and an external solder ball on the back surface of the CIS chip and the upper surface of the transparent substrate.
In another embodiment of the invention, the method further comprises dividing to form single high pixel CIS chip packaging structures.
The invention provides a high-pixel CIS wafer level fan-out type packaging structure and a manufacturing method thereof. The high-pixel CIS wafer level fan-out type packaging structure and the manufacturing method thereof reduce the thickness of light-transmitting glass of a light-sensitive surface and reduce the influence of incident rays; the front glass is kept for protection, so that pollution is reduced; the substrate groove structure is combined with the anti-reflection film, so that the influences of light reflection, diffraction and the like are reduced; the high-efficiency packaging of the wafer level pixel chip is realized; by utilizing the RDL scheme, the signal transmission loss is reduced; Fan-Out (Fan-Out) is adopted to realize multi-pin Fan-Out.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional view of a high pixel CIS wafer-level fan-out package structure 100 formed in accordance with an embodiment of the present invention.
Fig. 2A-2I illustrate cross-sectional views of a process for forming such a high pixel CIS wafer-level fan-out package structure 100, according to one embodiment of the invention.
Fig. 3 illustrates a flow diagram 300 for forming such a high pixel CIS wafer level fan-out package structure 100, according to one embodiment of the invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a high-pixel CIS wafer level fan-out type packaging structure and a manufacturing method thereof. The high-pixel CIS wafer level fan-out type packaging structure and the manufacturing method thereof reduce the thickness of light-transmitting glass of a light-sensitive surface and reduce the influence of incident rays; the front glass is kept for protection, so that pollution is reduced; the substrate groove structure is combined with the anti-reflection film, so that the influences of light reflection, diffraction and the like are reduced; the high-efficiency packaging of the wafer level pixel chip is realized; by utilizing the RDL scheme, the signal transmission loss is reduced; Fan-Out (Fan-Out) is adopted to realize multi-pin Fan-Out.
A high pixel CIS wafer level fan-out package structure according to an embodiment of the invention is described in detail below with reference to fig. 1. Fig. 1 illustrates a cross-sectional view of a high pixel CIS wafer-level fan-out package structure 100 formed in accordance with an embodiment of the present invention. As shown in fig. 1, the high-pixel CIS wafer-level fan-out package structure 100 further includes a transparent substrate 110, a first wiring layer 120, a first passivation layer 130, a chip soldering structure 140, a CIS chip 150, a second passivation layer 160, a second wiring layer 170, a solder resist layer 180, and external solder balls 190.
The transparent substrate 110 further includes a substrate main body 111, an infrared filter 112 disposed on a bottom surface of the substrate main body, a chip cavity 113 disposed on a top surface of the main plate main body 111, a photo-sensing area cavity 114 disposed at a middle position of an area of the chip cavity 113, and an anti-reflection film 115 disposed to cover the top surface of the substrate main body 111, an inner surface of the chip cavity 113, a vertical inner surface of the photo-sensing area cavity 114, and a portion of the bottom surface. The chip cavity 113 is used for accommodating the subsequent embedding of the CIS chip, and the depth of the chip cavity is determined according to the thickness of the CIS chip; the photosensitive region cavity 114 corresponds to a photosensitive region of a subsequent CIS chip, and the depth of the photosensitive region cavity 114 is greater than that of the chip cavity 113, so that the thickness of the photosensitive region of the CIS chip is the smallest in the case of forming a transparent substrate material. In one embodiment of the present invention, the material of the substrate main body 111 of the transparent substrate 110 is glass.
The first wiring layer 120 is disposed on the top surface of the transparent substrate 110 and the anti-reflection film 115 over the chip cavity 113. In the first embodiment of the present invention, the material of the first wiring layer 120 is Cu.
The first passivation layer 130 covers the top surface of the transparent substrate 110 and the anti-reflection film 115 over the chip cavity 113 and the first wiring layer 120 except for the pad, and plays a role in protecting and insulating the first wiring layer 120. In one embodiment of the present invention, the material of the first passivation layer 130 is PI.
The die bond structure 140 is configured to be electrically interconnected to the first wiring layer 120. In one embodiment of the present invention, the die attach structure 140 is a tin bump. In another embodiment of the present invention, the die bonding structure 140 may also be other lead-free solder balls or conductive copper pillars.
The CIS chip 150 is disposed in the chip cavity 113, and is electrically connected to the chip bonding structure 140 by flip chip bonding, thereby achieving electrical interconnection of the CIS chip 150 with the first wiring layer 120.
The second passivation layer 160 covers the back surface of the CIS chip 150 and the corresponding position of the upper surface of the transparent substrate 110. In one embodiment of the present invention, the second passivation layer 160 enables wafer reconfiguration of the CIS chip 150 after bonding, thereby providing support for the subsequent Fan-Out process.
The second wiring layer 170 is disposed to electrically interconnect with the first wiring layer 120, so as to further electrically interconnect with the CIS chip 150, wherein the second wiring layer 170 implements a fan-out function of the IO of the CIS chip 150, so as to meet the packaging requirement of more pins. In one embodiment of the present invention, the second wiring layer 170 may have one or more layers, which may be determined according to design requirements.
The solder resist layer 180 is disposed on the outer surfaces of the second wiring layer 170 and the second passivation layer 160 on the outermost layer, and plays a role of protecting the non-exposed region of the second wiring layer 170. In one embodiment of the present invention, solder mask 180 is a green oil solder mask.
The process of forming the high pixel CIS wafer level fan-out package structure 100 is described in detail below with reference to fig. 2A-2I and fig. 3. FIGS. 2A-2I illustrate cross-sectional views of a process for forming such a high pixel CIS wafer level fan-out package structure 100, according to one embodiment of the present invention; fig. 3 illustrates a flow diagram 300 for forming such a high pixel CIS wafer level fan-out package structure 100, according to one embodiment of the invention.
First, in step 310, as shown in fig. 2A, a transparent substrate 210 is provided, and the bottom surface of the substrate main body 211 of the transparent substrate 210 has an infrared filter 212. In one embodiment of the invention, the substrate main body 211 is glass, and the infrared filter 212 can be formed by a thin film deposition process such as sputtering, evaporation, etc. on the bottom surface of the substrate main body 211.
Next, at step 320, as shown in fig. 2B, a CIS chip cavity 213 is formed. The CIS chip cavity 213 corresponds to information on the size, pads, and the like of the CIS chip. In one embodiment of the present invention, the CIS chip cavity 213 is obtained by etching a specific region of the top surface of the substrate body 211 of the transparent substrate 210.
Then, at step 330, the photosensitive area cavity 214 is formed, as shown in fig. 2C. The photosensitive area cavity 214 corresponds to the photosensitive area of the CIS chip and is slightly larger than the photosensitive area.
Next, in step 340, as shown in fig. 2D, an anti-reflection film 215 is formed on the photosensitive region cavity 214, the inner wall of the CIS chip cavity 213, and the top surface of the transparent substrate 210 to prevent the peripheral glass from affecting light. In one embodiment of the present invention, the anti-reflection film 215 may be deposited on the top surface of the transparent substrate 210 on which the photosensitive region cavities 214 and the CIS chip cavities 213 have been formed.
Then, at step 350, as shown in FIG. 2E, the anti-reflection film 215 at the bottom of the photosensitive area cavity 214 is removed to form the light path 216. The light path 216 corresponds to a photosensitive region of the CIS chip.
Next, at step 360, as shown in fig. 2F, a first wiring layer 220 and a first passivation layer 230 are formed on the CIS chip cavity 213 and the anti-reflection film 215 on the front surface of the transparent substrate 210. In one embodiment of the present invention, first wiring layer 220 is formed by patterned plating, being a copper wiring layer; the first passivation layer 230 is formed by spin coating PI over the first wiring 220 and then cured, and the first passivation layer 230 plays a role of insulation and protection of the first wiring layer 220. Wherein first passivation layer 230 has a window over the pad location of first routing layer 220.
Then, at step 370, as shown in fig. 2G, a die bonding structure 240 is formed at the pad position of the first wiring layer 220 in the CIS chip cavity region. In one embodiment of the present invention, the die attach structure 240 is a lead-free solder ball formed by electroplating. In yet another embodiment of the present invention, the die bond structure 240 is a conductive copper pillar.
Next, at step 380, the CIS chip 250 is soldered to the chip solder structure 240, as shown in fig. 2H. When bonding, the chip photosensitive region 252 of the CIS chip 250 faces downward, and the chip pad 251 is bonded to the chip bonding structure 240. After bonding, CIS die 250 is positioned within CIS die cavity 213 and die photosensitive region 252 is positioned over light path 216.
Finally, in step 390, as shown in fig. 2I, a second passivation layer 260, a second wiring layer 270, a solder resist layer 280 and external solder balls 290 are sequentially formed on the back surface of the CIS chip 250 and the surface of the transparent substrate 210. The second passivation layer 260 covers the back surface of the CIS chip 250 and the corresponding position of the upper surface of the transparent substrate 210. In one embodiment of the invention, the second passivation layer 260 enables wafer reconfiguration of the CIS chip 250 after bonding, thereby providing support for the subsequent Fan-Out process. The second wiring layer 270 is configured to electrically interconnect with the first wiring layer 220, so as to further electrically interconnect with the CIS chip 250, wherein the second wiring layer 270 implements a fan-out function of the IO of the CIS chip 250, so as to meet the packaging requirement of more pins. In one embodiment of the present invention, the second wiring layer 270 may have one or more layers, which may be determined according to design requirements. The solder resist layer 280 is disposed on the outer surfaces of the second wiring layer 270 and the second passivation layer 260 of the outermost layer, and plays a role of protecting the non-exposed region of the second wiring layer 270. In one embodiment of the present invention, solder mask 280 is a green oil solder mask. External solder balls 290 are disposed on the second wiring layer 270 at the external pads, on top of the entire package structure, to serve as electrical and/or signal interconnections to external circuitry. The external solder balls 290 may be formed by a plating reflow or ball-mounting process.
Optionally, the method may further include dividing the transparent substrate 210 to form a single high-pixel CIS chip package structure.
Based on the high-pixel CIS wafer level fan-out type packaging structure and the manufacturing method thereof, provided by the invention, the wafer is cut, the chip cavity and the photosensitive area cavity are manufactured on the transparent substrate, then the wiring layer and the passivation layer are formed, then the cut single CIS chip is inversely welded to the chip cavity of the transparent substrate, the photosensitive surface protection is realized, and finally the IO pin conduction and fan-out of the CIS chip are realized. The high-pixel CIS wafer level fan-out type packaging structure and the manufacturing method thereof reduce the thickness of light-transmitting glass of a light-sensitive surface and reduce the influence of incident rays; the front glass is kept for protection, so that pollution is reduced; the substrate groove structure is combined with the anti-reflection film, so that the influences of light reflection, diffraction and the like are reduced; the high-efficiency packaging of the wafer level pixel chip is realized; by utilizing the RDL scheme, the signal transmission loss is reduced; Fan-Out with multiple pins is achieved using Fan-Out.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A high pixel CIS wafer level fan-out package structure comprising:
a transparent substrate having a chip cavity and a photosensitive area cavity;
a first wiring layer disposed on the upper surface of the transparent substrate and the inner surface of the chip cavity;
the first passivation layer covers the upper surface of the transparent substrate, the inner surface of the chip cavity and the first wiring layer except for the bonding pad;
a die bond structure disposed on a pad of the first routing layer of the die cavity region;
the CIS chip is positioned in the chip cavity and is in flip-chip bonding to the chip bonding structure, wherein the photosensitive area cavity corresponds to a photosensitive area of the CIS chip, and the depth of the photosensitive area cavity is greater than that of the chip cavity, so that the thickness of the transparent substrate at the photosensitive area of the CIS chip is minimum;
a second passivation layer covering the back surface of the CIS chip and the top surface of the transparent substrate;
a second routing layer electrically interconnected with the first routing layer; and
and the solder balls are externally connected.
2. The high-pixel CIS wafer level fan-out package structure of claim 1, wherein the material of the transparent substrate is glass.
3. The high-pixel CIS wafer level fan-out package structure of claim 1, wherein the bottom surface of the transparent substrate is provided with an infrared filter.
4. The high-pixel CIS wafer-level fan-out package structure of claim 1, wherein the chip cavity inner surface, the photosensitive region cavity vertical inner surface and a portion of the bottom surface are provided with anti-reflection films.
5. The high pixel CIS wafer level fan-out package structure of claim 1, wherein the photo-sensing area cavity is located inside the die cavity.
6. The high-pixel CIS wafer level fan-out package structure of claim 1, wherein the material of the first passivation layer is PI.
7. The high-pixel CIS wafer level fan-out package structure of claim 1, wherein the second wiring layer implements a fan-out function of the CIS chip IO.
8. The high pixel CIS wafer level fan-out package structure of claim 1, further comprising a solder resist layer disposed outside the second routing layer.
9. A manufacturing method of a high-pixel CIS wafer level fan-out type packaging structure comprises the following steps:
providing a transparent substrate with a bottom surface infrared filter film;
forming a chip cavity on the upper surface of the transparent substrate;
forming a photosensitive area cavity on the bottom surface of the chip cavity;
forming anti-reflection films on the cavity of the photosensitive area, the inner wall of the cavity of the chip and the upper surface of the transparent substrate;
removing part of the anti-reflection film at the bottom of the photosensitive area cavity to form a light path;
forming a first wiring layer and a first passivation layer on the chip cavity and the anti-reflection film on the front surface of the transparent substrate;
forming a chip welding structure at the position of the first wiring layer bonding pad in the chip cavity area;
welding the CIS chip to the chip welding structure, wherein the photosensitive area cavity corresponds to a photosensitive area of the CIS chip, and the depth of the photosensitive area cavity is greater than that of the chip cavity, so that the thickness of the transparent substrate at the photosensitive area of the CIS chip is minimum; and
and sequentially forming a second passivation layer, a second wiring layer, a solder mask layer and an external solder ball on the back surface of the CIS chip and the upper surface of the transparent substrate.
10. The method of claim 9, further comprising singulating to form a single high pixel CIS chip package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811548617.1A CN109638031B (en) | 2018-12-18 | 2018-12-18 | High-pixel CIS wafer-level fan-out type packaging structure and manufacturing method thereof |
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