CN109638031A - A kind of high pixel CIS wafer scale fan-out package structure and its manufacturing method - Google Patents
A kind of high pixel CIS wafer scale fan-out package structure and its manufacturing method Download PDFInfo
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- CN109638031A CN109638031A CN201811548617.1A CN201811548617A CN109638031A CN 109638031 A CN109638031 A CN 109638031A CN 201811548617 A CN201811548617 A CN 201811548617A CN 109638031 A CN109638031 A CN 109638031A
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000002161 passivation Methods 0.000 claims abstract description 35
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000000576 coating method Methods 0.000 claims description 16
- 239000011521 glass Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000001914 filtration Methods 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 4
- 230000011218 segmentation Effects 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 description 17
- 239000010408 film Substances 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 6
- 230000008054 signal transmission Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
- H01L27/14629—Reflectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
Abstract
The invention discloses a kind of high pixel CIS wafer scale fan-out package structures, comprising: transparent substrate, the transparent substrate have chip cavity and photosensitive region cavity；First wiring layer, first wiring layer are arranged in the transparent substrate upper surface and the chip cavity inner surface；First passivation layer, first passivation layer cover the transparent substrate upper surface, the chip cavity inner surface and the first wiring layer in addition to pad；Chip welded structure, the chip welded structure are arranged on the pad of first wiring layer of the chip cavity area；CIS chip, the CIS chip is located in the chip cavity, and upside-down mounting is welded to the chip welded structure；Second passivation layer, second passivation layer cover the CIS chip back and the transparent substrate top surface；Second wiring layer, second wiring layer and first wiring layer are electrically interconnected；And external soldered ball.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation more particularly to a kind of high pixel CIS wafer scale fan-out package knots
Structure and its manufacturing method.
Background technique
The market application of CIS (CMOS Image Sensor, cmos image sensor) is more and more wider, as technology develops,
The pixel and sensitivity of CIS is higher and higher.The encapsulation of CIS has significant impact to the performance, reliability and service life of product,
In combination with the cost of encapsulation, wafer-level packaging is increasingly becoming the mainstream of CIS encapsulation.
There are mainly two types of traditional CIS encapsulation.1) CIS Wafer level packaging, structure are front bonding glass, the back side
Realize that pin is drawn in the hole TSV.There are the following problems for this kind of technology: the problems such as heavy sheet glass on encapsulating structure surface is due to refractive index,
It is easy that incident ray is generated light and dazzled etc. to influence；Back side TSV technology is larger to signal transmission attenuation；As pixel increases, individually
The data processing amount of chip is also increasing, and the I/O pin quantity of chip is also increasing, existing Fan-in (fan-in) scheme, is limited
In the size of chip, it can not achieve more pins and draw；High pixel CIS encapsulation simultaneously, it is desirable that increase watch crystal to photosurface away from
From.Existing wafer-level packaging distance is generally 30/40um, is not able to satisfy high pixel encapsulation and requires.2) COB wire bond package
Technology.This technology there are the problem of it is as follows: dirt control is extremely difficult, needs the proper clean room grade of superelevation, and manufacture maintains cost
It is high；Product design customizes, the period is long, flexibility ratio is inadequate；It cannot achieve the high efficiency encapsulation of wafer scale.
Dazzle that phenomenon, signal transmission attenuation be big, Fan-in scheme can not expire for light existing for existing CIS wafer-level packaging
The more pin packages of foot, glass and photosurface, which are closer, is unable to satisfy high pixel encapsulation requirement and COB wire bond package system
The problems such as causing excessively high, product design customization, period length, a flexibility ratio not enough and cannot achieve the encapsulation of wafer scale high efficiency,
The invention proposes a kind of novel high pixel CIS wafer scale fan-out package structure and its manufacturing method, at least part of gram
The above problem is taken.
Summary of the invention
Dazzle that phenomenon, signal transmission attenuation be big, Fan-in scheme can not expire for light existing for existing CIS wafer-level packaging
The more pin packages of foot, glass and photosurface, which are closer, is unable to satisfy high pixel encapsulation requirement and COB wire bond package system
The problems such as causing excessively high, product design customization, period length, a flexibility ratio not enough and cannot achieve the encapsulation of wafer scale high efficiency,
According to an aspect of the present invention, a kind of high pixel CIS wafer scale fan-out package structure is provided, comprising:
Transparent substrate, the transparent substrate have chip cavity and photosensitive region cavity；
Table is arranged in the transparent substrate upper surface and the chip cavity in first wiring layer, first wiring layer
Face；
First passivation layer, first passivation layer cover the transparent substrate upper surface, the chip cavity inner surface with
And the first wiring layer in addition to pad；
First wiring layer of the chip cavity area is arranged in chip welded structure, the chip welded structure
On pad；
CIS chip, the CIS chip is located in the chip cavity, and upside-down mounting is welded to the chip welded structure；
Second passivation layer, second passivation layer cover the CIS chip back and the transparent substrate top surface；
Second wiring layer, second wiring layer and first wiring layer are electrically interconnected；And
External soldered ball.
In one embodiment of the invention, the material of the transparent substrate is glass.
In one embodiment of the invention, the bottom surface of the transparent substrate is provided with infrared filtering film.
In one embodiment of the invention, the chip cavity inner surface, the photosensitive region cavity vertical inside surface
Portion bottom surface is provided with T-coating.
In one embodiment of the invention, the photosensitive region cavity is located at the chip cavity inside, and the sense
The depth of light area vacuity is greater than the depth of the chip cavity.
In one embodiment of the invention, the material of first passivation layer is PI.
In one embodiment of the invention, what second wiring layer realized the CIS chip I/O is fanned out to function.
In one embodiment of the invention, high pixel CIS wafer scale fan-out package structure further includes being arranged described
Solder mask outside second wiring layer.
According to another embodiment of the invention, a kind of manufacture of high pixel CIS wafer scale fan-out package structure is provided
Method, comprising:
The transparent substrate for having bottom surface infrared filtering film is provided；
Chip cavity is formed in the transparent substrate upper surface；
Photosensitive region cavity is formed in the chip cavity floor；
Reflection-proof is formed in the photosensitive region cavity, the inner wall of the chip cavity and the transparent substrate upper surface
Film；
The T-coating for removing the part photosensitive region cavity bottom forms light-path；
The first wiring layer and first are formed on the chip cavity and the positive T-coating of the transparent substrate
Passivation layer；
Chip welded structure is formed in the first wiring layer pad locations of the chip cavity area；
CIS chip is soldered to the chip welded structure；And
The upper surface of the CIS chip back and the transparent substrate sequentially form the second passivation layer, the second wiring layer,
Solder mask and external soldered ball.
In another embodiment of the present invention, this method further includes that segmentation forms single high pixel CIS chip package knot
Structure.
The present invention provides a kind of high pixel CIS wafer scale fan-out package structure and its manufacturing method, by cutting wafer
It cuts, by carrying out chip cavity and the production of photosensitive region cavity to transparent substrate, next re-forms wiring layer and passivation layer, so
Single CIS flip-chip after cutting is welded to the chip cavity of transparent substrate afterwards, photosurface protection is realized, finally realizes again
The I/O pin of CIS chip is connected and is fanned out to.Based on this kind high pixel CIS wafer scale fan-out package structure of the invention and its system
The method of making reduces photosurface transparent glass thickness, reduces the influence of incident ray；Retain face glass protection, reduces dirt
Dye；Using substrate recess structure combination T-coating, reduce the influence such as light reflection, diffraction；Realize the high pixel core of wafer scale
The encapsulation of piece high efficiency；Using RDL scheme, reduce signal transmission attenuation；It (is fanned out to) using Fan-Out, realizes that more pins are fanned out to.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Fig. 1 shows a kind of high pixel CIS wafer scale fan-out package structure formed according to one embodiment of present invention
100 diagrammatic cross-section.
Fig. 2A to Fig. 2 I is shown forms this kind high pixel CIS wafer scale fan-out package according to one embodiment of present invention
The process diagrammatic cross-section of structure 100.
Fig. 3 is shown forms this kind high pixel CIS wafer scale fan-out package knot according to one embodiment of present invention
The flow chart 300 of structure 100.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention is described processing step with particular order, however this is only
Facilitate and distinguish each step, and is not the sequencing for limiting each step, it in different embodiments of the invention, can be according to work
Skill is adjusted to adjust the sequencing of each step.
The present invention provides a kind of high pixel CIS wafer scale fan-out package structure and its manufacturing method, by cutting wafer
It cuts, by carrying out chip cavity and the production of photosensitive region cavity to transparent substrate, next re-forms wiring layer and passivation layer, so
Single CIS flip-chip after cutting is welded to the chip cavity of transparent substrate afterwards, photosurface protection is realized, finally realizes again
The I/O pin of CIS chip is connected and is fanned out to.Based on this kind high pixel CIS wafer scale fan-out package structure of the invention and its system
The method of making reduces photosurface transparent glass thickness, reduces the influence of incident ray；Retain face glass protection, reduces dirt
Dye；Using substrate recess structure combination T-coating, reduce the influence such as light reflection, diffraction；Realize the high pixel core of wafer scale
The encapsulation of piece high efficiency；Using RDL scheme, reduce signal transmission attenuation；It (is fanned out to) using Fan-Out, realizes that more pins are fanned out to.
A kind of high pixel CIS wafer scale according to an embodiment of the invention is discussed in detail below with reference to Fig. 1 to be fanned out to
Type encapsulating structure.Fig. 1 shows a kind of high pixel CIS wafer scale fan-out package knot formed according to one embodiment of present invention
The diagrammatic cross-section of structure 100.As shown in Figure 1, the high pixel CIS wafer scale fan-out package structure 100 further comprises transparent
Substrate 110, the first wiring layer 120, the first passivation layer 130, chip welded structure 140, CIS chip 150, the second passivation layer 160,
Second wiring layer 170, solder mask 180 and external soldered ball 190.
Transparent substrate 110 further comprises base main body 111, and the infrared filtering film 112 of base main body bottom surface is arranged in, if
The chip cavity 113 in 111 top surface of mainboard main body is set, the photosensitive region cavity in 113 region middle position of chip cavity is set
114, and setting is in covering 111 top surface of base main body, 113 inner surface of chip cavity, 114 vertical inside surface of photosensitive region cavity
With the T-coating 115 of portion bottom surface.Wherein subsequent CIS is chip buried, and depth is according to CIS for accommodating for chip cavity 113
The thickness of chip determines；Photosensitive region cavity 114 is corresponding with the photosensitive region of subsequent CIS chip, photosensitive region cavity 114
Depth is greater than chip cavity 113, minimum in CIS chip photosensitive region thickness from transparent substrate material is formed.Of the invention one
In a embodiment, the material of the base main body 111 of transparent substrate 110 is glass.
First wiring layer 120 is arranged on the T-coating 115 on the top surface and chip cavity 113 of transparent substrate 110.
In one embodiment of the invention, the material of the first wiring layer 120 is Cu.
First passivation layer 130 cover transparent substrate 110 top surface and T-coating 115 on chip cavity 113 and
The first wiring layer 120 in addition to pad, plays the protection to the first wiring layer 120 and insulating effect.At of the invention one
In embodiment, the material of the first passivation layer 130 is PI.
Chip welded structure 140 is electrically interconnected for being arranged to the first wiring layer 120.In one embodiment of the present of invention
In, chip welded structure 140 is tin salient point.In another embodiment of the present invention, chip welded structure 140 can also be other
Lead-free solder ball or conduction copper column.
CIS chip 150 is arranged in chip cavity 113, is electrically connected to chip welded structure 140 by flip chip bonding, thus
Realize the electrical interconnection of CIS chip 150 and the first wiring layer 120.
Second passivation layer 160 covers the corresponding position of 150 back side of CIS chip and 110 upper surface of transparent substrate.In the present invention
One embodiment in, the second passivation layer 160 realize CIS chip 150 weld after wafer reconstruct, thus be subsequent Fan-
Out technique provides support.
Second wiring layer 170 is arranged to be electrically interconnected with the first wiring layer 120, to further realize and CIS chip 150
It is electrically interconnected, wherein the second wiring layer 170 realizes that the IO's of CIS chip 150 is fanned out to function, to be able to satisfy the encapsulation of more pins
It is required that.In one embodiment of the invention, the second wiring layer 170 can have one or more layers, specifically can be according to design need
It determines.
The outer surface of outermost second wiring layer 170 and the second passivation layer 160 is arranged in solder mask 180, plays to
The protective effect of the non-exposed region of two wiring layers 170.In one embodiment of the invention, solder mask 180 is green oil welding resistance
Layer.
The external pad locations of the second wiring layer 170 are arranged in external soldered ball 190, positioned at the top of entire encapsulating structure,
Play the role of the electricity and/or signal interconnection with external circuit.External soldered ball 190 can pass through plating Reflow Soldering or plant ball technique
It is formed.
It is described in detail to form this kind high pixel CIS wafer scale fan-out package below with reference to Fig. 2A to Fig. 2 I and Fig. 3
The process of structure 100.Fig. 2A to Fig. 2 I, which is shown, to be formed this kind high pixel CIS wafer scale according to one embodiment of present invention and is fanned out to
The process diagrammatic cross-section of type encapsulating structure 100；Fig. 3 is shown forms this kind high pixel according to one embodiment of present invention
The flow chart 300 of CIS wafer scale fan-out package structure 100.
Firstly, as shown in Figure 2 A, providing transparent substrate 210, the bottom of 210 base main body 211 of transparent substrate in step 310
Face has infrared filtering film 212.In one embodiment of the invention, base main body 211 is glass, and infrared filtering film 212 can
By being formed in thin film deposition processes such as the sputtering of the bottom surface of base main body 211, vapor depositions.
Next, as shown in Figure 2 B, forming CIS chip cavity 213 in step 320.CIS chip cavity 213 and CIS core
The information such as size, the pad of piece are corresponding.In one embodiment of the invention, CIS chip cavity 213 is by transparent substrate
The top surface specific region of 210 base main bodies 211 performs etching acquisition.
Then, in step 330, as shown in Figure 2 C, photosensitive region cavity 214 is formed.Photosensitive region cavity 214 and and CIS
The photosensitive zone position of chip is corresponding, and size is slightly larger than photosensitive area.
Next, in step 340, as shown in Figure 2 D, photosensitive region cavity 214, CIS chip cavity 213 inner wall with
And transparent substrate 210 top surface formed T-coating 215, avoid around glass on light influence.In an implementation of the invention
In example, T-coating 215 can be on the top for the transparent substrate 210 for having formed photosensitive region cavity 214, CIS chip cavity 213
Face deposits to be formed.
Then, in step 350, as shown in Figure 2 E, the T-coating 215 of 214 bottom of photosensitive region cavity is removed, forms light
Access 216.Light-path 216 is corresponding with the photosensitive area of CIS chip.
Next, in step 360, as shown in Figure 2 F, in CIS chip cavity 213 and the positive reflection-proof of transparent substrate 210
The first wiring layer 220 and the first passivation layer 230 are formed on film 215.In one embodiment of the invention, the first wiring layer 220
It to be formed by being graphically electroplated, be copper wiring layer；First passivation layer 230 above the first wiring 220 after spin coating PI by solidifying
It is formed, the first passivation layer 230 plays the insulation and protective effect to the first wiring layer 220.Wherein, in the first wiring layer 220
Above pad locations, the first passivation layer 230 has window.
Then, in step 370, as shown in Figure 2 G, in the 220 pad locations shape of the first wiring layer of CIS chip cavity area
At chip welded structure 240.In one embodiment of the invention, chip welded structure 240 is by the unleaded of plating formation
Soldered ball.In another embodiment of the present invention, chip welded structure 240 is conduction copper column.
Next, as illustrated in figure 2h, CIS chip 250 is soldered to chip welded structure 240 in step 380.When welding,
Downward, chip bonding pad 251 is bonded the chip photosensitive region 252 of CIS chip 250 with chip welded structure 240.After welding, CIS core
Piece 250 is located in CIS chip cavity 213, and chip photosensitive region 252 is located at 216 top of light-path.
Finally, as shown in figure 2i, being sequentially formed on the surface at 250 back side of CIS chip and transparent substrate 210 in step 390
Second passivation layer 260, the second wiring layer 270, solder mask 280 and external soldered ball 290.Second passivation layer 260 covers CIS chip
The corresponding position of 210 upper surface of 250 back sides and transparent substrate.In one embodiment of the invention, the second passivation layer 260 is realized
Wafer after CIS chip 250 welds reconstructs, to provide support for subsequent Fan-Out technique.The setting of second wiring layer 270
It is electrically interconnected at the first wiring layer 220, so that the electrical interconnection with CIS chip 250 is further realized, wherein the second wiring layer 270
Realize that the IO's of CIS chip 250 is fanned out to function, to be able to satisfy the encapsulation requirement of more pins.In an implementation of the invention
In example, the second wiring layer 270 can have one or more layers, can specifically determine according to the design needs.Solder mask 280 is arranged most
Second wiring layer 270 of outer layer and the outer surface of the second passivation layer 260, are played to the non-exposed region of the second wiring layer 270
Protective effect.In one embodiment of the invention, solder mask 280 is green oil solder mask.External soldered ball 290 is arranged in the second cloth
The external pad locations of line layer 270 play and the electricity of external circuit and/or signal interconnection work positioned at the top of entire encapsulating structure
With.External soldered ball 290 can be formed by plating Reflow Soldering or plant ball technique.
Optionally, it can also include segmentation transparent substrate 210, form single high pixel CIS chip-packaging structure.
Based on this kind provided by the invention high pixel CIS wafer scale fan-out package structure and its manufacturing method, pass through by
Wafer cutting is made by carrying out chip cavity and photosensitive region cavity to transparent substrate, next re-forms wiring layer and blunt
Change layer, then single CIS flip-chip after cutting is welded to the chip cavity of transparent substrate, realizes photosurface protection, finally
The I/O pin conducting of CIS chip is realized again and is fanned out to.Based on this kind high pixel CIS wafer scale fan-out package structure of the invention
And its manufacturing method reduces photosurface transparent glass thickness, reduces the influence of incident ray；Retain face glass protection, subtracts
Pollution is lacked；Using substrate recess structure combination T-coating, reduce the influence such as light reflection, diffraction；Realize that wafer scale is high
The encapsulation of pixel chip high efficiency；Using RDL scheme, reduce signal transmission attenuation；Using Fan-Out, realize that more pins are fanned out to.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (10)
1. a kind of high pixel CIS wafer scale fan-out package structure, comprising:
Transparent substrate, the transparent substrate have chip cavity and photosensitive region cavity；
First wiring layer, first wiring layer are arranged in the transparent substrate upper surface and the chip cavity inner surface；
First passivation layer, first passivation layer cover the transparent substrate upper surface, the chip cavity inner surface and remove
The first wiring layer except pad；
The pad of first wiring layer of the chip cavity area is arranged in chip welded structure, the chip welded structure
On；
CIS chip, the CIS chip is located in the chip cavity, and upside-down mounting is welded to the chip welded structure；
Second passivation layer, second passivation layer cover the CIS chip back and the transparent substrate top surface；
Second wiring layer, second wiring layer and first wiring layer are electrically interconnected；And
External soldered ball.
2. a kind of high pixel CIS wafer scale fan-out package structure as described in claim 1, which is characterized in that described transparent
The material of substrate is glass.
3. a kind of high pixel CIS wafer scale fan-out package structure as described in claim 1, which is characterized in that described transparent
The bottom surface of substrate is provided with infrared filtering film.
4. a kind of high pixel CIS wafer scale fan-out package structure as described in claim 1, which is characterized in that the chip
Cavity inner surface, the photosensitive region cavity vertical inside surface and portion bottom surface are provided with T-coating.
5. a kind of high pixel CIS wafer scale fan-out package structure as described in claim 1, which is characterized in that described photosensitive
Area vacuity is located at the chip cavity inside, and the depth of the photosensitive region cavity is greater than the depth of the chip cavity.
6. a kind of high pixel CIS wafer scale fan-out package structure as described in claim 1, which is characterized in that described first
The material of passivation layer is PI.
7. a kind of high pixel CIS wafer scale fan-out package structure as described in claim 1, which is characterized in that described second
What wiring layer realized the CIS chip I/O is fanned out to function.
8. a kind of high pixel CIS wafer scale fan-out package structure as described in claim 1, which is characterized in that further include setting
Set the solder mask outside second wiring layer.
9. a kind of manufacturing method of high pixel CIS wafer scale fan-out package structure, comprising:
The transparent substrate for having bottom surface infrared filtering film is provided；
Chip cavity is formed in the transparent substrate upper surface；
Photosensitive region cavity is formed in the chip cavity floor；
T-coating is formed in the photosensitive region cavity, the inner wall of the chip cavity and the transparent substrate upper surface；
The T-coating for removing the part photosensitive region cavity bottom forms light-path；
The first wiring layer and the first passivation are formed on the chip cavity and the positive T-coating of the transparent substrate
Layer；
Chip welded structure is formed in the first wiring layer pad locations of the chip cavity area；
CIS chip is soldered to the chip welded structure；And
The second passivation layer, the second wiring layer, welding resistance are sequentially formed in the upper surface of the CIS chip back and the transparent substrate
Layer and external soldered ball.
10. method as claimed in claim 9 further includes that segmentation forms single high pixel CIS chip-packaging structure.
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