CN101383335B - Semiconductor package substrate and fabrication method thereof - Google Patents
Semiconductor package substrate and fabrication method thereof Download PDFInfo
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- CN101383335B CN101383335B CN2007101482552A CN200710148255A CN101383335B CN 101383335 B CN101383335 B CN 101383335B CN 2007101482552 A CN2007101482552 A CN 2007101482552A CN 200710148255 A CN200710148255 A CN 200710148255A CN 101383335 B CN101383335 B CN 101383335B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Wire Bonding (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention relates to a semiconductor packaging substrate and a fabricating method thereof. The invention is characterized in that electric connection pads on the surface of a circuit board provided with a wire bonding area and a lug area synchronously form a nickel/palladium/metal layer, so as to reduce the flow of process and the waste of time. The effect for enhancing the binding force between the substrate and the chip exists in the nickel/palladium/metal layer.
Description
Technical field
The present invention relates to a kind of conductor package substrate and preparation method thereof, refer to that especially a kind of being applicable to simultaneously forms conductor package substrate of one nickel/palladium/gold layer and preparation method thereof in routing zone and projection zone.
Background technology
Because demands such as the compact day by day and multifunction of electronic product drive the integrated circuit (IC) chip Development of Packaging Technology simultaneously, and then impel Chip Packaging towards multiwayization, slimming.
Be the densification that adapts to compact trend and pursue encapsulation, present spherical array package (Ball Grid Array), chip size type encapsulate (Chip Scale Package) and cover crystalline substance (Flip Chip) technology has become the encapsulation mainstream technology.Therefore, for demands such as small size, the raising of I/O (I/O) pin, wiring densification, low noise, product reliability even costs of manufacture, become the important topic that base plate for packaging is made.
The manufacturing process of base plate for packaging generally needs to form fine and close circuit pattern in substrate surface, with the usefulness as transmission electronic signal or power supply.Industry generally uses copper wires as wiring at present, so the I/O contact place of wiring need be coated with nickel/gold layer, it to keep the electrical quality at I/O contact place, also can promote the steadiness when beating gold thread between base plate for packaging and the chip except can preventing the copper conductor oxidation.
The conventional package substrates processing procedure is prior to being coated with behind the anti-welding material contact that manufacturing is connected with chip in routing zone and processing procedure that the projection zone separates on the substrate that forms line pattern.
In general traditional processing procedure, please refer to Fig. 1, it is the cutaway view that tradition is made the method for conductor package substrate.Shown in Figure 1A, provide a surface to have a plurality of electric connection pad 11a, 11b, the circuit board 10 of 11c, and a patterned anti-soldering layer 12 (solder mask) is with protective circuit plate 10.This circuit board 10 has routing zone 10a and projection zone 10b.Then, shown in Figure 1B, in the 10a of routing zone, form a nickel/gold layer 13 (form nickel earlier, form gold again) in electric connection pad 11a surface at first earlier.At last, shown in Fig. 1 C, the electric connection pad 11b surface in the 10b of projection zone forms a protective layer 14 earlier for another example; for example can be the metal of tin or nickel/gold; via the mode of mould printing, form a solder projection 15 at last, and obtain the conventional semiconductor packages substrate again.
In existing processing procedure, as if the Jin Taihou that forms, the phenomenon that then has ion migration (migration) causes surface engagement not good to solder projection in the electric connection pad projection zone.Yet Nei Ruojin is thin excessively in the routing zone, and its metal wire joint capacity can reduce, and nickel then has the small part metal migration to gold, and the conjugation that can cause routing to engage has problem.In existing processing procedure, form the tin layer again, still have the problem of ion migration, can cause surface combination power not good, make the waste of cost of manufacture, simultaneously also waste time of making.
Summary of the invention
In view of this, the objective of the invention is to overcome the deficiencies in the prior art and defective, a kind of conductor package substrate and preparation method thereof is proposed, be applicable to simultaneously and form one nickel/palladium/gold layer in routing zone and projection zone, not only in the routing zone, can keep with the conjugation of routing and projection zone in can keep conjugation with solder projection, and can reduce the cost and the waste of time of making.And then can keep the electrical quality at I/O contact place.
For reaching above-mentioned purpose, the invention provides a kind of conductor package substrate, this conductor package substrate comprises: a circuit board, this circuit board both side surface has a plurality of electric connection pads, and the part electric connection pad of a side surface is as wire pad and bump pads; One patterned anti-soldering layer, it is disposed at this circuit board surface, this circuit board wherein patterned anti-soldering layer on a surface has a plurality of first openings and a plurality of second opening, described a plurality of first opening manifests this circuit board surface around this wire pad and this wire pad, described a plurality of second opening appears this bump pads, the surperficial patterned anti-soldering layer of another of this circuit board has a plurality of the 3rd openings, to manifest this electric connection pad; One metal coupling, it disposes corresponding to this bump pads surface; One nickel/palladium/gold layer, it is disposed at this metal lug surface and this wire pad surface; And a conductive layer, it is disposed between this metal coupling and this bump pads, between this nickel/palladium/gold layer and this wire pad and between this nickel/palladium/gold layer and this electric connection pad.
At this, the zone at wire pad place can form a routing zone, and the zone at bump pads place then can be used as a projection zone.
In the conductor package substrate of the invention described above, circuit board opposite side surface also comprises the electric connection pad that has this patterned anti-soldering layer and manifest part, and this electric connection pad surface that manifests part also is formed with nickel/palladium/gold layer.
In the conductor package substrate of the present invention, also comprise forming the semiconductor package module, and have at least two chips.Wherein, at least one chip electrically connects with this wire pad via a metal wire, and another chip electrically connects with this bump pads via solder projection at least.
According to the conductor package substrate of the invention described above, for example can make by step following but that be not limited thereto.
Therefore the present invention, provides a kind of manufacture method of conductor package substrate in order to have the contact in projection zone and routing zone simultaneously, and its step comprises: at first, provide a circuit board, have a plurality of electric connection pads on its surface; Then, form a patterned anti-soldering layer in this circuit board surface, and the wherein patterned anti-soldering layer on a surface of circuit board has a plurality of first openings and a plurality of second opening, and a plurality of first openings can manifest electric connection pad and partial circuit plate outer surface, with as a routing zone, second opening then can manifest electric connection pad, with as a projection zone, another surperficial patterned anti-soldering layer at circuit board then forms a plurality of the 3rd openings, to manifest electric connection pad; Then, on circuit board surface, form a conductive layer (seed layer) with welding resisting layer; Form a patterning resistance layer in the circuit board surface with this conductive layer again, and this resistance layer has a plurality of the 4th openings, described the 4th opening is corresponding to second opening; Moreover, in the 4th opening, form a metal coupling respectively; Then, remove resistance layer and be covered in welding resisting layer and the conductive layer of circuit board surface again; At last, form one nickel/palladium/gold layer in metal coupling and electric connection pad surface.
After the manufacture method except the conductor package substrate of finishing the invention described above, also can comprise and form the semiconductor package module, and have at least two chips, the routing zone in conductor package substrate of the present invention can electrically connect with at least one chip via a metal wire.Then can be in the projection zone via a solder projection and another chip electric connection at least.
In conductor package substrate of the invention described above and preparation method thereof, wherein use the main cause of palladium to be, when simple use nickel/gold, because nickel is not complete pure nickel, and the foreign metal that can have minority, the foreign metal of this minority can cause the phenomenon of ion migration.Therefore, use palladium can block the ion transport phenomena that foreign metal produces, can be simultaneously on the electric connection pad in the metal coupling in projection zone and routing zone, form this nickel/palladium/gold layer, with direct Connection Step as successive process.Be that the projection zone can form solder projection again, the routing zone then can directly be connected with chip via metal wire.And the mode that forms this nickel/palladium/gold layer preferably can be one of sputter, evaporation, electroless-plating and chemical deposition.Therefore, nickel/palladium/gold layer is except between the electric connection pad that helps the routing zone and metal wire and the electric connection between the solder projection in projection zone, also can reduce the problem that external environment causes the electric connection pad oxidation, plant in the electrical quality of the conducting element of electric connection pad to improve metal coupling, solder projection or routing etc.
In conductor package substrate of the invention described above and preparation method thereof, which kind of circuit board this circuit board is not limited to, and it can be a single or multiple lift circuit board.The material that aforementioned mentioned electric connection pad provides then can be copper, nickel, chromium, titanium, copper/evanohm or tin/lead alloy.And electric connection pad described herein, preferablely can be contact mat (contact pad or Land), bump pads or its combination that wire pad (wire bonding pad can be described as Finger again), base plate for packaging and circuit board electrical couplings that routing type conductor package substrate and chip electrical couplings use are used.
In conductor package substrate of the invention described above and preparation method thereof, this welding resisting layer mainly uses the insulating barrier of substrate surface, can also protect electric connection pad, can prevent that also part is soldered to incorrect place.Preferably, the operable material of welding resisting layer is a green lacquer or pitch-dark.When this welding resisting layer of patterning, then can promptly make the welding resisting layer patterning, and form first opening of the present invention, second opening and the 3rd opening with little shadow technology in the mode of exposing and develop.
In conductor package substrate of the present invention and preparation method thereof, conductive layer can or pile up several layers metal and be formed by metal, alloy, preferably be selected from one of group that forms by copper, tin, nickel, chromium, titanium, copper-evanohm and tin-lead alloy, more preferably can use copper, and the main purpose of conductive layer is as needed current conduction path when forming successive process.In addition, when forming this conductive layer, the mode that this conductive layer can form has with one of sputter, evaporation, electroless-plating and chemical deposition.Preferably can use the mode of electroless-plating to form conductive layer.
Moreover employed resistance layer can be the resistance layer material that existing micro-photographing process is suitable among the present invention, the preferable photosensitive material that can be, and this photosensitive material can be and at least onely is selected from by dry film (dryfilm), reaches the material of group that liquid photoresistance is formed.The formation of resistance layer is unrestricted among the present invention, preferablely utilizes aforementioned manner such as printing, rotary coating, applying for it.In addition, during the patterning resistance layer, the technology that can utilize exposure and develop, with the patterning resistance layer, wherein, when the light source that uses when exposing then can be for UV-irradiation, then can be being generally used in the developer of manufacture of semiconductor when developing, and form the 4th opening of the present invention.
In conductor package substrate among the present invention and preparation method thereof, use the purpose of metal coupling to be and the thickness of electric connection pad can be thickened, can reduce the cost waste of using different materials.The operable material of this metal coupling is copper, nickel, chromium, titanium, copper/evanohm or tin/lead alloy.Preferably, metal coupling can use copper.Moreover the mode that forms this metal coupling can be used plating mode.
Therefore, the invention solves in the existing processing procedure, must be with the surperficial separate processes in routing zone and projection zone.Form one nickel/palladium/gold layer in the routing zone and in the projection zone simultaneously, not only in the routing zone, can keep with the conjugation of routing and projection zone in can keep conjugation with solder projection, and can reduce the cost and the waste of time of making.And then can keep the electrical quality at I/O contact place.
Description of drawings
Fig. 1 is the cutaway view of the method for existing manufacturing conductor package substrate;
Fig. 2 A to 2F is the cutaway view of method of the manufacturing conductor package substrate of a preferred embodiment of the present invention;
Fig. 3 is the cutaway view of the semiconductor package module of a preferred embodiment of the present invention.
Symbol description among the figure
10,20 circuit board 10a, 20a routing zone
10b, 20b projection zone 12,22a, 22b welding resisting layer
11a, 11b, 11c, 21a, 21b, 21c, 21d electric connection pad
13 nickel/gold layer 14 protective layer
15 solder projections, 23 first openings
24 second openings 25 the 3rd opening
26 conductive layers, 27 resistance layers
28 the 4th openings, 29 metal couplings
30 nickel/palladium/gold layer 31 package module
33a, 33b chip 34 metal wires
The 35a first resin portion 35b second resin portion
36 wire pads, 37 bump pads
32 solder projections
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can be implemented or be used by other different specific embodiment, and the every details in this specification also can be carried out various modifications and change based on different viewpoints and application under not departing from spirit of the present invention.
Please refer to Fig. 2 A to 2F, be the cutaway view of the manufacture method of conductor package substrate of the present invention.Yet the described graphic schematic diagram that is simplification.Described icon only shows the element relevant with the present invention, the aspect that its shown each element is non-when being actual enforcement, and component number, the shape equal proportion during its actual enforcement is an optionally design, and its component placement kenel may be more complicated.
At first, shown in Fig. 2 A, provide the circuit board 20 of a single or multiple lift, for example present embodiment is a single layer board 20, has a plurality of electric connection pad 21a, 21b, 21c, 21d in the surface of this circuit board 20.Described electric connection pad 21a, 21b, 21c, 21d for example can be copper and its material is preferable for wire pad, bump pads or contact mat or the like.
Then; shown in Fig. 2 B; in upper and lower two surfaces of this circuit board 20 via irradiate light; ultraviolet photoetching and develop to form a patterned anti-soldering layer 22a, 22b, and this welding resisting layer 22a for example via developer; the operable material of 22b is that green lacquer is with protection electric connection pad 21a; 21b, 21c, 21d.Simultaneously, have a plurality of first openings 23 and a plurality of second opening 24 among the welding resisting layer 22a of the upper surface of circuit board 20.In first opening 23, manifest the circuit board 20 of electric connection pad 21a and part, with as routing zone 20a.Electric connection pad 21a in the 20a of this routing zone can be used as a wire pad 36.In second opening 24, manifest electric connection pad 21b, with as projection zone 20b.The electric connection pad 21b of 20b can be used as a bump pads 37 in this projection zone.In the welding resisting layer 22b of the lower surface of this circuit board 20, then form a plurality of the 3rd openings 25, in described the 3rd opening 25, also manifest electric connection pad 21d.Still again need remove dregs (De-scum) operation to remove because of the interior dregs of institute's first opening 23, second opening 24 and the 3rd opening 25 etc. of being residued in that develop thereafter.
Then, shown in Fig. 2 C, in having described welding resisting layer 22a, two surfaces up and down of the circuit board 20 of 22b can form a conductive layer 26 respectively.26 of this conductive layers use the mode of electroless-plating that one bronze medal metal is formed, with as needed current conduction path in the aftermentioned processing procedure.
Moreover, use a ultraviolet light to expose via one and form a patterning resistance layer 27 in the upper surface of circuit board 20 via the mode that a developer develops with this conductive layer 26, and this resistance layer 27 has a plurality of the 4th openings 28, and described the 4th opening 28 is corresponding to second opening 24, the mode that wherein can use a pressing with a dry film as resistance layer 27 with on the surface that is formed at this circuit board 20.After abovementioned steps, still need remove the dregs operation again to remove the dregs that residued in because of developing in the 4th opening 28.
Then, shown in Fig. 2 D, form a metal coupling 29 via electroplating respectively in the 4th opening 28, the material of this metal coupling 29 then is the copper metal.Can avoid in the successive process and form this metal coupling 29, can influence the surface texture of aforementioned electric connection pad 21b, and make the not good situation of adhesion occur.
Then, shown in Fig. 2 E, remove resistance layer 27 and be covered in welding resisting layer 22a, the conductive layer 26 on 22b and circuit board 20 surfaces.That is, be retained in electric connection pad 21a, the lip-deep conductive layer 26 of 21d.
At last, shown in Fig. 2 F, in metal coupling 29 and each electric connection pad 21a, the surface of 21d all forms one nickel/palladium/gold layer 30 in the mode of electroless-plating, and wherein, this nickel/palladium/gold layer 30 forms nickel earlier, forms palladium again, just forms gold at last.Thereby finish the manufacture method of conductor package substrate of the present invention.
Therefore, please refer to Fig. 2 F, the conductor package substrate of present embodiment comprises at least: the welding resisting layer 22a of a circuit board 20, a patterning, a metal coupling 29 and one nickel/palladium/gold layer 30.Circuit board 20 both side surface have a plurality of electric connection pad 21a, 21b, and 21c, 21d, and the part electric connection pad 21a of a side surface, 21b is as wire pad 36 and bump pads 37.The welding resisting layer 22a of patterning manifests bump pads 37 and manifests wire pad 36 and wire pad 36 circuit board 20 surfaces on every side.Metal coupling 29 configurations are corresponding to bump pads 37 surfaces.Nickel/palladium/30 on gold layer is disposed at metal coupling 29 surfaces and wire pad 36 upper surfaces.
After finishing abovementioned steps, can more finish as shown in Figure 3 a semiconductor package module.Bump pads 37 in the projection zone in this package module sees through nickel/palladium/gold layer 30 surface and combines with chip 33a via a formed solder projection 32.The wire pad 36 in routing zone sees through nickel/palladium/gold layer 30 surface, electrically connects with chip 33b via a metal wire 34 (being preferably gold thread).Chip in this package module 31 can be one or more.When it is a plurality of chip 33a, in the time of 33b, described chip 33a, 33b are then stacked mutually.At last, near the zone at solder projection 32 places, inject a resin and form one first resin portion 35a, form one second resin portion 35b breaking near another resin of injection metal wire 34 regional and finish this package module 31.
In sum, the present invention utilizes same step to make the electric connection pad surface in routing zone and the metal lug surface in projection zone form one nickel/palladium/gold layer simultaneously.Can reduce processing flow, and keep the electrical quality at I/O contact place.At this, the phenomenon of the ion that foreign metal the produced migration that the palladium in nickel/palladium/gold layer mainly can prevent from the nickel to be had and influenced in the successive process adhesion with chip.Can consider that gold whether can be too thick and influenced the conjugation in projection zone, need not consider that also gold whether can be too thin and influenced the conjugation in routing zone.Solve the problem that prior art needs the division step manufacturing and loses time.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claims are described certainly, but not only limits to the foregoing description.
Claims (11)
1. a conductor package substrate is characterized in that, comprising:
One circuit board, this circuit board both side surface has a plurality of electric connection pads, and the part electric connection pad of a side surface is as wire pad and bump pads;
One patterned anti-soldering layer, it is disposed at this circuit board surface, this circuit board wherein patterned anti-soldering layer on a surface has a plurality of first openings and a plurality of second opening, described a plurality of first opening manifests this circuit board surface around this wire pad and this wire pad, described a plurality of second opening appears this bump pads, the surperficial patterned anti-soldering layer of another of this circuit board has a plurality of the 3rd openings, to manifest this electric connection pad;
One metal coupling, it disposes corresponding to this bump pads surface;
One nickel/palladium/gold layer, it is disposed at this metal lug surface and this wire pad surface; And
One conductive layer, it is disposed between this metal coupling and this bump pads, this nickel/palladium/gold layer and this wire pad between and between this nickel/palladium/gold layer and this electric connection pad.
2. conductor package substrate as claimed in claim 1, wherein, this circuit board opposite side surface also comprises the electric connection pad that has this patterned anti-soldering layer and manifest part, and this electric connection pad surface that manifests part is formed with nickel/palladium/gold layer.
3. conductor package substrate as claimed in claim 1, wherein, this circuit board is a single or multiple lift circuit board.
4. conductor package substrate as claimed in claim 1, wherein, the material that this metal coupling uses is copper, nickel, chromium, titanium, copper/evanohm or tin/lead alloy.
5. conductor package substrate as claimed in claim 1 wherein, also comprises forming the semiconductor package module, and have at least two chips, wherein, at least one chip electrically connects with this wire pad via a metal wire, and another chip electrically connects with this bump pads via solder projection at least.
6. the manufacture method of a conductor package substrate is characterized in that, comprises step:
(a) provide a circuit board, have a plurality of electric connection pads in its surface;
(b) form a patterned anti-soldering layer in this circuit board surface, and the wherein patterned anti-soldering layer on a surface of this circuit board has a plurality of first openings and a plurality of second opening, described a plurality of first opening manifests electric connection pad and partial circuit plate outer surface, with as a routing zone, described a plurality of second opening manifests electric connection pad, with as a projection zone, the surperficial patterned anti-soldering layer of another of this circuit board forms a plurality of the 3rd openings, to manifest electric connection pad;
(c) form a conductive layer in this circuit board surface with this welding resisting layer;
(d) form a patterning resistance layer in the circuit board surface with this conductive layer, and this resistance layer has a plurality of the 4th openings, described the 4th opening is corresponding to described second opening;
(e) in described the 4th opening, form a metal coupling respectively;
(f) remove this resistance layer and be covered in the conductive layer of this welding resisting layer and this circuit board surface; And
(g) form one nickel/palladium/gold layer in this metal coupling and described electric connection pad surface.
7. the manufacture method of conductor package substrate as claimed in claim 6, wherein, this nickel/palladium/gold layer forms with one of sputter, evaporation, electroless-plating and chemical deposition.
8. the manufacture method of conductor package substrate as claimed in claim 6, also comprise and form the semiconductor package module, and have at least two chips, wherein, at least one chip electrically connects with this wire pad via a metal wire, and another chip electrically connects with this bump pads via solder projection at least.
9. the manufacture method of conductor package substrate as claimed in claim 6 wherein, forms described first opening, described second opening and described the 3rd opening in the mode of exposing and develop in this welding resisting layer.
10. the manufacture method of conductor package substrate as claimed in claim 6 wherein, forms described the 4th opening in the mode of exposing and develop in this resistance layer.
11. the manufacture method of conductor package substrate as claimed in claim 6, wherein, this metal coupling forms with plating mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101482552A CN101383335B (en) | 2007-09-04 | 2007-09-04 | Semiconductor package substrate and fabrication method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101482552A CN101383335B (en) | 2007-09-04 | 2007-09-04 | Semiconductor package substrate and fabrication method thereof |
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| CN101383335A CN101383335A (en) | 2009-03-11 |
| CN101383335B true CN101383335B (en) | 2010-06-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8110931B2 (en) | 2008-07-11 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Wafer and semiconductor package |
| TWI372453B (en) | 2008-09-01 | 2012-09-11 | Advanced Semiconductor Eng | Copper bonding wire, wire bonding structure and method for processing and bonding a wire |
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| CN2791881Y (en) * | 2004-09-27 | 2006-06-28 | 威盛电子股份有限公司 | Chip package structure |
| CN101005057A (en) * | 2006-01-20 | 2007-07-25 | 日月光半导体制造股份有限公司 | Chip packaging structure and its line connection process |
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