CN102244058A - Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method - Google Patents
Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method Download PDFInfo
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- CN102244058A CN102244058A CN2010101786102A CN201010178610A CN102244058A CN 102244058 A CN102244058 A CN 102244058A CN 2010101786102 A CN2010101786102 A CN 2010101786102A CN 201010178610 A CN201010178610 A CN 201010178610A CN 102244058 A CN102244058 A CN 102244058A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention provides a quad flat lead-free semiconductor package and a manufacturing method thereof and a metal plate used in the manufacturing method. The method comprises the step of stamping the metal plate to obtain a chip holding pad and multiple convex solder pads, wherein the area of at least one cross section of each convex solder pad is larger than that of another cross section below the cross section and the area of at least one cross section of the chip holding pad is larger than that of another cross section below the cross section so that the chip holding pad and the solder pads are embedded in a packaging colloid. Besides, in the method provided by the invention, the metal plate is removed after the packaging colloid is formed, thus the colloid can be prevented from flowing over to the bottoms of the convex solder pads.
Description
Technical field
The present invention relates to a kind of encapsulating structure and method for making thereof, relate in particular to a kind of quad flat do not have lead foot semiconductor package part (Quad Flat Non Leaded Package, QFN) and method for making.
Background technology
Existing chip be with lead frame (Lead Frame) as chip bearing member to form the semiconductor packaging part, and this lead frame mainly comprises a chip carrier and be formed at this chip carrier a plurality of lead foots on every side, gluing chip on this chip carrier, and after electrically connecting this chip and lead foot with bonding wire, again potting resin is coated the inner segment of this chip, chip carrier, bonding wire and lead foot and form the semiconductor package part of this tool lead frame.
With regard to the integrated circuit technique development, continuous towards the higher technology evolution of integration on semiconductor technology, and highdensity assembling structure is the target of pursuing for the dealer.And the carrier (carrier) that chip size structure dress is adopted comprising: lead frame (lead frame), soft substrate plate (flexible substrate) or hard substrate (rigid substrate) etc., because it is low that lead frame has a cost, characteristics such as handling ease are electronic product chip size structure dress type commonly used; Non-pin square flat structure dress (QFN) wherein is for the lead frame being the chip size structure dress (lead frame based CSP) of structure dress base material, it is characterized in that not being provided with outer lead foot, promptly be not formed with outer lead foot, and can dwindle overall dimensions in order to electrically connect with the external world.
Seeing also Fig. 4 A, is to be United States Patent (USP) the 6th, 143,981,6,130,115, and disclosed for 6,198, No. 171 do not have the cutaway view of lead foot structure dress (QFN) as the quad flat of chip bearing member with lead frame; As shown in the figure, be on lead frame 40, to set firmly chip 42 with pin 41, and this chip 42 also is electrically connected to this pin 41 by bonding wire 43, form encapsulation material 44 to coat this lead frame 40, chip 42, to reach bonding wire 43, and the bottom surface that makes the pin 41 of this lead frame 40 exposes to this encapsulation material 44 surfaces, makes this QFN semiconductor package must be by these pin that exposes 41 exposed surfaces directly to electrically connect with the external device (ED) of external device such as printed circuit board (PCB) (printed circuit board) by soldering tin material (not with graphic representation).
Above-mentioned existing wire-frame type structure, the I/O negligible amounts that can provide can't satisfy the high-order product, and after cutting single technology, this pin has the risk that comes off.Moreover, because this pin that exposes 41 and encapsulation material 44 flush, when formation soldered ball 46 on this pin that exposes 41 electrically connects with the printed circuit board (PCB) with external device (ED), shown in Fig. 4 B, this soldered ball 46 is easy to generate bridge joint (solder bridge), and cause producing between this pin 41 bridge joint or short circuit, and cause the electric connection condition of poor.
For obtaining more I/O quantity, also have on copper clad laminate and form lead frame by etching mode, to obtain more pins, yet, the etch process step is various and consuming time, no matter and be the packaging part of earlier figures 4A or the lead frame that obtains with etching mode, when inserting packing colloid, all there is the problem of the glue that overflows, cause and can't plant soldered ball and influence soldered ball and the electric connection of pin by cloth.In addition, the lead frame that etching mode forms, its structure is separated and imperfect, and the situation of sealing-off is arranged often in the ultrasonic waves welding.
Therefore, in view of the above-mentioned problems, provide more I/O quantity, and avoid the pin of conventional semiconductor packages part to come off and the packing colloid problems such as glue of overflowing, the real problem of desiring most ardently solution at present that become as the technology of how simplifying.
Summary of the invention
Disadvantages in view of above-mentioned prior art, the objective of the invention is to, semiconductor package part and method for making thereof that a kind of quad flat do not have lead foot and the metallic plate that is used to make semiconductor package part are provided, provide more I/O quantity with the manufacturing process of simplifying, and avoid the pin of conventional semiconductor packages part to come off and the packing colloid problems such as glue of overflowing.
To achieve these goals, the invention provides the semiconductor package part that a kind of quad flat does not have lead foot, comprising: put chip mat, wherein, in this put the thickness range of chip mat, this at least one cross-sectional area of putting chip mat was greater than its another cross-sectional area of below; A plurality of projection welding pads are located at this and are put around the chip mat, and wherein, in the thickness range of this projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below, and the end face of this projection welding pad is higher than the end face of putting chip mat; Be arranged at this and put chip on the chip mat; Bonding wire electrically connects this chip and reaches respectively this projection welding pad; And packing colloid, coat this and put chip mat, projection welding pad, chip and bonding wire, make this put the bottom surface that chip mat and projection welding pad are embedded in this packing colloid and expose outside those projection welding pads and put chip mat.
For obtaining semiconductor package part of the present invention, the present invention also provides a kind of quad flat not have the method for making of the semiconductor package part of lead foot, comprising: preparing a definition has a plurality of metallic plates of putting chip region; With this metallic plate of die stamping, with on metallic plate respectively this is put chip region and forms and to put chip mat, and put in this that chip region is peripheral to form a plurality of projection welding pads, wherein, in this puts the thickness range of chip mat and projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below, and this at least one cross-sectional area of putting chip mat is greater than its another cross-sectional area of below, and the bottom surface of this projection welding pad is higher than the bottom surface of putting chip mat; In respectively this is put to connect on the chip mat and puts chip; Electrically connect this chip and projection welding pad with bonding wire; In this metallic plate, chip and be welded in line and cover packing colloid, this projection welding pad is embedded in this packing colloid; Remove this metallic plate bottom, make this put chip mat and respectively this projection welding pad be spaced apart from each other; And cut this packing colloid, to form a plurality of semiconductor package parts.
In aforesaid method for making, this mould can comprise male model, master mold and a plurality of insert, and this master mold has depression and groove that a plurality of arrays are arranged, be positioned at the same depression that lists in order to connection, wherein, this groove is established wherein for the insert cunning, makes this depression aperture area less than the depression floor space.
In another execution mode, this punching press forms this step of putting chip mat and projection welding pad and comprises with this metallic plate of die stamping to form a plurality of chip mat and projection welding pads put; And suppress this and put chip mat and projection welding pad end face, so that in this puts the thickness range of chip mat and projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below, and this at least one cross-sectional area of putting chip mat is greater than its another cross-sectional area of below.
On the other hand, the present invention also provides a kind of metallic plate that quad flat does not have the semiconductor package part of lead foot that is used to make, comprise: a plurality of projection welding pads, be one of the forming on this metallic plate, and those projection welding pads surround puts chip region, wherein, in the thickness range of this projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below; Put chip mat, be positioned at and put chip region, wherein, in this put the thickness range of chip mat, this at least one cross-sectional area of putting chip mat was greater than its another cross-sectional area of below; And a plurality of holes, correspondence is formed at rebasing of respectively this projection welding.
As from the foregoing, semiconductor package part of the present invention and method for making thereof, be prior to stamping out the projection welding pad on the metallic plate, connect and put and electrically connect chip and form packing colloid, just cut single job afterwards, the excessive glue problem in the time of can avoiding prior art perfusion packing colloid, in addition, projection welding spacer on the metallic plate of the present invention has the function of inlay card, can avoid after forming packing colloid, and the projection welding pad comes off from encapsulating in the colloid.Again, the end face of projection welding pad is higher than the end face of putting chip mat, can reduce the height of routing, dwindles the volume of overall package part.Semiconductor package part of the present invention and method for making, not only prevent to overflow glue and projection welding pad come off, and have more simplification technology, and the advantage of more I/O quantity is provided.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Figure 1A to Fig. 1 E " there is not the method for making schematic diagram of the semiconductor package part of lead foot for quad flat of the present invention, wherein, Figure 1B ' is the vertical view of the master mold of Figure 1B; Fig. 1 D ' is for having the semiconductor package part schematic diagram in hole, and Fig. 1 E is the semiconductor package part schematic diagram that the projection welding pad flushes with the packing colloid side; And Fig. 1 E ' is for having the semiconductor package part schematic diagram of welding resisting layer;
Fig. 2 A to Fig. 2 C forms another method for making schematic diagram of projection welding pad for the present invention;
Fig. 3 A to Fig. 3 C forms the method for making schematic diagram of putting chip mat for another punching press of the present invention, and wherein, Fig. 3 C has the semiconductor package part schematic diagram of putting chip mat; And
Fig. 4 A and Fig. 4 B are existing with the cutaway view of lead frame as the non-pin square flat structure dress (QFN) of chip bearing member.
Wherein, Reference numeral
1,3 semiconductor package parts, 10,20,30 metallic plates
11,31 put chip region 12,22,32 moulds
121 male models, 122 master molds
123 inserts, 1221 depressions
1222 grooves, 13,23,33 projection welding pads
131 holes, 14,34,42 chips
15,35,43 bonding wires, 16,36 packing colloids
17,37,46 soldered balls, 18 welding resisting layers
181 perforates 221,221 ' patrix
222 counterdies 19,29,38 are put chip mat
381 protruding pad 40 lead frames
41 pins, 44 encapsulation materials
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
And the palpus explanation is, " end face " narrated in this specification and " bottom surface " and nisi concept of space, but change with the spatial relationship of constitutive requirements, that is, when being inverted the semiconductor package part of this case shown in graphic, " end face " " bottom surface " and " bottom surface " " end face ".Use of those so " end faces ", " bottom surface " noun, be in order to the connection relationship between constitutive requirements in the disclosed semiconductor package part to be described, make disclosed semiconductor package part in the scope of equivalence, have rational variation and replacement, but but not in order to limit practical range of the present invention in a specific aspect (Embodiment).
First embodiment
See also Figure 1A to Fig. 1 E ", be the method for making that explanation quad flat of the present invention does not have the semiconductor package part of lead foot.
Shown in Figure 1A, prepare a definition a plurality of metallic plates 10 of putting chip region 11 are arranged, this metallic plate can be copper, in addition, these metallic plate 10 upper and lower surfaces can be formed with metal level by plating, it can comprise one or more materials that are selected from gold, palladium, silver, copper and group that nickel is formed, for example, gold/palladium/nickel/the palladium layer forms in regular turn or the multiple layer metal of gold/nickel/copper/nickel/silver, gold/nickel/copper/silver, palladium/nickel/palladium, gold/nickel/gold or palladium/nickel/gold one of them constitute.
Shown in Figure 1B and Figure 1B ', with this metallic plate 10 of mould 12 punching presses, with on metallic plate 10 respectively this is put chip region 11 and forms and put chip mat 19, and put in this that chip region 11 is peripheral to form a plurality of projection welding pads 13, wherein, in this puts the thickness h, h ' scope of chip mat 19 and projection welding pad 13, at least one cross-sectional area of this projection welding pad 13 is greater than its another cross-sectional area of below, and this at least one cross-sectional area of putting chip mat 19 is greater than its another cross-sectional area of below, and the bottom surface of this projection welding pad 13 is higher than the bottom surface of putting chip mat 19.This projection welding pad 13 can be dovetail or half dovetail, and shown in Figure 1B, this projection welding pad 13 is a dovetail, any two cross sections in the thickness h scope of this projection welding pad 13, and the area of top cross section is greater than the area of another cross section of below.Again, also can be included in after this metallic plate of punching press, form metal level in this metallic plate upper and lower surface (not shown).
On the implementation, this mould 12 comprises male model 121, master mold 122 and a plurality of insert 123, and 122 vertical views of the master mold shown in Figure 1B ', this master mold 122 has depression 1221 and the groove 1222 that a plurality of arrays are arranged, be to be positioned at the same depression that lists 1221 in order to connection, wherein, this groove 1222 is for insert 123 sliding establishing wherein, make these depression 1221 aperture areas less than depression 1221 floor spaces, thereby after punching press, obtain the projection welding pad 13 of dovetail.
Shown in Fig. 1 C,, then electrically connect this chip 14 and projection welding pad 13 with bonding wire 15 in respectively this is put to connect on the chip mat 19 and puts chip 14; Afterwards again in this metallic plate 10, cover packing colloid 16 on chip 14 and the bonding wire 15, because the area of arbitrary cross section of dovetail projection welding pad 13 all greater than the area of another cross section of below (in the present invention, hole 131 cross sections in the projection welding pad 13 also calculate in the cross section of projection welding pad 13), for example top surface area is greater than base area, so that this projection welding pad 13 is embedded in this packing colloid 16, in addition, because of the bottom surface of this projection welding pad 13 is higher than the bottom surface of putting chip mat 19, and the end face of projection welding pad 13 is higher than the end face of putting chip mat 19, can reduce the height of routing, dwindle the volume of overall package part, moreover, because of metallic plate is a continuous structure, the defective of sealing-off in the time of can reducing the ultrasonic waves welding.During again because of the formation packing colloid, this metallic plate still is a continuous structure, more can prevent the problem of excessive glue.
Shown in Fig. 1 D, remove this metallic plate 10 bottoms in modes such as milling cutter or etchings, make respectively this this put chip mat 19 and projection welding pad 13 is spaced apart from each other.Consult Fig. 1 D ' again, be different among Fig. 1 D this and put chip mat 19 and projection welding pad 13 bottoms flush with the packing colloid bottom, when removing these metallic plate 10 bottoms, owing to can set press depth during punching press, be able in remove metallic plate 10 optionally make obtain put the corresponding hole 131 that forms in chip mat and projection welding pad 13 bottom surfaces, shown in Fig. 1 E, this hole can be laid wherein for soldered ball 17, between soldered ball 17 and projection welding pad, provide preferable bond strength, cut this packing colloid 16 at last, to form a plurality of semiconductor package parts 1.On the other hand, when adjacent two encapsulation units have shared projection welding pad, in carrying out cutting step, can be shown in Fig. 1 E ', the projection welding pad 13 that cutting packing colloid 16 and adjacent two semiconductor packaging parts are shared, outermost projection welding pad 13 sides with the semiconductor package part that makes gained expose, and flush with packing colloid 16 sides.Certainly also can be shown in Fig. 1 E, adjacent two encapsulation units do not have shared projection welding pad 13, and 16 of packing colloids envelope projection welding pad 13 sides.
In addition, as Fig. 1 E " shown in, also can be included in remove this metallic plate 10 after, on these packing colloid 16 bottom surfaces, form welding resisting layer 18, and make this welding resisting layer 18 have a plurality ofly exposing for corresponding that respectively this puts the welding resisting layer perforate 181 of chip mat 19 and projection welding pad 13.In this example,, do not exceed with this aspect though do explanation with projection welding pad 13 with hole 131.
Second embodiment
Present embodiment and aforementioned method for making are roughly the same, and its difference is different impact styles.Punching press shown in Fig. 2 A to Fig. 2 C forms the step that this puts chip mat and projection welding pad, comprises earlier with this metallic plate 20 of mould 22 punching presses of comprising patrix 221 and counterdie 222 to form a plurality of chip mat 29 and projection welding pads 23 put; And once more, suppress this and put chip mat 29 and projection welding pad 23 end faces, so that in this puts the thickness range of chip mat 29 and projection welding pad 23, even if projection welding pad 23 end faces and off-peak area, still there be the relation of at least one cross-sectional area,, make projection welding pad 23 be embedded in packing colloid with after forming packing colloid greater than its another cross-sectional area of below, similarly, make this at least one cross-sectional area of putting chip mat 29 greater than its another cross-sectional area of below.Particularly, shown in Fig. 2 B, can utilize another patrix 221 ' to suppress this once more and put chip mat 29 and projection welding pad 23 end faces, finally demould can obtain having the metallic plate 20 of projection welding pad 23.
The 3rd embodiment
Present embodiment and aforementioned method for making are roughly the same, and its difference is to put the chip mat profile.As shown in Figure 3A, the step of this metallic plate 30 of punching press also comprises puts chip region 31 with mould 32 punching presses and forms and put chip mat 38, and this is put chip mat 38 and is made of 381 on a plurality of protruding pads, and its profile can be identical with projection welding pad 33.Similarly, in this put the thickness range of chip mat 38, this at least one cross-sectional area of putting chip mat 38 was greater than its another cross-sectional area of below.
According to aforesaid method for making, the invention provides a kind of quad flat does not have the semiconductor package part 1,3 of lead foot, shown in Fig. 1 E and Fig. 3 C, this semiconductor package part 1,3 comprises: put chip mat 19,38, wherein, in this put the thickness range of chip mat 19,38, this at least one cross-sectional area of putting chip mat was greater than its another cross-sectional area of below; A plurality of projection welding pads 13,33, put around the chip mat 19,38 for being located at this, wherein, in the thickness range of this projection welding pad 13,33, at least one cross-sectional area of this projection welding pad 13,33 is greater than its another cross-sectional area of below, and the end face of this projection welding pad 13,33 is higher than the end face of putting chip mat 19,38; Chip 14,34 is arranged at this and puts on the chip mat 19,38; Bonding wire 15,35 electrically connects this chip 14,34 and reaches respectively this projection welding pad 13,33; And packing colloid 16,36, coat this and put chip mat 19,38, projection welding pad 13,33, chip 14,34 and bonding wire 15,35, make this put chip mat 19,38 and projection welding pad 13,33 is embedded in this packing colloid 16,36 and the bottom surface that exposes outside those projection welding pads 13,33 and put chip mat 19,38.In addition, this projection welding pad 13,33 and put chip mat 19,38 bottom surfaces and can connect and be equipped with soldered ball 17,37.
In semiconductor package part of the present invention, this projection welding pad 13 and put chip mat 19 and can be dovetail shown in Fig. 1 E perhaps can be half dovetail or other shape.
Shown in Fig. 1 E ', this semiconductor package part also can comprise welding resisting layer 18, and for being formed on these packing colloid 16 bottom surfaces, and this welding resisting layer 18 has and a plurality ofly exposes for corresponding that respectively this puts the welding resisting layer perforate 181 of chip mat 19 and projection welding pad 13.
On the other hand, according to aforesaid method for making, the invention provides a kind of metallic plate that quad flat does not have the semiconductor package part of lead foot that is used to make, shown in Fig. 1 C, this metallic plate 10 comprises: a plurality of projection welding pads 13 are one of the forming on this metallic plate 10, and those projection welding pads 13 surround puts chip region 11, wherein, in the thickness range of this projection welding pad 13, at least one cross-sectional area of this projection welding pad 13 is greater than its another cross-sectional area of below; Put chip mat 19, be positioned at and put chip region 11, wherein, in this put the thickness range of chip mat 19, this at least one cross-sectional area of putting chip mat 19 was greater than its another cross-sectional area of below; And a plurality of holes 131, for correspondence is formed at respectively these projection welding pad 13 bottom surfaces.
Semiconductor package part of the present invention and method for making thereof, be prior to stamping out the projection welding pad on the metallic plate, connect and put and electrically connect chip and form packing colloid, just cut single job afterwards, the excessive glue problem in the time of can avoiding prior art perfusion packing colloid, in addition, put the function that chip mat and projection welding spacer have inlay card on the metallic plate of the present invention, can avoid after forming packing colloid, the projection welding pad comes off from encapsulating in the colloid, and promotes reliability.Again preferably, the mode of punching press also can make this put the chip mat height to be lower than the projection welding pad, help reducing the height of packaging part, reduced volume promotes heat conductivility, semiconductor package part of the present invention and method for making, prevent that not only excessive glue and projection welding pad from coming off, have more simplified manufacturing technique, the advantage of more I/O quantity is provided.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (12)
1. a quad flat does not have the semiconductor package part of lead foot, it is characterized in that, comprising:
Put chip mat, wherein, in this put the thickness range of chip mat, this at least one cross-sectional area of putting chip mat was greater than its another cross-sectional area of below;
A plurality of projection welding pads are located at this and are put around the chip mat, and wherein, in the thickness range of this projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below, and the end face of this projection welding pad is higher than the end face of putting chip mat;
Chip is arranged at this and puts on the chip mat;
Bonding wire electrically connects this chip and reaches respectively this projection welding pad; And
Packing colloid coats this and puts chip mat, projection welding pad, chip and bonding wire, makes this put the bottom surface that chip mat and projection welding pad are embedded in this packing colloid and expose outside those projection welding pads and put chip mat.
2. quad flat according to claim 1 does not have the semiconductor package part of lead foot, it is characterized in that, this projection welding pad is dovetail or half dovetail.
3. quad flat according to claim 1 does not have the semiconductor package part of lead foot, it is characterized in that, this puts chip mat is dovetail or half dovetail.
4. quad flat according to claim 1 does not have the semiconductor package part of lead foot, it is characterized in that, also comprises welding resisting layer, be formed on this packing colloid bottom surface, and this welding resisting layer has and a plurality ofly exposes for corresponding that respectively this puts the welding resisting layer perforate of chip mat and projection welding pad.
5. a quad flat does not have the method for making of the semiconductor package part of lead foot, it is characterized in that, comprising:
Prepare a definition a plurality of metallic plates of putting chip region are arranged;
With this metallic plate of die stamping, with on metallic plate respectively this is put chip region and forms and to put chip mat, and put in this that chip region is peripheral to form a plurality of projection welding pads, wherein, in this puts the thickness range of chip mat and projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below, and this at least one cross-sectional area of putting chip mat is greater than its another cross-sectional area of below, and the bottom surface of this projection welding pad is higher than the bottom surface of putting chip mat;
In respectively this is put to connect on the chip mat and puts chip;
Electrically connect this chip and projection welding pad with bonding wire;
Cover packing colloid in this metallic plate, chip and bonding wire, this projection welding pad is embedded in this packing colloid;
Remove this metallic plate bottom, make this put chip mat and respectively this projection welding pad be spaced apart from each other; And
Cut this packing colloid, to form a plurality of semiconductor package parts.
6. quad flat according to claim 5 does not have the method for making of the semiconductor package part of lead foot, it is characterized in that, this mould comprises male model, master mold and a plurality of insert, and this master mold has depression and groove that a plurality of arrays are arranged, be positioned at the same depression that lists in order to connection, wherein, this groove is established wherein for the insert cunning, makes this depression aperture area less than the depression floor space.
7. quad flat according to claim 5 does not have the method for making of the semiconductor package part of lead foot, it is characterized in that, punching press forms this step of putting chip mat and projection welding pad and comprises with this metallic plate of die stamping to form a plurality of chip mat and projection welding pads put; And suppress this and put chip mat and projection welding pad end face, so that in this puts the thickness range of chip mat and projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below, and this at least one cross-sectional area of putting chip mat is greater than its another cross-sectional area of below.
8. quad flat according to claim 5 does not have the method for making of the semiconductor package part of lead foot, it is characterized in that, the end face of this projection welding pad is higher than the end face of putting chip mat.
9. quad flat according to claim 5 does not have the method for making of the semiconductor package part of lead foot, it is characterized in that, also is included in before or after this metallic plate of punching press, forms metal level in this metallic plate upper and lower surface.
10. quad flat according to claim 6 does not have the method for making of the semiconductor package part of lead foot, it is characterized in that, this projection welding pad is dovetail or half dovetail.
11. quad flat according to claim 5 does not have the method for making of the semiconductor package part of lead foot, it is characterized in that, also be included in remove this metallic plate after, on this packing colloid bottom surface, form welding resisting layer, and make this welding resisting layer have a plurality ofly exposing for corresponding that respectively this puts the welding resisting layer perforate of chip mat and projection welding pad.
12. one kind is used to make the metallic plate that quad flat does not have the semiconductor package part of lead foot, it is characterized in that, comprising:
A plurality of projection welding pads are one of the forming on this metallic plate, and those projection welding pads surround and put chip region, and wherein, in the thickness range of this projection welding pad, at least one cross-sectional area of this projection welding pad is greater than its another cross-sectional area of below;
Put chip mat, be positioned at and put chip region, wherein, in this put the thickness range of chip mat, this at least one cross-sectional area of putting chip mat was greater than its another cross-sectional area of below; And
A plurality of holes, correspondence are formed at rebasing of respectively this projection welding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101786102A CN102244058A (en) | 2010-05-13 | 2010-05-13 | Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101786102A CN102244058A (en) | 2010-05-13 | 2010-05-13 | Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102244058A true CN102244058A (en) | 2011-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101786102A Pending CN102244058A (en) | 2010-05-13 | 2010-05-13 | Quad flat lead-free semiconductor package and manufacturing method thereof and metal plate used in manufacturing method |
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| Country | Link |
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| CN (1) | CN102244058A (en) |
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Application publication date: 20111116 |