CN101017785A - Semiconductor stack structure and its making method - Google Patents
Semiconductor stack structure and its making method Download PDFInfo
- Publication number
- CN101017785A CN101017785A CNA2006100074320A CN200610007432A CN101017785A CN 101017785 A CN101017785 A CN 101017785A CN A2006100074320 A CNA2006100074320 A CN A2006100074320A CN 200610007432 A CN200610007432 A CN 200610007432A CN 101017785 A CN101017785 A CN 101017785A
- Authority
- CN
- China
- Prior art keywords
- substrate
- stack structure
- semiconductor stack
- making
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Wire Bonding (AREA)
Abstract
The provided preparation method for semiconductor stack structure comprises: setting semiconductor chip and a peripheral support device on a first substrate, setting the second substrate with pre-set chip on one surface on the support device and electric connecting with the first one by welding wire; packing and stem pressing to form a package colloid encasing the semiconductor chip and wire and the second substrate and exposing the chip top from the collid; removing the chip to expose the first surface of the second substrate for electronic element. This invention prevents different pollution.
Description
Technical field
The invention relates to a kind of semiconductor device and method for making, particularly about a kind of semiconductor stack structure and method for making thereof.
Background technology
Current electronic product develops to direction multi-functional, electrically high and high-speed cruising, and for cooperating this developing direction, semiconductor manufacturing industry is is actively researched and developed and can be integrated the semiconductor device of a plurality of chips or packaging part, so that meet the electronic product demand.
See also Fig. 1, United States Patent (USP) the 5th, 222, the stack architecture that discloses a kind of semiconductor package part No. 014, it provides a upper surface to be provided with first ball bar array (BGA) substrate 11 of weld pad 110, so that on this first ball bar multiple substrate 11, connect the packing colloid 13 of putting semiconductor chip 10 and forming this semiconductor chip 10 of parcel, and then another is finished the second ball bar multiple substrate 12 of encapsulation, connect by soldered ball 14 and to put and to be electrically connected on this weld pad 110, form the stack architecture of semiconductor packaging part.
But, in above-mentioned semiconductor package stacking structure, this second ball bar multiple substrate 12 is electrically connected to the number of these first ball bar multiple substrate, 11 weld pads 110, be subjected to the size impact of this packing colloid 13, thereby reduced storehouse, also limited simultaneously packaging part type and electrical I/O (I/O) number that carries out storehouse, promptly can only limit and select specific storehouse packaging part type and electrical I/O (I/O) configuration from the laying of weld pad 110, in addition, when carrying out the storehouse processing procedure, because of being subjected to the limitation in height of soldered ball 14, the height that is located at the packing colloid 13 on the first ball bar multiple substrate 11 needs minimization (it is following generally to be limited in 0.3mm), thereby has increased the difficulty of processing procedure.
See also Fig. 2, United States Patent (USP) the 6th, 828, disclosed another kind of semiconductor package stacking structure No. 664, it provides a upper surface to be provided with the first ball bar multiple substrate 21 of weld pad 210, so that on this first ball bar multiple substrate 21, connect and put semiconductor chip 20, and make this semiconductor chip 20 be electrically connected to this first ball bar multiple substrate 21 by bonding wire 25, then the second ball bar multiple substrate 22 is connect by soldered ball 24 and put and be electrically connected to this weld pad 210, form this semiconductor chip 20 of parcel again, the packing colloid 23 of the bonding wire 25 and the second ball bar multiple substrate 22, and the top of exposing this second ball bar multiple substrate 22, put another packaging part 26 so that on this second ball bar multiple substrate 22, connect.
But, in above-mentioned stack architecture, after it is electrically connected to this first ball bar multiple substrate 21 with semiconductor chip 20 by bonding wire 25, utilize back welding process that the second ball bar multiple substrate 22 is electrically connected to this first ball bar multiple substrate 21 by soldered ball 24 again, like this, not only influence this bonding wire 25 quality, more can cause the pollution of the semiconductor chip 20 and the first ball bar multiple substrate 21 simultaneously, cause problems such as product quality decline and reliability reduction.
See also Fig. 3 A to Fig. 3 C, United States Patent (USP) the 6th, 861, disclosed a kind of method for making that does not adopt back welding process storehouse packaging part for No. 288, it is finished to put on the brilliant substrate 31 one and sets up a metal supporting frames 37, semiconductor chip 30 is contained in this metal supporting frames 37 belows, on this metal supporting frames 37, connect again and put storehouse substrate 32, and make this storehouse substrate 32 utilize bonding wire 352 to be electrically connected to this substrate 31 (as shown in Figure 3A), one special dies 38 with patrix 381 parts then is provided, these patrix 381 inboard apical margins are preset a protuberance 382, be connected to this storehouse substrate 32 tops, can around these patrix 381 protuberances 382, form accommodation space 383 simultaneously and be installed with this bonding wire 352, by the substrate 31 of above-mentioned connection storehouse substrate 32 is wherein ccontaining, encapsulate molding operation, form this semiconductor chip 30 of parcel, the packing colloid 33 of bonding wire 352 and storehouse substrate 32 (shown in Fig. 3 B), removable subsequently this mould 38, make the top of this storehouse substrate 32 expose this packing colloid 33, so that at these storehouse substrate 32 top storehouse packaging parts 36 (shown in Fig. 3 C).
But, in above-mentioned method for making, to additionally provide metal supporting frames 37, cause the processing procedure cost to increase, in addition, its processing procedure will use special dies to avoid the bonding wire 352 on second substrate 32 to touch mould, thereby causes the processing procedure cost to improve.
In addition, above-mentioned United States Patent (USP) the 6th, 828, No. 664 and the 6th, 861, No. 288 in the mold pressing processing procedure that forms packing colloid, very likely make the packing colloid glue that overflows, pollute the second ball bar multiple substrate or storehouse substrate, cause the follow-up difficulty of removing glue operation and packaging part storehouse and electric connection.
Therefore, how a kind of semiconductor stack structure and method for making thereof are provided, need not limit by the size of storehouse packaging part, type and electrical I/O number, and do not adopt soldered ball reflow mode to electrically connect the storehouse substrate, can avoid because of using special dies to cause the processing procedure cost to increase, and in the encapsulation molding operation problem such as excessive glue pollution storehouse substrate, become present industry problem demanding prompt solution.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor stack structure and method for making thereof, need not limit by the size of storehouse packaging part, type and electrical I/O number.
Another object of the present invention is to provide a kind of semiconductor stack structure and method for making thereof, in the time of can avoiding adopting the reflow mode to electrically connect the storehouse substrate, cause the semiconductor chip pollution problems.
Another purpose of the present invention is to provide a kind of semiconductor stack structure and method for making thereof, can avoid because of using special dies to cause the processing procedure cost to increase.
A further object of the present invention is to provide a kind of semiconductor stack structure and method for making thereof, can avoid in the encapsulation molding operation because of the problem of excessive glue pollution storehouse substrate.
For realizing above-mentioned and other purpose, the method for making of semiconductor stack structure of the present invention comprises: connect at least on first substrate and put and electrically connect the semiconductor chip, and around should semiconductor chip strutting piece be set on this first substrate; One second substrate with first surface and relative second surface connect put on this strutting piece, the subregion of this first surface covers a paster, and this second substrate connects with its second surface and puts on this strutting piece; Utilize bonding wire to electrically connect this first substrate and second substrate; And encapsulate molding operation, on this first substrate, form the packing colloid of this semiconductor chip of parcel, strutting piece, second substrate, bonding wire and paster, and make this paster top expose this packing colloid.Removable subsequently this paster makes the part first surface of this second substrate expose this packing colloid; And expose at this second substrate to connect on the first surface of this packing colloid and put and electrically connect electronic component.This semiconductor chip is with routing or cover brilliant mode and be electrically connected to this first substrate.Semiconductor stack structure of the present invention can adopt single or batch mode manufacturing.
Semiconductor stack structure of the present invention comprises: first substrate; At least one semiconductor chip connects and puts and be electrically connected to this first substrate; Strutting piece is located on this first substrate, and to around should semiconductor chip; Second substrate with first surface and second surface, this second substrate is put on this strutting piece by connecing around the second surface; Bonding wire electrically connects this first and second substrate; And packing colloid, be formed on this first substrate, and wrap up this semiconductor chip, bonding wire, strutting piece and second substrate, make the first surface of this second substrate expose this packing colloid.This semiconductor stack structure also comprises: electronic component connects and puts and be electrically connected on second substrate that exposes this packing colloid.
In addition, in other execution mode of semiconductor stack structure of the present invention and method for making thereof, can also on the second surface of this second substrate, connect earlier and put and electrically connect semiconductor chip, passive device or packaging part at least, second surface with this second substrate supports the strutting piece that is located on this first substrate again, strengthens the semiconductor stack structure electrical functionality.In addition, this strutting piece can adopt useless chip, metal derby, collets or substrate strip etc., when if this strutting piece is substrate strip, this second substrate can be electrically connected to this substrate strip, and be electrically connected to this first substrate from this substrate strip, utilize the electrical bridgeware of this substrate strip, directly be electrically connected to the required wire length of this first substrate thereby shorten second substrate as this first and second substrate.
Therefore, semiconductor stack structure of the present invention and method for making thereof are to connect to put semiconductor chip and the sticking strutting piece of establishing around this semiconductor chip on first substrate, second substrate of the default paster in one surface is provided simultaneously, this second substrate that is provided with paster connect put on this strutting piece, and be electrically connected to this first substrate by bonding wire, the structure of this first and second substrate of connection can be contained in one subsequently has in the traditional moulds of patrix, and make this patrix medial roof be against this paster top, so that carry out the injecting glue operation, on this first substrate, form the parcel semiconductor chip, bonding wire, the packing colloid of second substrate and paster, then, removable this mould, make this paster top expose this packing colloid, remove the first surface that this paster exposes this second substrate then, connect for electronic components such as semiconductor chip or semiconductor package parts and put on it.Therefore, in semiconductor stack structure of the present invention and method for making thereof, the weld pad of semiconductor chip or the packaging part storehouse second substrate first surface on it exposes this packing colloid fully, thereby need not limit by the storehouse package size, type and electrical I/O number, this second substrate is electrically connected to this first substrate in the routing mode simultaneously, cause the semiconductor chip pollution problems when having avoided existing employing soldered ball reflow mode to electrically connect first and second substrate, in addition, by being preset in the paster on second substrate, can avoid existing stack architecture in the encapsulation molding operation, use special dies to cause the processing procedure cost to increase, and the problem of excessive glue pollution second substrate, thereby reduce the cost of making semiconductor stack structure.
Description of drawings
Fig. 1 is a United States Patent (USP) the 5th, 222, the semiconductor package stacking structure generalized section of No. 014 announcement;
Fig. 2 is a United States Patent (USP) the 6th, 828, the semiconductor package stacking structure generalized section of No. 664 announcements;
Fig. 3 A is a United States Patent (USP) the 6th, 861 to Fig. 3 C, the method for making generalized section of the semiconductor package stacking structure of No. 288 announcements;
Fig. 4 A is the generalized section of semiconductor stack structure of the present invention and method for making embodiment 1 thereof to Fig. 4 G;
Fig. 5 A and Fig. 5 B are that semiconductor stack structure of the present invention connects the floor map of putting strutting piece on first substrate;
Fig. 6 A and Fig. 6 B are that semiconductor stack structure of the present invention is provided with paster on the surface second substrate prepares schematic diagram;
Fig. 7 is the generalized section of semiconductor stack structure embodiment 2 of the present invention;
Fig. 8 is the generalized section of semiconductor stack structure embodiment 3 of the present invention;
Fig. 9 is the generalized section of semiconductor stack structure embodiment 4 of the present invention;
Figure 10 is the generalized section of semiconductor stack structure embodiment 5 of the present invention;
Figure 11 A and Figure 11 B are the generalized sections of semiconductor stack structure embodiment 6 of the present invention; And
Figure 12 A is the generalized section of semiconductor stack structure of the present invention and method for making embodiment 7 thereof to Figure 12 D.
Embodiment
Embodiment 1
Fig. 4 A is the method for making generalized section of semiconductor stack structure of the present invention to Fig. 4 G.
Shown in Fig. 4 A, one first substrate 41 is provided, this first substrate 41 can be the ball bar multiple substrate, be convenient on this first substrate 41, connect and put and electrically connect semiconductor chip 40 at least, and on this first substrate 41 to should semiconductor chip around 40 with gluing (adhesive) modes such as (not marking), bonding strutting piece 47; Wherein this semiconductor chip 40 is electrically connected to this first substrate 41 by a plurality of bonding wires 451, and this strutting piece 47 is useless chip, metal derby or collets etc., and the height of this strutting piece 47 is greater than the bank height of this bonding wire 451.
Please cooperate and consult Fig. 5 A and Fig. 5 B, it has shown that this strutting piece 47 is configured in the floor map on this first substrate 41, this strutting piece 47 be arranged in relatively this semiconductor chip 40 around or both sides, but not as limit.
Shown in Fig. 4 B, one second substrate 42 with first surface 421 and relative second surface 422 is provided, the subregion of this first surface 421 covers a paster 49, and the second surface 422 of this second substrate 42 connects in gluing (adhesive) (not marking) mode and puts on this strutting piece 47, and this second substrate 42 is supported on this semiconductor chip 40.
Please cooperate and consult Fig. 6 A and Fig. 6 B, it is the preparation schematic diagram of this second substrate 42, promptly provide one to have a plurality of second substrates 42 and be the substrate module sheet 42A that array is arranged each other earlier, the first surface core of this second substrate 42 is provided with a plurality of weld pads 423, and first surface peripheral part of this second substrate 42 is provided with a plurality of wire bond pads 424, and relatively one paster 49 is set at the core of these second substrate, 42 first surfaces, by covering this weld pad 423; Respectively cut at these second substrate, 42 edges on the edge again, forms second substrate 42 that a plurality of surfaces are provided with paster 49, connects and put on strutting piece 47.
Shown in Fig. 4 C, carry out the routing operation, utilize bonding wire 452 to make the wire bond pad 424 on this second substrate 42 be electrically connected to this first substrate 41, wherein the bank height of this bonding wire 452 is lower than the thickness of this paster 49.
Shown in Fig. 4 D, provide one to have the traditional moulds 48 of patrix 481, these patrix 481 inboard accommodation spaces 480 that form have first substrate 41 of second substrate 42 to be placed in one in storehouse on it, and make these patrix 481 inboard apical margin contacts to the paster 49 that is located on this second substrate 42.
Shown in Fig. 4 E, carry out Encapsulation Moulds compacting journey, on this first substrate 41, form the packing colloid 43 of this semiconductor chip 40 of parcel, second substrate 42, bonding wire 452 and paster 49, removable subsequently this mould makes these paster 49 tops expose this packing colloid 43.
Shown in Fig. 4 F, utilize to divest or mode such as chemical agent removes this paster 49, expose the weld pad 423 of these second substrate, 42 first surface cores fully, but semiconductor chip or packaging part storehouse are on it.
Shown in Fig. 4 G, can on this second substrate 42 exposes the first surface of this packing colloid 43, connect electronic components 46 such as putting semiconductor chip, passive device or another semiconductor package part subsequently, and make this electronic component 46 be electrically connected to weld pad 423 on this second substrate 42.In addition, also soldered ball 44 can be set, be used to be electrically connected to external device (ED) in these first substrate, 41 bottom surfaces.
By above-mentioned method for making, the present invention has disclosed a kind of semiconductor stack structure, and this semiconductor stack structure comprises: first substrate 41; At least one semiconductor chip 40 connects and puts and be electrically connected to this first substrate 41; Strutting piece 47 is bonded on this first substrate 41 and to around should semiconductor chip 40; Second substrate 42 with first surface 421 and second surface 422 connects around the second surface 422 of this second substrate 42 and puts on this strutting piece 47; Bonding wire 452 electrically connects this first and second substrate 41 and 42; And packing colloid 43, be formed on this first substrate 41, and wrap up this semiconductor chip 40, bonding wire 452, strutting piece 47 and second substrate 42, and make the part first surface 421 of this second substrate 42 expose this packing colloid 43.In addition, this stack architecture also comprises: at least one electronic component 46 connects and puts on the first surface 421 of second substrate 42 that exposes this packing colloid 43.
Therefore, semiconductor stack structure of the present invention and method for making thereof are to connect to put semiconductor chip on first substrate, and around this semiconductor chip bonding strutting piece, second substrate of the default paster in one surface is provided simultaneously, this second substrate that is provided with paster connect put on this strutting piece, and be electrically connected to this first substrate by bonding wire, the structure of this first and second substrate of connection can be contained in one subsequently has in the traditional moulds of patrix, and make this patrix medial roof be against this paster top, so that carry out the injecting glue operation, on this first substrate, form the parcel semiconductor chip, bonding wire, the packing colloid of second substrate and paster, then, removable this mould, make this paster top expose this packing colloid, remove this paster then, expose the weld pad of this second substrate first surface fully, electronic components such as semiconductor chip or semiconductor package part can connect and put on it.Therefore, in semiconductor stack structure of the present invention and method for making thereof, weld pad for semiconductor chip or the packaging part storehouse second substrate first surface on it exposes this packing colloid fully, need not limit by the storehouse package size, type and electrical I/O number, this second substrate is electrically connected to this first substrate in the routing mode simultaneously, cause the semiconductor chip pollution problem in the time of can avoiding existing soldered ball reflow mode to electrically connect first and second substrate, in addition, by being preset in the paster on second substrate, also can avoid existing stack architecture in the encapsulation molding operation, to use special dies to cause the problem of increase of processing procedure cost and excessive glue pollution second substrate, thereby the cost of making semiconductor stack structure is reduced.
Embodiment 2
Fig. 7 is the generalized section of semiconductor stack structure embodiment 2 of the present invention.
This semiconductor stack structure is made by being similar to said method in present embodiment 2, and main difference is that semiconductor chip 40 is to connect and put and be electrically connected to first substrate 41 by covering crystal type.
Embodiment 3
Fig. 8 is the generalized section of semiconductor stack structure embodiment 3 of the present invention.
The semiconductor stack structure of present embodiment 3 and embodiment 1 are roughly the same, mainly make semiconductor chip 40 be electrically connected to first substrate 41 earlier by bonding wire 451, its main difference is to connect on the second surface 422 of second substrate 42 in advance to put semiconductor chip 400, and this semiconductor chip 400 is electrically connected to this second substrate 42 to cover crystal type, subsequently this second substrate 42 is connect to put on strutting piece 47 and by bonding wire 452 and be electrically connected to this first substrate 41, thereby strengthen the electrical functionality of stack architecture.
Embodiment 4
Fig. 9 is the generalized section of semiconductor stack structure embodiment 4 of the present invention.
The semiconductor stack structure of present embodiment 4 and embodiment 2 are roughly the same, mainly be to make semiconductor chip 40 be electrically connected to this first substrate 41 by covering crystal type, its main difference is to connect on the second surface 422 of second substrate 42 in advance to put semiconductor chip 400, and this semiconductor chip 400 is electrically connected to this second substrate 42 in the routing mode, subsequently this second substrate 42 is connect to put on strutting piece 47 and by bonding wire 452 and be electrically connected to this first substrate 41, thereby strengthen the electrical functionality of stack architecture.
Embodiment 5
Figure 10 is the generalized section of semiconductor stack structure embodiment 5 of the present invention.
The semiconductor stack structure of present embodiment 5 and embodiment 2 are roughly the same, mainly be to make semiconductor chip 40 be electrically connected to this first substrate 41 by covering crystal type, its main difference is to connect on the second surface 422 of second substrate 42 in advance to put semiconductor chip 400, and this semiconductor chip 400 is electrically connected to this second substrate 42 to cover crystal type, subsequently this second substrate 42 is connect to put on strutting piece 47 and by bonding wire 452 and be electrically connected to this first substrate 81, thereby strengthen the electrical functionality of stack architecture.
In addition, in the above-described embodiments, put and electrically connect the semiconductor chip except connecing on this second substrate 42, also can select to electrically connect passive device and packaging part etc., thereby promote or improve the electrical functionality of stack architecture.
Embodiment 6
Figure 11 A and Figure 11 B are the generalized sections of semiconductor stack structure embodiment 6 of the present invention.
The semiconductor stack structure of present embodiment 6 and embodiment 1 are roughly the same, main difference is to be bonded in semiconductor chip 40 strutting piece on every side to adopt substrate strip 57, second substrate 42 is electrically connected to this substrate strip 57, and be electrically connected to this first substrate 51 by this substrate strip 57, required wire length when shortening directly this second substrate 42 of electric connection and first substrate 41.
Shown in Figure 11 A, this substrate strip 57 is provided with electric connection pad 570, second substrate 42 connect put behind this strutting piece as substrate strip 57, can utilize first bonding wire 551 to electrically connect the electric connection pad 570 of this second substrate 42 and this substrate strip 57 earlier, utilize second bonding wire 552 to electrically connect the electric connection pad 570 and this first substrate 41 of this substrate strip 57 again.
Shown in Figure 11 B, this second substrate 42 also can directly utilize conductive projection 553 to connect the electric connection pad 570 of putting and be electrically connected to this substrate strip 57, electric connection pad 570 by this substrate strip 570 utilizes bonding wire 554 to be electrically connected to this first substrate 41 again, and this substrate strip 57 electrically connects this first and second substrate as electrical bridgeware.
Embodiment 7
Figure 12 A is the generalized section of semiconductor stack structure of the present invention and method for making embodiment 7 thereof to Figure 12 D.The semiconductor stack structure of present embodiment 7 and method for making thereof and embodiment 1 are roughly the same, and main difference is in the present embodiment, and this semiconductor stack structure can adopt the batch mode processing procedure, thereby improve processing procedure speed and reduce manufacturing cost.
Shown in Figure 12 A, the one first substrate module sheet 61A with a plurality of first substrates 61 is provided, on this first substrate 61 respectively, connect and put and electrically connect semiconductor chip 60, and around this semiconductor chip 60 bonding strutting piece 67, on this strutting piece 67, connect and put one second substrate 62, and a paster 69 is arranged on this second substrate 62, cover the weld pad 623 on these second substrate, 62 surfaces, and utilize bonding wire 652 that this second substrate 62 is electrically connected to this first substrate 61.
Shown in Figure 12 B, carry out Encapsulation Moulds compacting journey, on this first substrate module sheet 61A, form the packing colloid 63 of a parcel semiconductor chip 60, strutting piece 67, second substrate 62, bonding wire 652 and paster 69, and make this paster top expose this packing colloid.
Shown in Figure 12 C, also connect soldered ball 64, and correspondence cuts between this first substrate 61 respectively in this first substrate, 61 bottom surfaces respectively, separate respectively this first substrate 61.
Shown in Figure 12 D, follow removable this paster 69, expose the weld pad 623 on this second substrate 62 fully, connect thereon subsequently and put and electrically connect semiconductor chip, packaging part or passive device etc.
Claims (25)
1. the method for making of a semiconductor stack structure is characterized in that, the method for making of this semiconductor stack structure comprises:
On first substrate, connect at least and put and electrically connect the semiconductor chip, and on this first substrate, around should semiconductor chip, strutting piece be set;
One second substrate with first surface and relative second surface connect put on this strutting piece, the subregion of this first surface covers a paster, and the second surface of this second substrate connects and puts on this strutting piece;
Utilize bonding wire to electrically connect this first substrate and second substrate; And
Encapsulate molding operation, on this first substrate, form the packing colloid of this semiconductor chip of parcel, strutting piece, second substrate, bonding wire and paster, and make this paster top expose this packing colloid.
2. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, the method for making of this semiconductor stack structure also comprises:
Remove this paster, make the part first surface of this second substrate expose this packing colloid;
Expose at this second substrate to connect on the first surface of this packing colloid and put and electrically connect electronic component.
3. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, this semiconductor chip is with routing or cover brilliant mode and be electrically connected to this first substrate.
4. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, this strutting piece is useless chip, metal derby or collets.
5. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, this strutting piece is a substrate strip, and this second substrate is electrically connected to this substrate strip, and is electrically connected to this first substrate by this substrate strip.
6. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, second base plate preparation method that this surface is provided with paster comprises:
Provide one to have a plurality of second substrates and be the substrate module sheet that array is arranged, the core of this second substrate first surface is provided with a plurality of weld pads, and this second substrate first surface peripheral part is provided with a plurality of wire bond pads, and in this second substrate center one paster is set partly and covers this weld pad;
Cut on edge respectively this second substrate edges, forms second substrate that a plurality of surfaces are provided with paster.
7. the method for making of semiconductor stack structure as claimed in claim 6 is characterized in that, this wire bond pad makes this second substrate be electrically connected to this first substrate by bonding wire.
8. the method for making of semiconductor stack structure as claimed in claim 6 is characterized in that, can expose this weld pad after this paster removes, and electronic component is electrically connected to this weld pad.
9. the method for making of semiconductor stack structure as claimed in claim 1, it is characterized in that, first substrate that this storehouse has second substrate is arranged on one to have in the mould of patrix, and makes the inboard apical margin of this patrix prop up the paster that is located on this second substrate, so that encapsulate molding operation.
10. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, the second surface of this second substrate can connect puts and electrically connect semiconductor chip, passive device or packaging part.
11. the method for making of semiconductor stack structure as claimed in claim 10 is characterized in that, this semiconductor chip is with routing or cover brilliant mode and be electrically connected to this second substrate.
12. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, the thickness of this paster is greater than the bank height of bonding wire.
13. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, this first substrate bottom surface is provided with soldered ball.
14. the method for making of semiconductor stack structure as claimed in claim 1 is characterized in that, this semiconductor stack structure can adopt single or batch mode manufacturing.
15. the method for making of semiconductor stack structure as claimed in claim 14 is characterized in that, the batch mode method for making of this semiconductor stack structure comprises:
The one first substrate module sheet with a plurality of first substrates is provided, on this first substrate respectively, connect and put and electrically connect semiconductor chip, and strutting piece is set around this semiconductor chip, on this strutting piece, connect and put second substrate, on this second substrate, form a paster, form the weld pad of this second substrate surface by covering, and utilize bonding wire that this second substrate is electrically connected to this first substrate;
Carry out Encapsulation Moulds compacting journey, on this first substrate module sheet, form the packing colloid of a parcel semiconductor chip, strutting piece, second substrate, bonding wire and paster, and make this paster top expose this packing colloid;
Connect in this first substrate bottom surface respectively and to put soldered ball, and correspondence respectively cuts between this first substrate, so that separate respectively this first substrate; And
Remove this paster, expose the weld pad on this second substrate fully.
16. a semiconductor stack structure is characterized in that, this semiconductor stack structure comprises:
First substrate;
At least one semiconductor chip connects and puts and be electrically connected to this first substrate;
Strutting piece is located on this first substrate, and to around should semiconductor chip;
Second substrate with first surface and second surface, this second substrate is put on this strutting piece by connecing around the second surface;
Bonding wire electrically connects this first and second substrate; And
Packing colloid is formed on this first substrate, and wraps up this semiconductor chip, bonding wire, strutting piece and second substrate, makes the first surface of this second substrate expose this packing colloid.
17. semiconductor stack structure as claimed in claim 16 is characterized in that, this semiconductor stack structure also comprises: electronic component connects and puts and be electrically connected on second substrate that exposes this packing colloid.
18. semiconductor stack structure as claimed in claim 16 is characterized in that, this semiconductor chip is with routing or cover brilliant mode and be electrically connected to this first substrate.
19. semiconductor stack structure as claimed in claim 16 is characterized in that, this strutting piece is useless chip, metal derby or collets.
20. semiconductor stack structure as claimed in claim 16 is characterized in that, this strutting piece is a substrate strip, and this second substrate is electrically connected to this substrate strip, and is electrically connected to this first substrate by this substrate strip.
21. semiconductor stack structure as claimed in claim 16 is characterized in that, the first surface core of this second substrate is provided with a plurality of weld pads, and first surface peripheral part of this second substrate is provided with a plurality of wire bond pads.
22. semiconductor stack structure as claimed in claim 21 is characterized in that, this wire bond pad makes this second substrate be electrically connected to this first substrate by bonding wire.
23. semiconductor stack structure as claimed in claim 21 is characterized in that, this weld pad can electrically connect electronic component.
24. semiconductor stack structure as claimed in claim 16 is characterized in that, the second surface of this second substrate can connect puts and electrically connects semiconductor chip, passive device or packaging part.
25. semiconductor stack structure as claimed in claim 24 is characterized in that, this semiconductor chip is with routing or cover brilliant mode and be electrically connected to this second substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100074320A CN101017785A (en) | 2006-02-10 | 2006-02-10 | Semiconductor stack structure and its making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100074320A CN101017785A (en) | 2006-02-10 | 2006-02-10 | Semiconductor stack structure and its making method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101017785A true CN101017785A (en) | 2007-08-15 |
Family
ID=38726682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100074320A Pending CN101017785A (en) | 2006-02-10 | 2006-02-10 | Semiconductor stack structure and its making method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101017785A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546742B (en) * | 2008-03-26 | 2012-05-30 | 日本电气株式会社 | Mounting structure of semiconductor device and electronic apparatus using thereof |
| CN104916645A (en) * | 2014-03-13 | 2015-09-16 | 株式会社东芝 | Semiconductor device and manufacture method of the same |
| CN108886024A (en) * | 2016-03-31 | 2018-11-23 | 索尼公司 | Semiconductor device, manufacturing method for semiconductor device, integrated substrate and electronic equipment |
| CN112259463A (en) * | 2020-09-04 | 2021-01-22 | 深圳市安捷芯源半导体有限公司 | Packaging method of fan-out chip and fan-out chip packaging structure |
| WO2021174470A1 (en) * | 2020-03-05 | 2021-09-10 | 华为技术有限公司 | Circuit structure and electronic device |
| CN113658933A (en) * | 2021-08-20 | 2021-11-16 | 名校友(北京)科技有限公司 | Laminated semiconductor packaging structure |
| CN117391038A (en) * | 2023-10-23 | 2024-01-12 | 北京市合芯数字科技有限公司 | Metal stack space information dividing method of chip layout and chip |
-
2006
- 2006-02-10 CN CNA2006100074320A patent/CN101017785A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101546742B (en) * | 2008-03-26 | 2012-05-30 | 日本电气株式会社 | Mounting structure of semiconductor device and electronic apparatus using thereof |
| CN104916645A (en) * | 2014-03-13 | 2015-09-16 | 株式会社东芝 | Semiconductor device and manufacture method of the same |
| CN104916645B (en) * | 2014-03-13 | 2018-09-14 | 东芝存储器株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| CN108886024A (en) * | 2016-03-31 | 2018-11-23 | 索尼公司 | Semiconductor device, manufacturing method for semiconductor device, integrated substrate and electronic equipment |
| WO2021174470A1 (en) * | 2020-03-05 | 2021-09-10 | 华为技术有限公司 | Circuit structure and electronic device |
| CN112259463A (en) * | 2020-09-04 | 2021-01-22 | 深圳市安捷芯源半导体有限公司 | Packaging method of fan-out chip and fan-out chip packaging structure |
| CN112259463B (en) * | 2020-09-04 | 2022-06-24 | 深圳市安捷芯源半导体有限公司 | Packaging method of fan-out chip and fan-out chip packaging structure |
| CN113658933A (en) * | 2021-08-20 | 2021-11-16 | 名校友(北京)科技有限公司 | Laminated semiconductor packaging structure |
| CN117391038A (en) * | 2023-10-23 | 2024-01-12 | 北京市合芯数字科技有限公司 | Metal stack space information dividing method of chip layout and chip |
| CN117391038B (en) * | 2023-10-23 | 2024-05-14 | 北京市合芯数字科技有限公司 | Metal stack space information dividing method of chip layout and chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5032623B2 (en) | Semiconductor memory device | |
| JP3205235B2 (en) | Lead frame, resin-encapsulated semiconductor device, method of manufacturing the same, and mold for manufacturing semiconductor device used in the manufacturing method | |
| CN100539054C (en) | Chip-packaging structure and preparation method thereof | |
| TW454287B (en) | Multi-media chip package and its manufacture | |
| US6965154B2 (en) | Semiconductor device | |
| CN101017785A (en) | Semiconductor stack structure and its making method | |
| US8354739B2 (en) | Thin semiconductor package and method for manufacturing same | |
| JP2014236056A (en) | Semiconductor device | |
| CN101740407A (en) | Process for encapsulating square flat outer-pin-free encapsulating structure | |
| CN101241890A (en) | Chip package structure and its making method | |
| JP2005150459A (en) | Semiconductor device and its manufacturing method | |
| CN102270589B (en) | The manufacture method of semiconductor element and corresponding semiconductor element | |
| CN101814461B (en) | Packaging substrate structure and chip packaging structure, as well as manufacturing method thereof | |
| CN101465300B (en) | LED optical strip and method of manufacturing the same | |
| TWI380379B (en) | Package structure and manufacturing method thereof | |
| CN102208401A (en) | LED (Light-emitting diode) light strip | |
| CN100361317C (en) | Package of possessing support piece for packing light sensitive semiconductor | |
| CN101165886B (en) | Semiconductor packaging member for semiconductor device stacking and its manufacture method | |
| JP3599031B2 (en) | Semiconductor device | |
| JP2002033432A (en) | Manufacturing method of semiconductor device | |
| TW200830496A (en) | Substrate structure for semiconductor package and package method thereof | |
| US8368189B2 (en) | Auxiliary leadframe member for stabilizing the bond wire process | |
| CN104103536A (en) | Package-on-package (POP) packaging method | |
| CN110931371B (en) | Semiconductor device and method for manufacturing the same | |
| US20090004783A1 (en) | Method of package stacking using unbalanced molded tsop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |