CN104916645B - The manufacturing method of semiconductor device and semiconductor device - Google Patents
The manufacturing method of semiconductor device and semiconductor device Download PDFInfo
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- CN104916645B CN104916645B CN201410453794.7A CN201410453794A CN104916645B CN 104916645 B CN104916645 B CN 104916645B CN 201410453794 A CN201410453794 A CN 201410453794A CN 104916645 B CN104916645 B CN 104916645B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention relates to the manufacturing method of semiconductor device and semiconductor device, which can be improved the movement speed of semiconductor device, and reduce mounting area.The semiconductor device of embodiment has：Wiring substrate；1st semiconductor chip is arranged on wiring substrate, and has the 1st thickness；1st spacer and the 2nd spacer are arranged Deng in a manner of being detached across the 1st semiconductor chip on wiring substrate, and with the 2nd thickness compared with the 1st thickness thickness；2nd semiconductor chip is arranged in a manner of overlapping the 1st semiconductor chip on the 1st spacer and the 2nd spacer；Sealing resin layer is set to around by wiring substrate, the 1st spacer, the 2nd spacer and the 2nd semiconductor chip area encompassed and the 2nd semiconductor chip.1st spacer and the 2nd spacer contain dielectric resin material.
Description
[related application]
Present application was enjoyed with No. 2014-50427 (applying date of Japanese patent application case：On March 13rd, 2014) based on
The priority of application case.Present application includes the full content of basic application case by referring to the basis application case.
Technical field
The invention of embodiment is related to the manufacturing method of a kind of semiconductor device and semiconductor device.
Background technology
In recent years, miniaturization and the high speed of semiconductor device are required with the development of mechanics of communication and the information processing technology
Change.To cope with this, there are following technologies, i.e., in semiconductor devices, have the three-dimensional of a plurality of semiconductor chips to pacify by lamination
It fills and shortens the wiring lengths between part to cope with the increase of operating frequency, and improve mounting area efficiency.
For example, in the semiconductor devices such as NAND (with non-) type memory, from from the viewpoint of miniaturization and high speed and
There is on same wiring substrate lamination to have the three-dimension mount characteristic of controller chip and memory chip.It is constructed as three-dimensional, example
As research has with chip attachment film (Die Attach Film：DAF) adhesive linkages overlay controller chip and the product on adhesive linkage such as
Construction (the Film On Die of layer memory chip：FOD, film cover chip) or using silicon partition lamination memory chip construction
Deng.
Even if when using the situation of the three-dimension mount characteristic, it is also preferably reduced as far as the increasing of manufacturing cost
Add.To use the chip attachment film to realize three-dimension mount characteristic, it is necessary to thicken chip attachment film in case controller chip with
Memory chip is in direct contact.However, if chip attachment film thickens, cutting speed can not be promoted, and material applicatory
Also limited, therefore manufacturing cost increases.Also, using silicon partition situation when, because must for each chip come be arranged silicon every
The reasons such as piece and cause manufacturing cost to increase.
Invention content
The present invention is to provide the semiconductor device and its manufacturing method that a kind of movement speed is very fast and mounting area is smaller.
The semiconductor device of embodiment has：Wiring substrate；1st semiconductor chip is arranged on wiring substrate, and
With the 1st thickness；1st spacer and the 2nd spacer, Deng be arranged in a manner of being detached across the 1st semiconductor chip with
On line substrate, and with the 2nd thickness compared with the 1st thickness thickness；2nd semiconductor chip, to overlap the side of the 1st semiconductor chip
Formula is arranged on the 1st spacer and the 2nd spacer；And sealing resin layer, it is set to by between wiring substrate, the 1st spacer, the 2nd
Around spacing body and the 2nd semiconductor chip area encompassed and the 2nd semiconductor chip.1st spacer and the 2nd spacer contain
There is dielectric resin material.
Description of the drawings
Figure 1A and B is the figure for the structure example for indicating semiconductor device.
Fig. 2A~C is the sectional view for the manufacturer's rule for illustrating semiconductor device.
Fig. 3 A and B are the sectional views for the manufacturer's rule for illustrating semiconductor device.
Fig. 4 is the sectional view for another structure example for indicating semiconductor device.
Fig. 5 is the sectional view for another structure example for indicating semiconductor device.
Specific implementation mode
Hereinafter, being illustrated to the semiconductor device of embodiment with reference to schema.Furthermore schema is schematic person, such as
There are the situations different with actual conditions such as the relationship of thickness and planar dimension, the ratio of each layer thickness.Also, in embodiment
In, the same symbol is enclosed to substantially the same inscape and is omitted the description.
Fig. 1 is the figure of the structure example for the semiconductor device for indicating present embodiment, and Fig. 1 (A) is vertical view, and Fig. 1 (B) is edge
The sectional view of the line segment X-Y of Fig. 1 (A).Semiconductor device 1 has shown in Fig. 1 (A) and Fig. 1 (B)：Wiring substrate 2；Spacer
3a is arranged on wiring substrate 2；Spacer 3b is arranged in a manner of being detached with spacer 3a on wiring substrate 2；Half
Conductor chip 4, the region being clipped between spacer 3a and spacer 3b being arranged on wiring substrate 2；Semiconductor chip 6,
It is arranged across spacer 3a and spacer 3b on wiring substrate 2 in a manner of overlapping semiconductor chip 4；It installs on surface
Element 9 is arranged on wiring substrate 2；Sealing resin layer 10, sealing semiconductor chips 4 and semiconductor chip 6 etc..Furthermore
Sealing resin layer not shown 10 for the sake of convenience in Fig. 1 (A).
Wiring substrate 2 such as has shown in Fig. 1 (B)：Insulating layer 21 is arranged between the 1st face and the 2nd face；Wiring layer 22,
It is arranged in the 1st face；Wiring layer 23 is arranged in the 2nd face；Through-hole 24 penetrates through insulating layer 21 and is arranged；External connection terminals
25, it is electrically connected at wiring layer 23；Solder resist 28 is arranged on wiring layer 22；And solder resist 29, it is arranged in wiring layer
On 23.Furthermore the 1st face of wiring substrate 2 is equivalent to the surface of the wiring substrate 2 in Fig. 1 (B), and the 2nd face is equivalent in Fig. 1 (B)
Wiring substrate 2 lower surface, the 1st face of wiring substrate 2 and the 2nd face are mutually opposite.Furthermore for the sake of convenient in Fig. 1 (A) and not
Illustrate wiring layer 22, wiring layer 23, through-hole 24, external connection terminals 25, solder resist 28 and solder resist 29.
Spacer 3a is arranged on the 1st face on wiring substrate 2, and spacer 3b is arranged in a manner of being detached with spacer 3a
On the 1st face of wiring substrate 2 ((A) referring to Fig.1).That is, spacer 3a and spacer 3b are with across semiconductor chip 4 and phase
The mode mutually detached is arranged on wiring substrate 2.By making spacer 3a and spacer 3b separation, and can spacer 3a and
The inflow entrance and outflux of sealing resin are set between spacing body 3b.Even if thus, for example after semiconductor chip 6 is arranged, still
Sealing resin can be filled to the region for being provided with semiconductor chip 4 via inflow entrance and outflux, sealing resin layer can be passed through
10 sealing semiconductor chips 4.At this point, the interval of spacer 3a and spacer 3b can also be wider than the width of semiconductor device.Also, close
The viscosity of envelope resin be according to such as the interval of spacer 3a and spacer 3b or the thickness of spacer 3a and spacer 3b and
Setting.
When semiconductor chip 4 is set as having 1 thickness, spacer 3a and spacer 3b preferably have compared with the 1st thickness
The 2nd thick thickness.It can be easy to fill sealing resin into the gap of semiconductor chip 4 and semiconductor chip 6 as a result,.Also,
The thickness of spacing body 3a and spacer 3b are preferably identical.The thickness of spacer 3a and spacer 3b can be set as such as 100 μm~150
μm。
The shape of spacer 3a and spacer 3b are not particularly limited, as long as that can fill sealing resin to semiconductor core
Piece 6 times.Also, can also make the area of the spacer 3a and one of spacer 3b under vertical view more than the area of another one.Also,
Also can spacer 3a and spacer 3b be set in a manner of being stretched out at least partially from semiconductor chip 6 under vertical view.
Furthermore the quantity of spacer is not limited to two, the spacer more than or equal to three may also set up.At this point, stream
At least one of entrance or outflux are formed with a plurality of.It can be easy to fill sealing resin to semiconductor chip 4 as a result,.
Spacer 3a and spacer 3b preferably contains dielectric resin material, preferably contain be applicable to solder resist 28 and
The material (such as polyimides system resins etc.) of solder resist 29.For one, it is applicable to the material of solder resist 28 and solder resist 29
Material, even if be also easy in the situation of thick-film processing and it is cheap.Even if also, in the feelings for manufacturing a plurality of semiconductor devices
When shape, the spacer 3a and spacer 3b of each semiconductor device also can be once formed in same step.Therefore, it can be greatly lowered
The manufacturing cost of spacer 3a and spacer 3b.Also, passing through at least part use and resistance in spacer 3a and spacer 3b
29 identical material of solder flux 28 and solder resist, also can be improved the compatibility of spacer 3a and spacer 3b and solder resist 28.Furthermore
As the material of spacer 3a and spacer 3b, by containing SiO2Contour rigid material and the warpage that wiring substrate 2 can be reduced.
Semiconductor chip 4 is arranged on the 1st face of wiring substrate 2.Semiconductor chip 4 is by closing line 7 and wiring
Substrate 2 is electrically connected, and is electrically connected at semiconductor chip 6 via wiring substrate 2.For example, being arranged in semiconductor chip 4
Electronic pads and the connection gasket that is arranged in wiring substrate 2 be bonded to closing line 7.Furthermore semiconductor chip 4 and wiring substrate 2
Connection method is not limited to routing engagement or flip-chip bond or the automatic engagement of coil type etc. without wire bonding.As
Semiconductor chip 4 can be used such as controller chip, interface chip.In turn, other logic circuits etc. can be also arranged half
Conductor chip 4.Furthermore the size of semiconductor chip 4 is preferably the size less than semiconductor chip 6.
Semiconductor chip 6 is arranged in a manner of overlapping semiconductor chip 4 on spacer 3a and spacer 3b.That is,
Semiconductor chip 6 is supported as bridge leg using spacer 3a and spacer 3b.Semiconductor chip 6 is by closing line 8
It is electrically connected with wiring substrate 2.Such as be arranged semiconductor chip 6 electronic pads and connection gasket in wiring substrate 2 is set
It is bonded to closing line 8.Therefore, semiconductor chip 6 is electrically connected at semiconductor chip 4 via wiring substrate 2.
Semiconductor chip 6 is to be bonded in spacer 3a and spacer 3b by adhesive linkage 5.In turn, a plurality of semiconductors
Chip 6 is the lamination in a manner of across a part of overlapping of adhesive linkage 5.At this point, a plurality of semiconductor chips 6 pass through closing line 8
And it is electrically connected with each other.As adhesive linkage 5, such as chip attachment film can be used.Diagram lamination has four in Fig. 1 (A) and Fig. 1 (B)
The example of a semiconductor chip 6, but it's not limited to that for the lamination number of semiconductor chip 6.
As semiconductor chip 6, can be used such as the memory chip with memory element NAND type flash memory
Deng.At this point, semiconductor chip 6 can also have decoder etc. in addition to storage unit.Use memory chip as semiconductor
When the situation of chip 6, also can semiconductor chip 4 controlled using controller the data relative to memory chip write-in and
It reads.
Surface mounted component 9 is arranged on the 1st face of wiring substrate 2.As surface mounted component 9, can be used for example warm
Spend the electronic components such as sensor.By keeping surface mounted component 9 Chong Die with semiconductor chip 6, and it can inhibit semiconductor device
The increase of mounting area.Furthermore surface mounted component 9 can need not be also set.
Sealing resin layer 10 is surrounded by wiring substrate 2, spacer 3a, spacer 3b and semiconductor chip 6 with sealing
Region and semiconductor chip 6 around mode be arranged.That is, sealing resin layer 10 is in a manner of covering semiconductor chip 4
Setting, and then be arranged in a manner of covering semiconductor chip 6, surface mounted component 9.Sealing resin layer 10 contains inorganic fill material
Material (such as SiO2), and be using such as by the inorganic filling material and the sealing resin mixed organic resin and passing through
The methods of forming such as transfer formation method, compression forming methods, jet forming method and formed.
Such as in Fig. 1 (A) and Fig. 1 (B) as an example shown in stock, in the semiconductor device of present embodiment, using with set
It sets and forms spacer in the identical material of solder resist of wiring substrate, and (partly led in the 1st semiconductor chip by spacer
Body chip 4) on the 2nd semiconductor chip (semiconductor chip 6) of lamination, thus can shorten the length of the wiring between part, therefore can
It improves movement speed and mounting area can be reduced, and then manufacturing cost can be reduced.
Secondly, an example of the manufacturing method of the semiconductor device as present embodiment, to shown in Fig. 1 (A) and Fig. 1 (B)
Manufacturer's rule of semiconductor device illustrate.
Fig. 2 and Fig. 3 is the sectional view for the manufacturer's rule for illustrating semiconductor device.In the manufacturer of semiconductor device
In rule, first as shown in Fig. 2 (A), prepare wiring substrate 2.A plurality of wiring substrates are made with matrix as an example herein
The assembly substrate of the construction of shape connection setting.Furthermore, it is possible to use commercially available wiring substrate.
In wiring substrate 2, as insulating layer 21, such as silicon substrate, glass substrate, ceramic substrate, epoxy glass can be used
Resin substrates such as glass etc..
It is formed such as signal wire, power cord, ground wire in wiring layer 22 and wiring layer 23.Furthermore wiring layer 22 and match
The each of line layer 23 is not limited to monolayer constructions, or across insulating layer and lamination has via the opening portion of insulating layer and it is electric
Property connection plural conductive layer lamination construction.In wiring layer 22 and the use of wiring layer 23 such as copper foil, copper, silver or contain this
Deng conductive plating or conductive paste, also can nickel plating or gold-plated etc. optionally be applied to surface.
Through-hole 24 be formed in a manner of penetrating through insulating layer 21 it is a plurality of.Through-hole 24 has for example to be arranged to insulate in perforation
The conductor layer of the inner surface of the opening of layer 21 and filling are to the filling perforation material on the inside of conductor layer.Such as copper, silver are used in conductor layer
Or containing such conductive plating or conductive paste, also can nickel plating or gold-plated etc. optionally be applied to surface.Filling perforation material is to make
It is formed with such as insulating materials or conductive material.Furthermore it's not limited to that, such as also can be by using plating etc. by metal
Through-hole 24 is formed in material (copper etc.) filling to through hole.
In solder resist 28 opening portion is formed in such a way that at least part (connection gasket etc.) of wiring layer 22 is exposed.In welding resistance
Agent 29 forms opening portion in such a way that at least part (connection gasket etc.) of wiring layer 23 is exposed.As solder resist 28 and solder resist
29, for example described insulative resin material can be used, such as uv-hardening resin or thermmohardening type resin etc. can be used.
In turn, as shown in Fig. 2 (A), insulating resin layer 3 is formed on wiring substrate 2.As insulating resin layer 3, can be used
Such as such as lower layer, this layer of use are applicable to the material of solder resist 28 and solder resist 29.
Secondly, as shown in Fig. 2 (B), spacer 3a and spacer are formed by removing a part for insulating resin layer 3
3b.Such as when insulating resin layer 3 is the situation of uv-hardening resin, formed in a part for insulating resin layer 3 anti-
Agent is lost, ultraviolet light is irradiated using the resist as mask, thus makes the partially hardened for not forming mask of insulating resin layer 3.
Spacer 3a and spacer 3b can be formed thereafter by the unhardened part under removal mask.Also, after resist is formed,
The part that the resist can be removed insulating resin layer 3 by blasting treatment as mask.Furthermore it is not limited to
This, such as a part for insulating resin layer 3 can be also removed by a part of irradiating laser light to insulating resin layer 3.Due to
Using laser light so not needing resist, therefore manufacturing cost can be further decreased.
Secondly, as shown in Fig. 2 (C), in the region configuring semiconductor chip 4 being clipped between spacer 3a and spacer 3b.
Such as chip attachment machine can be used etc. and across DAF configuring semiconductors chip 4 (not shown).In turn, it is configured on wiring substrate 2
Surface mounted component 9.In turn, closing line 7 is engaged in set on electronic pads set on semiconductor chip 4 and wiring layer 22
The connection gasket set.
It secondly,, will interval by using adhesive linkage 5 in a manner of overlapping semiconductor chip 4 as shown in Fig. 3 (A)
Part 3a and spacer 3b are bonded with semiconductor chip 6, to the configuring semiconductor chip 6 on spacer 3a and spacer 3b.Into
And using a plurality of semiconductor chips 6 of 5 lamination of adhesive linkage, and closing line 8 is bonded on to electricity set on semiconductor chip 6
Polar cushion and connection gasket set on wiring layer 22.
Secondly, as shown in Fig. 3 (B), by by sealing resin fill to by wiring substrate 2, spacer 3a, spacer 3b and
Sealing resin layer 10 is formed around 6 area encompassed of semiconductor chip and semiconductor chip 6.At this point, sealing resin
Viscosity is suitably adjusted according to interval or thickness of spacer 3a and spacer 3b etc..In turn, by the of wiring substrate 2
2 faces form solder ball and form external connection terminals 25.As external connection terminals 25, such as can setting signal terminal, power supply
Terminal, ground terminal etc..External connection terminals 25 are to be electrically connected at wiring layer 22 via wiring layer 23 and through-hole 24.It is external
Connection terminal 25 has solder ball.Solder ball is provided on the connection gasket of wiring layer 23.Furthermore it may also set up pad and replace weldering
Tin ball.
Thereafter, when using the situation of assembly substrate, the cutting of substrate is carried out for each semiconductor device, to divide
From for each semiconductor device.For cutting, such as the blades such as diamond blade can be used.
In turn, such as also the label that can carry out marking manufacture number etc., can be also heat-treated after the flag.Also,
Protection insulating layer or conductive shield etc. can be set on sealing resin layer 10.It is semiconductor device in present embodiment above
Manufacturer's rule explanation.
Furthermore the construction of the semiconductor device of present embodiment is not limited to construction shown in FIG. 1.To present embodiment
Another structure example of semiconductor device illustrate.Furthermore it, can for part identical with semiconductor device shown in FIG. 1
Suitably quote the explanation of semiconductor device shown in FIG. 1.
Fig. 4 is the sectional view of another structure example for the semiconductor device for indicating present embodiment.Semiconductor dress shown in Fig. 4
Set 1 be semiconductor chip 4 is embedded in a part for the closing line 7 that wiring substrate 2 is electrically connected shown in Fig. 1 (B) it is Nian Jie
The construction of layer 5.At this point, spacer 3a and spacer 3b have it is thick compared with the 1st thickness of semiconductor chip 4 and compared with from semiconductor chip
The 3rd thin thickness of height until 4 forming face to the top of closing line 7.By the way that closing line 7 is embedded in adhesive linkage 5, such as
Sealing resin is being filled when forming sealing resin layer 10, can inhibit the deforming of closing line 7, short circuit or broken string.
Fig. 5 is the sectional view of another structure example for the semiconductor device for indicating present embodiment.Semiconductor dress shown in fig. 5
It sets 1 and has semiconductor chip 14 to replace semiconductor chip 4 shown in Fig. 1 (B).Semiconductor chip 14 is that flip chip type is partly led
Body chip has the external connection terminals with solder ball.Semiconductor chip 14 is by external connection terminals and wiring base
Plate 2 is electrically connected.Semiconductor chip 14 and wiring substrate 2 are electrically connected without closing line by using flip-chip bond
7, therefore the bad connection of semiconductor chip 14 and wiring substrate 2 can be made to be difficult to generate.Also, can be increased by flip-chip bond
Add the external connection terminals quantity of semiconductor chip.Furthermore it's not limited to that for the construction of semiconductor chip, it is possible to use other
The semiconductor chip of construction.
Furthermore present embodiment is presenter as illustration, it is not intended to limit the range of invention.Such novel reality
The mode of applying is to carry out implementer with other various forms, can carry out various omissions without departing from the spirit of the invention, set
It changes or changes.Such embodiment or its variation are included in claims institute included in the range or purport of invention
In the invention of record and its range of equalization.
[explanation of symbol]
1 semiconductor device
2 wiring substrates
3 insulating resin layers
3a spacers
3b spacers
4 semiconductor chips
5 adhesive linkages
6 semiconductor chips
7 closing lines
8 closing lines
9 surface mounted components
10 sealing resin layers
14 semiconductor chips
21 insulating layers
22 wiring layers
23 wiring layers
24 through-holes
25 external connection terminals
28 solder resists
29 solder resists.
Claims (5)
1. a kind of semiconductor device, it is characterised in that include：
Wiring substrate；
1st semiconductor chip is arranged on the wiring substrate, has the 1st thickness；
1st spacer and the 2nd spacer are arranged Deng in a manner of being separated from each other across the 1st semiconductor chip in institute
It states on wiring substrate, there is the 1st thickness thickness and compared with from the forming face of the 1st semiconductor chip to the top of closing line
Until thin the 3rd thickness of height；
2nd semiconductor chip is arranged in a manner of overlapping the 1st semiconductor chip in the 1st spacer and described
On 2nd spacer；And
Sealing resin layer is set to and is led by the wiring substrate, the 1st spacer, the 2nd spacer and the described 2nd half
Around body chip area encompassed and the 2nd semiconductor chip；And
1st spacer and the 2nd spacer are made of the dielectric resin material containing high rigidity material.
2. semiconductor device according to claim 1, it is characterised in that：The wiring substrate has the resistance being arranged on surface
Solder flux, and
1st spacer and the 2nd spacer contain material identical with the solder resist.
3. semiconductor device according to claim 1 or 2, it is characterised in that also include：
Bonding coat, by the 2nd semiconductor chip and the 1st spacer and the 2nd spacer gluing；And
Closing line, is that at least part is embedded in the bonding coat, and by the 1st semiconductor chip and the wiring substrate
It is electrically connected.
4. semiconductor device according to claim 1 or 2, it is characterised in that：2nd semiconductor chip is to pass through upside-down mounting
Chip engages and is electrically connected at the wiring substrate.
5. a kind of manufacturing method of semiconductor device, it is characterised in that include：
Insulating resin layer is formed on wiring substrate；
The 1st spacer and the 2nd spacer are formed by removing a part for the insulating resin layer；
The region configuration being clipped between the 1st spacer and the 2nd spacer on the wiring substrate has the 1st thickness
1st semiconductor chip of degree；
In a manner of overlapping the 1st semiconductor chip, the 2nd half is configured on the 1st spacer and the 2nd spacer
Conductor chip；And
By being filled in sealing resin by the wiring substrate, the 1st spacer, the 2nd spacer and the described 2nd half
The sealing resin layer formed around conductor chip area encompassed and the 2nd semiconductor chip；
1st spacer and the 2nd spacer are made of the dielectric resin material containing high rigidity material, are had relatively described
The 3rd thick and thin compared with the height until the forming face to the top of closing line of the 1st semiconductor chip thickness of 1st thickness.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014050427A JP2015176906A (en) | 2014-03-13 | 2014-03-13 | Semiconductor device and method of manufacturing the same |
| JP2014-050427 | 2014-03-13 |
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| Publication Number | Publication Date |
|---|---|
| CN104916645A CN104916645A (en) | 2015-09-16 |
| CN104916645B true CN104916645B (en) | 2018-09-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410453794.7A Active CN104916645B (en) | 2014-03-13 | 2014-09-05 | The manufacturing method of semiconductor device and semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2015176906A (en) |
| CN (1) | CN104916645B (en) |
| TW (1) | TW201535668A (en) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6566625B2 (en) * | 2014-11-06 | 2019-08-28 | キヤノン株式会社 | Electronic component, electronic module, manufacturing method thereof, and electronic device |
| JP6523999B2 (en) * | 2016-03-14 | 2019-06-05 | 東芝メモリ株式会社 | Semiconductor device and method of manufacturing the same |
| JP6586036B2 (en) * | 2016-03-15 | 2019-10-02 | 東芝メモリ株式会社 | Manufacturing method of semiconductor device |
| TWI662671B (en) | 2016-03-24 | 2019-06-11 | 日商新川股份有限公司 | Joining device |
| JP2017204511A (en) * | 2016-05-10 | 2017-11-16 | ソニー株式会社 | Semiconductor device, semiconductor device manufacturing method and electronic apparatus |
| US20180090466A1 (en) * | 2016-09-29 | 2018-03-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| KR101751972B1 (en) * | 2016-12-26 | 2017-08-01 | (주)이녹스첨단소재 | FOD adhesive film of semiconductor controller embedding type and Semiconductor package |
| JP7034706B2 (en) * | 2017-12-27 | 2022-03-14 | キオクシア株式会社 | Semiconductor device |
| JP2019153619A (en) | 2018-02-28 | 2019-09-12 | 東芝メモリ株式会社 | Semiconductor device |
| JP2020021908A (en) * | 2018-08-03 | 2020-02-06 | キオクシア株式会社 | Semiconductor device and method for manufacturing the same |
| JP2020025022A (en) * | 2018-08-07 | 2020-02-13 | キオクシア株式会社 | Semiconductor device and manufacturing method for the same |
| JP2020053655A (en) | 2018-09-28 | 2020-04-02 | キオクシア株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JP2020155559A (en) | 2019-03-19 | 2020-09-24 | キオクシア株式会社 | Semiconductor device |
| WO2020217405A1 (en) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | Method for manufacturing semiconductor device having dolmen structure, method for manufacturing support piece, and laminate film for support piece formation |
| WO2020217397A1 (en) | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | Method for producing semiconductor device having dolmen structure, method for producing supporting pieces, and multilayer film |
| SG11202110111YA (en) * | 2019-04-25 | 2021-11-29 | Showa Denko Materials Co Ltd | Semiconductor device having dolmen structure and method for manufacturing same |
| WO2020217411A1 (en) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | Semiconductor device having dolmen structure and method for manufacturing same, and laminated film for forming support piece and method for manufacturing same |
| JP7247733B2 (en) * | 2019-04-25 | 2023-03-29 | 株式会社レゾナック | Manufacturing method of semiconductor device having dolmen structure |
| WO2020217394A1 (en) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | Semiconductor device having dolmen structure and method of manufacturing same and laminate film for forming support piece and method of manufacturing same |
| WO2020217401A1 (en) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | Semiconductor device having dolmen structure, method for manufacturing same, laminated film for forming support piece, and method for manufacturing same |
| CN113632225A (en) * | 2019-04-25 | 2021-11-09 | 昭和电工材料株式会社 | Semiconductor device having stone support structure, method for manufacturing the same, method for manufacturing support sheet, and laminated film for forming support sheet |
| JP2021015922A (en) * | 2019-07-16 | 2021-02-12 | キオクシア株式会社 | Semiconductor device and method of manufacturing the same |
| JP2021034606A (en) * | 2019-08-27 | 2021-03-01 | キオクシア株式会社 | Semiconductor device and manufacturing method of the same |
| JP2021044362A (en) * | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | Semiconductor device |
| JP7293056B2 (en) * | 2019-09-12 | 2023-06-19 | キオクシア株式会社 | Semiconductor device and its manufacturing method |
| JP2021048195A (en) * | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | Semiconductor device and method for manufacturing the same |
| JP2021129083A (en) * | 2020-02-17 | 2021-09-02 | キオクシア株式会社 | Semiconductor device and method for manufacturing the same |
| JP7413102B2 (en) * | 2020-03-17 | 2024-01-15 | キオクシア株式会社 | semiconductor equipment |
| CN116210358A (en) * | 2020-08-11 | 2023-06-02 | 株式会社力森诺科 | Semiconductor device and method for manufacturing the same |
| JP2022113250A (en) | 2021-01-25 | 2022-08-04 | キオクシア株式会社 | Semiconductor device |
| TWI818428B (en) * | 2022-01-27 | 2023-10-11 | 友達光電股份有限公司 | Communication device, communication component and method of manufacturing the communication component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017785A (en) * | 2006-02-10 | 2007-08-15 | 矽品精密工业股份有限公司 | Semiconductor stack structure and its making method |
| CN103178036A (en) * | 2011-12-20 | 2013-06-26 | 株式会社东芝 | Semiconductor and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013197341A (en) * | 2012-03-21 | 2013-09-30 | Toshiba Corp | Stacked semiconductor device and method of manufacturing the same |
-
2014
- 2014-03-13 JP JP2014050427A patent/JP2015176906A/en not_active Abandoned
- 2014-07-02 TW TW103122855A patent/TW201535668A/en unknown
- 2014-09-05 CN CN201410453794.7A patent/CN104916645B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017785A (en) * | 2006-02-10 | 2007-08-15 | 矽品精密工业股份有限公司 | Semiconductor stack structure and its making method |
| CN103178036A (en) * | 2011-12-20 | 2013-06-26 | 株式会社东芝 | Semiconductor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201535668A (en) | 2015-09-16 |
| JP2015176906A (en) | 2015-10-05 |
| CN104916645A (en) | 2015-09-16 |
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