CN108242431A - A kind of package substrate and chip packing-body - Google Patents
A kind of package substrate and chip packing-body Download PDFInfo
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- CN108242431A CN108242431A CN201711499147.XA CN201711499147A CN108242431A CN 108242431 A CN108242431 A CN 108242431A CN 201711499147 A CN201711499147 A CN 201711499147A CN 108242431 A CN108242431 A CN 108242431A
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- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
This application discloses a kind of package substrate and chip packing-bodies, are related to chip encapsulation technology field.The package substrate includes at least one the first pad for being used to be connected with the metal salient point on chip, at least one the second pad for being interconnected with connection terminal, wherein, the first pad and the second pad are located at the same face of package substrate.By the above-mentioned means, in subsequent chip package process, chip attachment and setting connection terminal can be carried out at the same time primary welding, the probability of substrate deformation when being repeatedly heated can be reduced；Reduce packaging technology, improve packaging technology efficiency, improve equipment capacity, reduce packaging cost.
Description
Technical field
This application involves chip encapsulation technology field, more particularly to a kind of package substrate and chip packing-body.
Background technology
With the increase of integrated circuit integrated level, the encapsulation technology of chip is also more and more diversified, because of flip-chip skill
Art can shorten the interconnection length in encapsulation, and then can better adapt to highly integrated growth requirement, extensively should at present
For chip package field.
Please refer to Fig.1 and Fig. 2, Fig. 1 be chip packing-body in the prior art structure diagram, Fig. 2 is in the prior art
The structure diagram of package substrate.The reverse installation process flow of current chip is generally required fills out by chip mill stroke, upside-down mounting, bottom
It fills, plastic packaging, printing, plant the encapsulation that chip is completed after ball, cutting, the series of processes such as visual examination, obtain chip packing-body 10,
There are bottom glue-line 101, plastic packaging layer 102 etc. in chip packing-body 10.
Present inventor is had found in long-term R＆D process in this kind of technological process, in package substrate 20
The pad 201 being connected with metal salient point is located at upper surface of base plate, is located at substrate with the pad 202 of connection terminal cooperation interconnection
Lower surface.Therefore when carrying out chip package, chip welding and plant ball need substep to complete, and also needed to before ball is planted to chip
Underfill and plastic packaging are carried out, substrate can be made to be subjected to primary height in reflow soldering, underfill and plastic packaging three process in this way
Temperature flows back and toasts twice, easily causes substrate deformation, this will all have shadow for subsequent printing, the plant processes such as ball and cutting
It rings.And substrate deform upon after the risk that gets stuck can also increase very much, the yield of product, which also will appear, significantly to be declined.
Invention content
Mainly solving the technical problems that providing a kind of package substrate and chip packing-body, having ready conditions can improve the application
Packaging technology efficiency improves equipment capacity, reduces packaging cost.
In order to solve the above technical problems, the technical solution that the application uses is：A kind of package substrate, the envelope are provided
Fill substrate include it is at least one be used for on chip metal salient point be connected the first pad, it is at least one be used for connecting
Second pad of terminal interconnection, wherein, the first pad and the second pad are located at the same face of package substrate.
Wherein, the surface of package substrate has groove, and the first pad is set to the groove floor, and second pad is set
It is placed in the package substrate surface on the outside of the groove.
Wherein, the depth of the groove matches the thickness of the chip.
Wherein, first pad is identical with the number of second pad, first pad and second pad
By the corresponding electrical connection of connecting line, wherein, the connecting line specifically includes two and connects perpendicular to the first of the substrate surface
Wiring and the second connecting line and a third connecting line for being parallel to the substrate surface, described in first connecting line connection
First pad, second connecting line connect second pad, and the third connecting line connects first connecting line and institute
State the second connecting line.
Wherein, first pad and second pad are copper pad.
In order to solve the above technical problems, another technical solution that the application uses is：A kind of chip packing-body, institute are provided
It states chip packing-body and includes package substrate, the chip being packaged on package substrate and the connection terminal being set on package substrate,
Wherein, chip is located at the same face of package substrate with connection terminal.
Wherein, the package substrate includes at least one the first weldering being used for the metal salient point mating connection on chip
Disk, at least one the second pad for being interconnected with the connection terminal, wherein, first pad, the connection terminal, institute
State the same face that the second pad is located at the package substrate.
Wherein, the surface of the package substrate has groove, and first pad is set to the groove floor, institute
Chip package is stated in the groove, second pad is set to the package substrate surface on the outside of the groove.
Wherein, first pad is identical with the number of second pad, first pad and second pad
By the corresponding connection of connecting line, wherein, the connecting line specifically includes two the first connections perpendicular to the substrate surface
Line and the second connecting line and a third connecting line for being parallel to the substrate surface, first connecting line connection described the
One pad, second connecting line connect second pad, and the third connecting line connects first connecting line and described
Second connecting line.
Wherein, the flip-chip is on the substrate.
In order to solve the above technical problems, another technical solution that the application uses is：A kind of chip packing-body is provided
Preparation method, the method includes：Package substrate and chip are provided, package substrate includes at least one be used for and the gold on chip
Belong to salient point be connected the first pad, at least one the second pad for being interconnected with connection terminal, wherein, the first pad and
Second pad is located at the same face of package substrate；Chip attachment on package substrate, wherein, the metal salient point on chip and first
Pad is connected, and connection terminal is placed on the second pad；Package substrate is welded, so that chip and the first weldering
Disk, connection terminal and the second pad solder interconnect, and obtain chip package substance.
Wherein, the offer package substrate, the package substrate include at least one be used for and the metal salient point on chip
The first pad, at least one the second pad for being interconnected with connection terminal being connected include：Substrate carrier is provided；Institute
State be molded on support plate, overlay film, exposure, development, copper facing make to form connecting line, the connecting line is corresponding for being electrically connected
First pad and second pad；It is molded again, overlay film, exposure, development, copper facing make to form first weldering
Disk and second pad, wherein, first pad is located at the same face of the package substrate with second pad.
Wherein, it is described be molded on support plate, overlay film, exposure, development, copper facing make to be formed after connecting line and include：
It is made by injection, overlay film, exposure, development, etching and forms the groove, wherein, the depth of the groove matches the chip
Thickness.
The chip attachment includes on the package substrate：The flip-chip is on the package substrate.
The chip attachment on the package substrate, wherein, metal salient point and first pad on the chip
It is connected, and connection terminal is placed on second pad and is included：It is set on the metal salient point or first pad
Fluxing agent layer；Fluxing agent layer is set on the connection terminal or second pad.
Fluxing agent layer is set on the metal salient point or first pad；The connection terminal or second pad
Upper setting fluxing agent layer includes：The scaling powder layer is formed by way of impregnating, printing coating or spraying.
It is described that package substrate is welded so that the chip and first pad, the connection terminal with it is described
Second pad solder interconnects, and obtains chip package substance and includes：Reflow soldering is carried out to the package substrate, so that described
Chip is interconnected with first pad, the connection terminal and second pad solder, obtains chip package substance.
It is described that reflow soldering is carried out to package substrate so that the chip and first pad, the connection terminal with
The second pad solder interconnection, obtains chip package substance and includes：The chip is applied during welding is formed and is pressed
Power, to press the chip and the substrate.
It is described that package substrate is welded so that the chip and first pad, the connection terminal with it is described
Second pad solder interconnects, and obtains chip package substance and includes：Directly the chip package substance is carried out being cut to core
Piece packaging body.
It is described that chip package substance further included after being cut to chip packing-body：To the chip packing-body
Carry out laser printing.
The advantageous effect of the application is：Be different from the situation of the prior art, package substrate provided herein include with
The first pad that metal salient point on chip is connected, the second pad with connection terminal interconnection, and the first pad and second
Pad is located at the same face of package substrate；By the way that the first pad and the second pad to be arranged on to the same face of package substrate, rear
In continuous chip package process, primary welding can be carried out at the same time by chip attachment and setting connection terminal by having ready conditions, and can be dropped
Low substrate because repeatedly be heated due to deformation probability；Reduce packaging technology, improve packaging technology efficiency, improve equipment capacity, reduce
Packaging cost.
Description of the drawings
Fig. 1 is a kind of structure diagram of chip packing-body in the prior art.
Fig. 2 is a kind of structure diagram of package substrate in the prior art.
Fig. 3 is the cross-sectional view of the application package substrate first embodiment.
Fig. 4 is the process flow diagram of one embodiment of preparation method of the application package substrate.
Fig. 5 is the process flow diagram of one embodiment of preparation method of the application package substrate.
Fig. 6 is the process flow diagram of one embodiment of preparation method of the application package substrate.
Fig. 7 is the flow diagram of the preparation method first embodiment of the application chip packing-body.
Fig. 8 is the structure diagram of the application chip packing-body first embodiment.
Specific embodiment
Purpose, technical solution and effect to make the application is clearer, clear and definite, and develop simultaneously embodiment pair referring to the drawings
The application is further described.
The application provides a kind of package substrate, which may at least apply in chip package process, the encapsulation
Substrate includes the first pad being connected with the metal salient point on chip, the second pad with connection terminal interconnection, and first
Pad and the second pad are located at the same face of package substrate.It, can be by chip when the package substrate is used to carry out chip package
Attachment with setting connection terminal be carried out at the same time primary welding, can reduce substrate because repeatedly be heated due to deformation probability；Reduction envelope
Dress technique improves packaging technology efficiency, improves equipment capacity, reduces packaging cost.
Specifically, referring to Fig. 3, Fig. 3 is the cross-sectional view of the application package substrate first embodiment.At this
In embodiment, package substrate 30 include it is at least one be used for on chip metal salient point be connected the first pad 301,
At least one the second pad 302 for being interconnected with connection terminal, wherein, the first pad 301 and the second pad 302 are located at encapsulation
The same face of substrate 30.
To accommodate chip in chip package, the surface of package substrate 30 also has groove 303, therefore the depth of groove 303
Degree answers the thickness of matching chip.Wherein, the first pad 301 is set to 303 bottom surface of groove, for matching with the metal salient point on chip
Close connection；Second pad 302 is set to the package substrate surface in 303 outside of groove, for setting connection terminal, and then realizes envelope
Cartridge chip is electrically connected with other elements.
Wherein, connection terminal is to be electrically connected for that will encapsulate chip with other elements realization, such as in chip stack package
When, upper lower package body is connected, therefore the pin of I/0 for needing to stack need to be led to the second pad 302 using connection terminal, it is real
Now it is electrically connected with connection terminal.In one embodiment, the pin being connect with the first pad 301 is required for drawing and connect, because
This, 302 numbers of the first pad 301 and the second pad are identical, and the first pad 301 and the second pad 302 are opposite by connecting line 304
It should be electrically connected.Connecting line 304 specifically includes two the first connecting lines 3041 and the second connecting line 3042 perpendicular to substrate surface,
And one be parallel to substrate surface third connecting line 3043, wherein, the first connecting line 3041 connects the first pad 301, and second connects
Wiring 3042 connects the second pad 302, and third connecting line 3043 connects the first connecting line 3041 and the second connecting line 3042.
To prepare above-mentioned package substrate, the application also provides a kind of preparation method of package substrate.Please refer to Fig. 4-
Fig. 6, Fig. 4-Fig. 6 are the process flow diagrams of one embodiment of preparation method of the application package substrate.Preferably
In, it is illustrated by taking wherein two groups of pads as an example, as Figure 4-Figure 6, wherein, the first pad 41 and the second pad 44 pass through
One connecting line 45, the second connecting line 46, third connecting line 47 are connected；First pad 42 is connect with the second pad 43 by first
Line 48, the second connecting line 49, third connecting line 410 are connected, and specific preparation process is as follows：
Step 1：Make the first sandwich circuit.
Substrate carrier 401 is provided；It is molded to obtain the first injection molded layers 402 on support plate 401, with the first injection molded layers 402
The first sandwich circuit making is carried out for matrix.
Specifically, in 402 upper cover dry film 403 of the first injection molded layers, through exposure and development, first layer line pattern is etched, plated
Copper forms the first sandwich circuit, wherein, the first sandwich circuit includes third connecting line 47.
Step 2：Make the second sandwich circuit.
It is molded on the first sandwich circuit, obtains the second injection molded layers 404, the is carried out for matrix with the second injection molded layers 404
Two sandwich circuits make.
Specifically, in 404 upper cover dry film of the second injection molded layers, through exposure and development, second layer line pattern, copper facing are etched
It makes and forms the second sandwich circuit, wherein, the first segment 405 of the second sandwich circuit including the first connecting line 45, the second connecting line 46
First segment 406 and third connecting line 410, and the first segment 406 of the first segment 405 of the first connecting line 45, the second connecting line 46 should
It is connected with the third connecting line 47 of the first sandwich circuit.Because the first pad is located at bottom portion of groove, there is difference in height with the second pad,
It is different perpendicular to the first connecting line of substrate surface and the height of the second connecting line from the second pad so to connect the first pad,
Therefore, when making the first connecting line and the second connecting line, it is possible to two sections or more sections can be divided to complete.
Step 3：Make third sandwich circuit.
It is molded on the second sandwich circuit, obtains third injection molded layers 407, the is carried out for matrix with third injection molded layers 407
Three sandwich circuits make.
Specifically, in 407 upper cover dry film of third injection molded layers, through exposure and development, third layer line pattern, copper facing are etched
Making forms third sandwich circuit.Wherein, third sandwich circuit includes the first pad 41 and 42, the second pad 43 and 44, the second connection
Line 46 and 49, the second segment of the first connecting line 45, the second segment of the second connecting line 46.
Wherein, should be corresponding with the second sandwich circuit when carrying out mask exposure, the particularly second segment of the first connecting line 45,
The figure of the second segment of second connecting line 46 should with the first segment of the first connecting line 45 obtained, the second connecting line 46 first
Section alignment, so that the second segment of the first connecting line 45 obtained, the in the second segment and the second sandwich circuit of the second connecting line 46
The 406 perpendicular connection of first segment of the first segment 405 of one connecting line 45, the second connecting line 46；Second connecting line 46 and 49 is distinguished
It is connected with third connecting line 410.
Wherein, when making third layer line pattern, the light transmittance for regulating and controlling different zones on mask plate can be simultaneously first
Groove 411 is etched in the graphics field of pad 41 and 42, and the first pad 41 and 42 to be formed is made to be located at the bottom of groove 411
Portion.When progress copper facing operates to form the first pad 41 and 42, mask is answered to block and avoids groove location.
So far, complete first pad, the second pad and its connecting line is made, then bond pad surface is handled, applies
Machine aided weldering protective layer (OSP) is covered with, support plate, molding, inspection is finally gone to obtain package substrate 40.
In other embodiments the first connecting line, the second connecting line, third connecting line material be not limited to copper, can also
It is other conductive materials.It is also not necessarily limited to the preparation of three sandwich circuits simultaneously, a point multilayer should may be selected and prepare according to the quantity of pad.
Using above-mentioned package substrate carry out chip package when, can reduce substrate because repeatedly be heated due to deformation probability；
Reduce packaging technology, improve packaging technology efficiency, improve equipment capacity, reduce packaging cost.On this basis, the application also carries
For a kind of preparation method of chip packing-body, referring to Fig. 7, the preparation method first that Fig. 7 is the application chip packing-body is implemented
The flow diagram of mode, as shown in fig. 7, in this embodiment, the preparation method of potted element includes the following steps：
S701：Package substrate and chip are provided.
Wherein, package substrate includes at least one the first pad, extremely for being used to be connected with the metal salient point on chip
Few second pad for being interconnected with connection terminal, wherein, the first pad and the second pad are located at the package substrate
The same face.
Specifically, which can be above-mentioned package substrate, and concrete structure please refers to above-mentioned related envelope to preparation method
The description of substrate embodiment is filled, details are not described herein.The substrate can be provided by customization by substrate manufacturer or chip
Encapsulation manufacturer voluntarily prepares according to above-mentioned preparation method.
S702：By chip attachment on package substrate, wherein, metal salient point and the first pad on chip are connected,
And connection terminal is placed on the second pad.
Specifically, in one embodiment, substrate can be the special substrate for adapting to certain chip, pad and metal
The quantity of salient point is consistent, and is correspondingly arranged；In other embodiments, substrate can also be used for chip package preparation process
In universal type basal plate, and multiple chips can be assembled on substrate simultaneously (these chips can be set in side-by-side fashion, can also
Set in a stacked fashion), to carry out fast packing to multiple chips simultaneously.Therefore the number of pads on substrate can be more than core
The quantity of the metal salient point of on piece, as long as can ensure that the metal salient point on chip has the corresponding matching connection of pad i.e.
It can.
Because package substrate provided herein the first pad and the second pad substrate the same face, therefore by core
When piece is mounted with substrate, while connection terminal can be placed on the second pad；With can be by once welding, while realize core
Piece and the first pad, connection terminal and the second pad solder interconnect.
S703：Package substrate is welded, so that chip and the first pad, connection terminal and the second pad solder are mutual
Even, chip package substance is obtained.
It is alternatively possible to be welded by way of being heated at reflux, other mode of heatings can also be selected to be welded.
It in one embodiment, can be by impregnating, printing before chip and substrate are mounted to improve the reliability welded
It brushes the mode covered or sprayed and scaling powder layer is formed on metal salient point.Can also pressure be applied to chip in the welding process,
To press chip and substrate, the stability of welding is improved.In other embodiments, scaling powder can also be coated in substrate-side
The first pad on.Similarly, scaling powder layer can also be set on connection terminal or the second pad.
Using the preparation method of chip packing-body provided herein, after the completion of welding, because of connection terminal and core
Piece is soldered simultaneously, and in substrate homonymy, and therefore, gained chip packing-body can no longer need to carry out underfill and plastic packaging,
Reduce packaging technology, while reducing equipment investment, also shorten the production cycle of product.Chip will be directly exposed in air simultaneously
In, better heat-radiation effect.
Because no longer needing to carry out underfill and plastic package process, therefore can be directly to chip package original after the completion of welding
Body carries out being cut to chip packing-body monolithic.Simultaneously laser printing process can also be adjusted to cutting pick up piece process it
Afterwards.In traditional handicraft, laser printing is printed in the form of whole substrate, and information, pattern are printed upon the positive modeling of product
It seals on body.And after adopting new technology, product will be printed in the form of single.Since the package substrate is exactly to use plastic packaging material
It manufactures, so product information, pattern are printed upon on the plastic-sealed body at the product back side.
Therefore, chip packing-body can be efficiently prepared using above-mentioned preparation method, referring to Fig. 8, Fig. 8 is the application core
The structure diagram of piece packaging body first embodiment.The application also provides a kind of chip packing-body 80,80 envelope of chip packing-body
Substrate 801, the chip 802 being packaged on package substrate 801 and the connection terminal 803 being set on package substrate 801 are filled,
In, chip 802 is located at the same face of package substrate 801 with connection terminal 803.
The substrate that wherein package substrate 801 is provided by the above embodiment, concrete structure and preparation method please refer to
State the description of embodiment.The chip packing-body 80 is made in preparation process using above-mentioned preparation method, is specifically prepared
Journey please refers to the description of the above embodiment, and details are not described herein.
Above scheme, package substrate provided herein include the be connected with the metal salient point on chip first weldering
Disk, the second pad with connection terminal interconnection, and the first pad and the second pad are located at the same face of package substrate；By by
One pad and the second pad are arranged on the same face of package substrate, can be by chip attachment in subsequent chip package process
With setting connection terminal be carried out at the same time primary welding, can reduce substrate because repeatedly be heated due to deformation probability；Reduction encapsulation work
Skill improves packaging technology efficiency, improves equipment capacity, reduces packaging cost.
The foregoing is merely presently filed embodiments, not thereby limit the scope of the claims of the application, every to utilize this
It is relevant to be directly or indirectly used in other for the equivalent structure or equivalent flow shift that application specification and accompanying drawing content are made
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of package substrate, which is characterized in that the package substrate includes at least one be used for and the metal salient point on chip
The first pad, at least one the second pad for being interconnected with connection terminal being connected, wherein, first pad and institute
State the same face that the second pad is located at the package substrate.
2. package substrate according to claim 1, which is characterized in that the surface of the package substrate has groove,
First pad is set to the groove floor, and second pad is set to the package substrate table on the outside of the groove
Face.
3. package substrate according to claim 2, which is characterized in that the depth of the groove matches the thickness of the chip
Degree.
4. package substrate according to claim 1, which is characterized in that the number of first pad and second pad
It is identical, first pad and second pad by the corresponding electrical connection of connecting line, wherein, the connecting line specifically includes
Two perpendicular to the first connecting line of the substrate surface and the second connecting line and a third for being parallel to the substrate surface
Connecting line, first connecting line connect first pad, and second connecting line connects second pad, the third
Connecting line connects first connecting line and second connecting line.
5. package substrate according to claim 1, which is characterized in that first pad is brazing with second pad
Disk.
6. a kind of chip packing-body, which is characterized in that the chip packing-body includes package substrate, is packaged in the package substrate
On chip and the connection terminal that is set on the package substrate, wherein, the chip is located at described with the connection terminal
The same face of package substrate.
7. chip packing-body according to claim 6, which is characterized in that the package substrate include it is at least one be used for
The first pad, at least one the second pad for being interconnected with the connection terminal that metal salient point on chip is connected,
Wherein, first pad, the connection terminal, second pad are located at the same face of the package substrate.
8. chip packing-body according to claim 7, which is characterized in that the surface of the package substrate has recessed
Slot, first pad are set to the groove floor, and in the groove, second pad is set to the chip package
The package substrate surface on the outside of the groove.
9. chip packing-body according to claim 7, which is characterized in that of first pad and second pad
Number is identical, first pad and second pad by the corresponding connection of connecting line, wherein, the connecting line specifically includes
Two perpendicular to the first connecting line of the substrate surface and the second connecting line and a third for being parallel to the substrate surface
Connecting line, first connecting line connect first pad, and second connecting line connects second pad, the third
Connecting line connects first connecting line and second connecting line.
10. chip packing-body according to claim 6, which is characterized in that the flip-chip is on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711499147.XA CN108242431A (en) | 2017-12-29 | 2017-12-29 | A kind of package substrate and chip packing-body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711499147.XA CN108242431A (en) | 2017-12-29 | 2017-12-29 | A kind of package substrate and chip packing-body |
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| Publication Number | Publication Date |
|---|---|
| CN108242431A true CN108242431A (en) | 2018-07-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711499147.XA Pending CN108242431A (en) | 2017-12-29 | 2017-12-29 | A kind of package substrate and chip packing-body |
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| Country | Link |
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| CN (1) | CN108242431A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951797A (en) * | 2021-01-27 | 2021-06-11 | 维沃移动通信有限公司 | Fingerprint module, electronic equipment and fingerprint module processing method |
| CN114677908A (en) * | 2020-12-25 | 2022-06-28 | 华为技术有限公司 | Display module assembly, display screen and electronic equipment |
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| US6272020B1 (en) * | 1997-10-16 | 2001-08-07 | Hitachi, Ltd. | Structure for mounting a semiconductor device and a capacitor device on a substrate |
| JP2004311598A (en) * | 2003-04-03 | 2004-11-04 | Ngk Spark Plug Co Ltd | Substrate with reinforcement, wiring board consisting of semiconductor element, reinforcement and substrate |
| CN1819173A (en) * | 2005-01-31 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device |
| JP2017084886A (en) * | 2015-10-26 | 2017-05-18 | 京セラ株式会社 | Wiring board and mounting structure of semiconductor element using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6272020B1 (en) * | 1997-10-16 | 2001-08-07 | Hitachi, Ltd. | Structure for mounting a semiconductor device and a capacitor device on a substrate |
| JP2004311598A (en) * | 2003-04-03 | 2004-11-04 | Ngk Spark Plug Co Ltd | Substrate with reinforcement, wiring board consisting of semiconductor element, reinforcement and substrate |
| CN1819173A (en) * | 2005-01-31 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device |
| JP2017084886A (en) * | 2015-10-26 | 2017-05-18 | 京セラ株式会社 | Wiring board and mounting structure of semiconductor element using the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114677908A (en) * | 2020-12-25 | 2022-06-28 | 华为技术有限公司 | Display module assembly, display screen and electronic equipment |
| CN112951797A (en) * | 2021-01-27 | 2021-06-11 | 维沃移动通信有限公司 | Fingerprint module, electronic equipment and fingerprint module processing method |
| CN112951797B (en) * | 2021-01-27 | 2022-10-14 | 维沃移动通信有限公司 | Fingerprint module, electronic equipment and fingerprint module processing method |
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Application publication date: 20180703 |