JP5813335B2 - Lead frame, semiconductor device, lead frame manufacturing method, and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a lead frame member and a manufacturing method thereof.

  In recent years, in order to cope with downsizing and high density of electronic devices, high density and high functionality of semiconductor components are required, and downsizing and light weight of semiconductor packages are rapidly progressing. In this trend, BGA (Ball Grid Array) and LGA (Land Grid Array) and other area array types, QFN (Quad Flat Non-leaded package) types and CSP (Chip Size Package) type resin-encapsulated types Semiconductor devices have been put into practical use.

  As a manufacturing method of this type of semiconductor device, a process of mounting a semiconductor element on a die pad portion of a lead frame (die bonding), and a process of electrically connecting an electrode of the semiconductor element and a lead of the lead frame by a bonding wire (Wire bonding). Furthermore, the process (molding) which seals a semiconductor element, a bonding wire, etc. with sealing resin, the process (dicing) etc. which divide | segment a lead frame into each package (semiconductor device) unit are included. Examples of the molding method include an individual molding method in which a sealing resin is applied to each individual semiconductor element, and a batch molding method in which resin sealing is performed in units of a plurality of semiconductor elements. However, in recent years, the bulk molding method has become mainstream due to the demand for cost reduction.

  However, in such a batch molding method, in order to prevent leakage of the sealing resin to the back surface of the lead frame, it is necessary to perform molding in a state where an adhesive tape is applied to the entire back surface of the lead frame. For this reason, there is a problem that the productivity is lowered and the cost is increased as much as the adhesive tape is applied.

  Therefore, as a method of eliminating the need for the adhesive tape, an insulating material for preventing the flow of the sealing resin is formed in the opening that penetrates between the front and back surfaces of the lead frame formed when the frame structure of the lead frame is formed. A method of embedding resin has been proposed (see, for example, Patent Documents 1 and 2).

JP 2003-309241 A JP 2003-309242 A

  However, since the thickness of the lead frame is as thin as about 100 to 500 μm, the area where the resin embedded in the through hole and the lead frame are in contact is small. For this reason, if the lead frame undergoes a slight bending deformation or heat or force is applied to the lead frame in the process after resin embedding (for example, plating process or mounting process), the embedded resin can be easily removed from the lead frame. There is a problem of peeling.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a lead frame, a lead frame manufacturing method, a semiconductor device, and a semiconductor capable of suppressing peeling of a resin embedded in an opening. It is to provide a method for manufacturing an apparatus.

According to one aspect of the present invention, there is provided a lead frame and a section bar, the unit lead frame having a supported die pad and lead by the section bar is plural continuously provided, said section bars and the die pad and the An opening for defining a lead, a recess formed on the lower surface of the section bar, a side surface of the die pad or at least a part of an inner wall surface of the opening that is a side surface of the lead, and only an inner wall surface of the recess. A rough surface plating layer having a roughened surface, and an insulating resin layer embedded in at least a part of the opening and the recess so as to be in contact with the rough surface plating layer.

  According to this configuration, by forming a rough plating layer on the inner wall surface of the opening, the contact area between the inner wall surface (rough surface plating layer) and the resin layer is greater than when the inner wall surface is a smooth surface. Will be increased. Thereby, the adhesiveness of the inner wall surface (rough surface plating layer) of an opening part and a resin layer can be improved. Therefore, occurrence of peeling of the resin layer from the opening can be suitably suppressed.

According to one aspect of the present invention, a manufacturing method of a lead frame and a section bar, the unit lead frame having a supported die pad and lead by the section bar is plural continuously provided, said section bars and the Forming a substrate frame by forming an opening for defining the die pad and the lead in the conductive substrate, and forming a substrate frame by forming a recess on a lower surface of the conductive substrate serving as the section bar ; A roughening step of forming a rough surface plating layer having a roughened surface only on at least a part of the inner wall surface of the opening and the inner wall surface of the recess, which is the side surface or the side surface of the lead; an insulating resin so as to be in contact with the layer, having a resin embedding step embeds into at least a portion with the recess of the opening.

  According to this configuration, by forming the rough plating layer on the inner wall surface of the opening, the inner wall surface (rough surface plating layer) and the resin embedded in the opening so as to be in contact with the rough plating layer The contact area is increased as compared with the case where the inner wall surface is a smooth surface. For this reason, the adhesiveness of the inner wall surface (rough surface plating layer) of an opening part and a resin layer can be improved. Therefore, occurrence of peeling of the resin layer from the opening can be suitably suppressed.

  According to one aspect of the present invention, it is possible to suppress the peeling of the resin embedded in the opening.

(A) is a schematic plan view showing the lead frame of the first embodiment, (b) is an enlarged plan view of a region R shown in FIG. 1 (a), and (c) is a lead shown in FIG. 1 (b). It is AA schematic sectional drawing of a flame | frame. (A)-(g) is a schematic sectional drawing which shows the manufacturing method of the lead frame of 1st Embodiment. It is a perspective view which shows schematic structure of a plating processing apparatus. It is a graph which shows the relationship between the surface roughness of a plating layer, and cup shear strength. It is a schematic sectional drawing which shows the lead frame of a modification. It is a schematic plan view which shows the lead frame of 2nd Embodiment. (A)-(h) is a schematic sectional drawing which shows the manufacturing method of the lead frame of 2nd Embodiment. (A) is an enlarged plan view showing the lead frame of the third embodiment, and (b) is a schematic BB cross-sectional view of the lead frame shown in FIG. 8 (a). (A)-(e) is a schematic sectional drawing which shows the manufacturing method of the lead frame of 3rd Embodiment. (A)-(e) is a schematic sectional drawing which shows the manufacturing method of the lead frame of 3rd Embodiment. It is a schematic sectional drawing which shows the lead frame of a modification. It is a schematic sectional drawing which shows the semiconductor device of 4th Embodiment. (A)-(d) is a schematic sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. (A)-(c) is a schematic sectional drawing which shows the semiconductor device of a modification.

Hereinafter, each embodiment will be described with reference to the accompanying drawings. Note that the attached drawings are for explaining the outline of the structure and do not represent the actual size.
(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.

  A lead frame 1 shown in FIG. 1 basically includes a substrate frame 2 used as a QFN substrate. As the material of the substrate frame 2, for example, copper (Cu), an alloy based on Cu, iron-nickel (Fe-Ni), an alloy based on Fe-Ni, or the like can be used.

  As shown in FIG. 1A, a plurality (three in the figure) of mold cavities 3 are separately defined on one surface of the substrate frame 2. Each mold cavity 3 is formed with a plurality of unit lead frames 10 connected in a matrix (5 × 5 in the figure). The unit lead frame 10 is finally cut out as an individual semiconductor device (package) with a semiconductor element mounted thereon. When assembling the semiconductor device, after the semiconductor element is mounted on each unit lead frame 10, resin sealing is performed for each mold cavity 3 by a batch molding method.

  As shown in FIG. 1B, the unit lead frame 10 includes an inner frame (hereinafter also referred to as a section bar) 11 formed in a lattice shape, and four support bars 12 extending from the section bar 11. And a plurality of comb-shaped leads 14 extending from the section bar 11 toward the die pad 13. The lead 14 is provided around the die pad 13. As shown in FIG. 1C, the lead 14 includes an inner lead 14A that is electrically connected to an electrode terminal of a semiconductor element to be mounted and an outer lead that is electrically connected to wiring of a mounting board such as a mother board. And leads (external connection terminals) 14B. The outer lead 14B is narrower than the inner lead 14A in sectional view. The die pad 13 has a back surface (lower surface in FIG. 1 (c)) narrower than a front surface (upper surface in FIG. 1 (c)). In addition, although illustration is abbreviate | omitted, in planar view, the back surface of the die pad 13 is smaller than the surface.

  The unit lead frame 10 is formed with an opening 15 that defines the section bar 11, the support bar 12, the die pad 13, and the leads 14. The opening 15 is formed so as to penetrate in the thickness direction of the substrate frame 2. Therefore, the inner wall surface 15 </ b> A of the opening 15 is a surface in the thickness direction of the substrate frame 2, that is, the side surface of the die pad 13 or the side surface of the lead 14. A recess 16 is formed on the back surface (lower surface in the drawing) of the section bar 11.

  On the inner wall surface 15 </ b> A of the opening 15 and the inner wall surface 16 </ b> A of the recess 16, a rough surface plating layer 17 having a roughened surface is formed. Moreover, the said rough surface plating layer 17 can be comprised from the laminated body which consists of any one of Ni, chromium (Cr), Fe, or those alloys, or two or more of these, for example. The roughened surface (surface) 17A of the rough plating layer 17 is formed in a fine uneven shape. The roughness of the roughened surface 17A is adjusted to, for example, a surface roughness Ra value of 100 nm or more by adjusting the composition, current density, etc. of the plating solution used when the plating layer 17 is formed by electrolytic plating. It is set to be. Here, the surface roughness Ra is a kind of numerical value representing the surface roughness, and is called arithmetic average roughness. Specifically, the absolute value of the height changing in the measurement region is expressed as an average line. Measured from a certain surface and arithmetically averaged.

  Further, an insulating resin layer 18 is formed in the opening 15 and the recess 16 so as to be in contact with the roughened surface 17A of the rough plating layer 17. As a material of the resin layer 18, for example, a build-up resin (such as an epoxy resin with a filler) or a sealing resin can be used.

Next, the operation of the lead frame 1 adopting such a structure will be described.
A rough plating layer 17 having a roughened surface is formed on the inner wall surface 15 </ b> A of the opening 15 of the lead frame 1. And the insulating resin layer 18 is formed in the opening part 15 so that the rough surface 17A of this rough surface plating layer 17 may be contact | connected. As a result, the contact area between the roughened surface 17A of the rough surface plating layer 17 and the resin layer 18 is increased as compared with the case where the inner wall surface 15A of the opening 15 is a smooth surface. The adhesion between 2) and the resin layer 18 can be improved. Therefore, it is possible to suitably suppress the occurrence of peeling of the resin layer 18 from the substrate frame 2.

Next, a manufacturing method of the lead frame 1 configured as described above will be described.
First, a conductive substrate 30 shown in FIG. As the conductive substrate 30, for example, a metal plate such as Cu, an alloy based on Cu, Fe—Ni or an alloy based on Fe—Ni can be used. The thickness of the conductive substrate 30 is, for example, 100 to 500 μm.

  Next, as shown in FIG. 2B, a resist layer 31 having openings 31 </ b> A corresponding to the shapes of the openings 15 and the recesses 16 is formed on both surfaces of the conductive substrate 30. The resist layer 31 is formed by, for example, a photolithography method. Further, the material of the resist layer 31 is not particularly limited as long as it has a desired resolution and is a material having etching resistance and plating resistance.

  Subsequently, as shown in FIG. 2C, the substrate frame 2 is formed by etching the conductive substrate 30 from both sides using the resist layer 31 as an etching mask (substrate forming step). Specifically, the conductive substrate 30 exposed from the opening 31 </ b> A of the resist layer 31 is etched from both sides, and the opening 15 and the recess 16 are formed in the conductive substrate 30 to form the substrate frame 2. By forming the opening 15 and the recess 16, a section bar 11, a support bar 12 (see FIG. 1B), a die pad 13, and a lead 14 are defined corresponding to each of a plurality of semiconductor elements to be mounted. . Note that the etching solution used in this step can be appropriately selected according to the material of the conductive substrate 30. For example, when copper is used as the conductive substrate 30, an aqueous ferric chloride solution can be used as the etching solution, and the substrate forming step can be performed by spray etching from both sides of the conductive substrate 30.

  Next, as shown in FIG. 2D, the substrate frame 2 is subjected to electrolytic plating using the resist layer 31 as a plating mask. Specifically, the rough plating layer 17 whose surface is the roughened surface 17A is formed on the surface of the conductive substrate 30 exposed from the resist layer 31, that is, the inner wall surfaces 15A and 16A of the opening 15 and the recess 16. (Roughening step). As a result, roughened surfaces are formed on the inner wall surfaces 15 </ b> A and 16 </ b> A of the opening 15 and the recess 16. Here, the thickness of the rough plating layer 17 can be set to 1 to 10 μm, for example. In addition, the surface roughness of the roughened surface 17A is preferably in the range of 100 to 500 nm in terms of surface roughness Ra in terms of adhesion to the resin layer 18. However, in order to set such roughness, it is necessary to appropriately adjust the composition and current density of the plating solution to be used as described above.

Below, an example of the method of electrolytic plating is demonstrated. First, the configuration of the plating apparatus 40 will be described.
As shown in FIG. 3, the plating apparatus 40 includes a processing tank 41 and a plating solution 42. The substrate frame 2 after the substrate forming process, which is a processing target, is immersed in the processing tank 41. The processing tank 41 is configured such that the substrate frame 2 can be conveyed in the direction of the arrow by an attached guide roller (not shown). Further, the treatment tank 41 includes two platinum electrode plates (+) 44 and 45 connected to a rectifier 43 for electrolytic plating. The rectifier 43 also supplies power to the substrate frame 2.

  An example of conditions for forming the rough plating layer 17 composed of Ni using the plating apparatus 40 configured as described above will be described. That is, the composition of the plating bath and the plating conditions when using a nickel chloride plating bath as the plating solution are as follows (condition 1).

Nickel chloride plating bath:
Nickel chloride 75g / L
Sodium thiocyanate 15g / L
Ammonium chloride 30g / L
pH: about 4.5 to 5.5
Bath temperature: Room temperature (about 25 ° C)
Cathode current density: about 1 to 3 A / cm ²
Thus, the surface of the rough plating layer 17 is roughened by appropriately adjusting the composition, current density, etc. of the plating solution used in advance, and the roughness of the roughened surface 17A is set to the desired surface roughness. Can be set. In addition, the composition and plating conditions of the plating solution described above are examples, and the composition and conditions are particularly limited as long as the roughened surface 17A of the rough plating layer 17 is adjusted to have a desired surface roughness. Not.

Then, after such electrolytic plating, the resist layers 31 on both sides are peeled off as shown in FIG.
Next, as shown in FIG. 2F, a semi-cured resin sheet 33 is disposed on one side surface (here, the lower surface) of the roughened substrate frame 2. Here, as a material of the resin sheet 33, for example, a build-up resin (such as an epoxy resin containing a filler) or a sealing resin can be used.

  Subsequently, the substrate frame 2 and the resin sheet 33 are disposed between the lower plate member 34 and the upper plate member 35, and are pressed and heated from the upper and lower surfaces by a press device or the like. Thereby, the resin sheet 33 is melted, and as shown in FIG. 2G, the melted resin is embedded as the resin layer 18 in the opening 15 and the recess 16 (resin embedding step). Here, as the material of the plate members 34 and 35, a material having high heat resistance and rigidity is preferable, and a material excellent in releasability from the resin layer 18 is more preferable. For example, polytetrafluoroethylene or the like is used. it can.

  Then, both surfaces of the substrate frame 2 after resin embedding are polished to expose the end surfaces of the die pad 13 and the end surfaces of the leads 14 (inner leads 14A and outer leads 14B). This polishing can be performed by, for example, sand blasting or buffing.

Through the manufacturing process described above, the lead frame 1 having a structure in which a plurality of unit lead frames 10 assigned to each semiconductor element to be mounted are connected in a matrix, that is, the structure shown in FIG. 1 is manufactured. In the lead frame 1, the exposed end face of the die pad 13 and the end face of the lead 14 are plated, and then a semiconductor element is mounted on the plated die pad 13, and the semiconductor element and the inner lead 14A are mounted. Are wire-bonded and used for batch molding.
(Evaluation of adhesion of rough plating layer)
Next, the result of having evaluated the adhesiveness of the rough surface plating layer manufactured on the conditions 1 mentioned above is demonstrated.

  First, a sample for evaluation was prepared. Specifically, a copper alloy material (trade name “CDA194”) containing a small amount of Fe is prepared as a sample, and a rough surface plating layer made of Ni is electrolytically plated at different film thicknesses on one side thereof. A sample of was prepared.

Sample A1: film thickness 0.5 μm
Sample B1: Film thickness 1.0 μm
Sample C1: film thickness 3.0 μm
Sample D1: film thickness 5.0 μm
The composition of the electrolytic plating bath and the plating conditions used for the production of the evaluation samples A1 to D1 are the above-described condition 1.

  In addition, samples for comparison with the evaluation samples A1 to D1 were also produced. Specifically, a copper alloy material (trade name “CDA194”) containing a small amount of Fe is prepared as a sample, and an Ni plating layer having a smooth surface is electrolytically plated on the one surface with different film thicknesses, Four types of comparative samples were prepared.

Sample A2: film thickness 0.5 μm
Sample B2: film thickness 1.0 μm
Sample C2: film thickness 3.0 μm
Sample D2: film thickness 5.0 μm
The composition and plating conditions of the electrolytic plating bath used for the production of these comparative samples A2 to D2 are as follows (Condition 2).

Nickel sulfamate plating bath:
Nickel sulfamate 320g / L
Boric acid 30g / L
Nickel bromide 10g / L
pH: about 3.0 to 4.0
Bath temperature: about 30-50 ° C
Cathode current density: about 3 to 30 A / cm ²
Surface roughness Ra was calculated | required about each of all the samples produced in this way, ie, evaluation samples A1-D1 and comparative samples A2-D2. The results are shown in Table 1.

また、全てのサンプルＡ１〜Ｄ１，Ａ２〜Ｄ２について、ＳＥＭＩ標準規格Ｇ６９−０９９６に規定される手順に従ってカップせん断強さを測定し、Ｎｉからなる粗面めっき層に対する樹脂の密着性を評価した。その結果を図４に示す。この図４は、めっき層の表面粗さＲａとカップ剪断強さとの関係を例示するグラフである。この図において、評価用サンプルの結果は、表面粗さＲａが異なる評価用サンプルＡ１〜Ｄ１についてそれぞれ測定された剪断強さをグラフ化したものであり、比較用サンプルの結果は、表面粗さＲａが異なる比較用サンプルＡ２〜Ｄ２についてそれぞれ測定された剪断強さをグラフ化したものである。この結果から明らかなように、表面粗さＲａが高くなるほど剪断強さを強くなり、樹脂との密着性が高くなる。さらに、粗面めっき層の表面粗さＲａが１００ｎｍ以上になると、カップ剪断強さが、表面が平滑面である場合のカップ剪断強さよりも４倍程度強くなることが分かる。したがって、めっき層の表面粗さＲａが１００ｎｍ以上になると、そのめっき層と樹脂との密着性が良好となる。

Moreover, about all the samples A1-D1, A2-D2, cup shear strength was measured according to the procedure prescribed | regulated to SEMI standard G69-0996, and the adhesiveness of resin with respect to the rough surface plating layer which consists of Ni was evaluated. The result is shown in FIG. FIG. 4 is a graph illustrating the relationship between the surface roughness Ra of the plating layer and the cup shear strength. In this figure, the result of the evaluation sample is a graph of the shear strength measured for each of the evaluation samples A1 to D1 having different surface roughness Ra, and the result of the comparative sample is the surface roughness Ra. Is a graph of the shear strength measured for the comparative samples A2 to D2 having different values. As is apparent from this result, the higher the surface roughness Ra, the stronger the shear strength and the higher the adhesion with the resin. Furthermore, it can be seen that when the surface roughness Ra of the rough plating layer is 100 nm or more, the cup shear strength is about four times stronger than the cup shear strength when the surface is a smooth surface. Therefore, when the surface roughness Ra of the plating layer is 100 nm or more, the adhesion between the plating layer and the resin becomes good.

According to this embodiment described above, the following effects can be obtained.
(1) A rough plating layer 17 whose surface is a roughened surface 17A is formed on the inner wall surface 15A of the opening 15 of the substrate frame 2, and the resin layer 18 is placed in the opening 15 so as to be in contact with the roughened surface 17A. It was made to embed in. Since the roughened surface 17A increases the contact area between the inner wall surface of the opening 15 and the resin layer 18, it is possible to improve the adhesion between the rough plating layer 17 (substrate frame 2) and the resin layer 18. it can. Therefore, it is possible to suitably suppress the occurrence of peeling of the resin layer 18 from the substrate frame 2.

  (2) Roughening of the opening 15 to the inner wall surface 15A is performed by electrolytic plating. Thereby, compared with the case where roughening is performed by etching, the life of the treatment solution (plating solution) can be extended, and the plating solution can be used continuously. For this reason, it can contribute to cost reduction.

  (3) The roughness of the roughened surface 17A of the rough plating layer 17 in contact with the resin layer 18 was set to 100 nm or more in terms of the surface roughness Ra. Thereby, favorable adhesiveness can be obtained between the rough surface plating layer 17 and the resin layer 18.

  (4) The resist layer 31 is used as an etching mask and a plating mask. Thereby, it is not necessary to form separate masks in each of the etching process (substrate forming process) and the plating process (roughening process), so that the manufacturing process can be reduced and the cost can be reduced.

In addition, the said 1st Embodiment can also be implemented in the following aspects which changed this suitably.
In the first embodiment, the end surface of the die pad 13 and the end surface of the lead 14 are exposed. However, as shown in FIG. 5, the plating layers 13 </ b> C and 14 </ b> C are respectively formed on the end surface of the die pad 13 and the end surface of the lead 14. You may make it form. The plating layers 13C and 14C can be formed, for example, by performing a plating process on the substrate frame 2 after the polishing step shown in FIG. Examples of the plating treatment include, but are not limited to, a plating treatment for sequentially applying Ni plating and Au plating, a plating treatment for applying Ag plating, and the like.

  In the first embodiment, the substrate frame 2 is formed from the conductive substrate 30 by etching, but the substrate frame 2 may be formed from the conductive substrate 30 by, for example, pressing.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. 6 and 7. The same members as those shown in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 6, the substrate frame 2A of the lead frame 1A of the present embodiment is provided with a plurality of gate portions 4 that are injection ports for filling a resin in a region outside the unit lead frame 10 as a product. It has been. The gate portion 4 is provided corresponding to each mold cavity 3.

Next, a manufacturing method of the lead frame 1A using the gate portion 4 will be described.
First, a conductive substrate 50 shown in FIG. As the conductive substrate 50, for example, a metal plate such as Cu, an alloy based on Cu, Fe-Ni or an alloy based on Fe-Ni can be used. The thickness of the conductive substrate 50 is, for example, 100 to 500 μm.

  Next, as shown in FIG. 7B, a resist layer 51 having openings 51 </ b> A corresponding to the shapes of the openings 15, the recesses 16, and the gate portions 4 is formed on both surfaces of the conductive substrate 50. The resist layer 51 is formed by, for example, a photolithography method. The material of the resist layer 51 is not particularly limited as long as the material has desired resolution and has etching resistance and plating resistance.

  Subsequently, as shown in FIG. 7C, the conductive substrate 50 exposed from the opening 51 </ b> A of the resist layer 51 is etched from both sides, and the opening 15, the recess 16, and the gate portion 4 are formed in the conductive substrate 50. To form a substrate frame 2A. By forming the opening 15 and the recess 16, a section bar 11, a support bar 12 (see FIG. 1B), a die pad 13, and a lead 14 are defined corresponding to each of a plurality of semiconductor elements to be mounted. . At this time, in this step, the conductive substrate 50 is etched so that the openings 15 are spatially continuously formed.

  Next, as shown in FIG. 7D, the surface of the conductive substrate 50 exposed from the resist layer 51, that is, the inner wall surfaces 15A and 16A of the opening 15 and the recess 16, as in the first embodiment. The rough surface plating layer 17 whose surface is the roughened surface 17A is formed. In this roughening step, the rough surface plating layer 17 is also formed on the gate portion 4. Here, the thickness of the rough plating layer 17 can be set to 1 to 10 μm, for example. Further, the surface roughness of the roughened surface 17A is in the range of 100 to 500 nm in terms of the surface roughness Ra value. After such plating treatment, the resist layers 51 on both sides are peeled off as shown in FIG.

  Next, as shown in FIG. 7 (f), resin films 52 and 53 for protecting the surface of the substrate frame 2A are disposed on both surfaces of the roughened substrate frame 2A, and the substrate frame 2A and the resin film are disposed. 52 and 53 are fixed by a molding die (one set of upper die 54 and lower die 55). Subsequently, the insulating resin 56 is injected from the gate portion 4 while being heated and pressurized (resin embedding step). As a result, as shown in FIG. 7G, the resin layer 18 is formed by filling the resin 56 into the opening 15 and the recess 16 in which a space is formed by the substrate frame 2 </ b> A and the resin films 52 and 53. . At this time, in order to spread the resin 56 throughout, it is necessary that the space for injecting the resin 56 is continuous. For this reason, when the space for injecting the resin 56 is not continuous only with the original lead frame pattern, in addition to the original lead frame pattern in the above-described steps of FIGS. 7B and 7C. In this step, the pattern that becomes the path of the resin 56 is processed into the conductive substrate 50, so that the openings 15 and the recesses 16 are spatially continuous.

  Here, as the material of the resin films 52 and 53, a material having high heat resistance and flexibility is preferable, and when the resin films 52 and 53 are fixed by the molds 54 and 55, the resin films 52 and 53 and the substrate frame 2A are interposed. A material that can be closely attached to the substrate frame 2 </ b> A so that the resin 56 does not enter is more preferable, and a material that is excellent in releasability from the resin 56 is more preferable. For example, as a material of the resin films 52 and 53, a fluororesin can be used. The resin films 52 and 53 have a thickness of 50 to 100 μm, for example. On the other hand, the material of the resin 56 is preferably a material with high fluidity. For example, as the material of the resin 56, for example, a build-up resin (such as an epoxy resin containing a filler) or a sealing resin can be used.

  Next, as shown in FIG. 7G, the substrate frame 2A on which the resin layer 18 is formed is taken out of the molds 54 and 55, and the resin films 52 and 53 are peeled from the substrate frame 2A. As a result, a lead frame 1A having a structure other than the gate portion 4 substantially the same as the structure shown in FIG.

  Subsequently, as shown in FIG. 7 (h), the end surface of the die pad 13 and the end surface of the lead 14 are plated to form plating layers 13 </ b> C and 14 </ b> C on each of the end surface of the die pad 13 and the end surface of the lead 14. Through the above manufacturing process, a lead frame 1A having a structure other than the gate portion 4 substantially the same as the structure shown in FIG. 5 can be manufactured. In the lead frame 1A, a semiconductor element is mounted on the plated die pad 13, and the semiconductor element and the lead 14 are wire-bonded and used for batch molding. In addition, the lead frame 1A can be used for a step of mounting a semiconductor element after cutting the gate portion 4 provided in a region outside the product portion.

According to the embodiment described above, the following effects are obtained in addition to the effects (1) to (4) of the first embodiment.
(5) The resin layer 18 is formed in the opening 15 and the recess 16 by injecting the resin 56 while applying pressure and heating. Thereby, it can suppress suitably that the outer surface of lead frame 1A (board frame 2A) is contaminated with resin 56.

In addition, the said 2nd Embodiment can also be implemented in the following aspects which changed this suitably.
The position where the gate portion 4 is provided in the second embodiment is not particularly limited as long as it is an area outside the unit lead frame 10 that is a product.

  In the resin embedding process of the second embodiment (see FIG. 7F), the resin film 52 disposed on the upper surface side of the substrate frame 2A and the resin film 53 disposed on the lower surface side may be different materials. For example, a resin film of another material can be attached in advance to one surface of the substrate frame 2A.

Alternatively, the resin films 52 and 53 may be omitted.
(Third embodiment)
Hereinafter, a third embodiment will be described with reference to FIGS. The same members as those shown in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 8A, each unit lead frame 10B is formed with an opening 15 that defines a section bar 11, a support bar 12, a die pad 13, and a lead. As shown in FIG. 8B, the opening 15 is formed so as to penetrate from the first main surface R1 to the second main surface R2 of the substrate frame 2B. Specifically, the opening 15 is formed by communication between a first recess 21 formed on the first main surface R1 side and a second recess 22 formed on the second main surface R2 side. A recess 16 is formed on the back surface (lower surface in the drawing) of the section bar 11.

  A rough surface plating layer 23 having a roughened surface is formed on a part of the inner wall surface of the opening 15, specifically, the inner wall surface 21 </ b> A of the first recess 21. Here, the inner wall surface 21 </ b> A of the first recess 21 is a partial surface of the side surface of the die pad 13 or a partial surface of the side surface of the lead 14. Similarly, the rough plating layer 23 is formed on the inner wall surface 16 </ b> A of the recess 16. The rough surface plating layer 23 can be composed of, for example, any one of Ni, Cr, Fe, or an alloy thereof, or a laminate composed of two or more of these. The roughened surface (surface) 23A of the rough plating layer 23 is formed in a fine uneven shape. The roughness of the roughened surface 23A is adjusted, for example, to a surface roughness Ra value of 100 by adjusting the composition, current density, etc. of the plating solution used when the rough surface plating layer 23 is formed by the electrolytic plating method. It is set to be in a range of ˜500 nm.

  In addition, an insulating resin layer 24 is formed in the first recess 21 and the recess 16 so as to be in contact with the roughened surface 23 </ b> A of the rough plating layer 23. As a material of the resin layer 24, for example, a build-up resin (such as an epoxy resin containing a filler) or a sealing resin can be used.

Next, a manufacturing method of the lead frame 1B configured as described above will be described.
First, a conductive substrate 60 shown in FIG. 9A is prepared. As the conductive substrate 60, for example, a metal plate such as Cu, an alloy based on Cu, Fe-Ni or an alloy based on Fe-Ni can be used. Further, the thickness of the conductive substrate 60 is, for example, 100 to 500 μm.

  Next, as shown in FIG. 9B, resist layers 61 and 62 having a predetermined pattern are formed on both surfaces of the conductive substrate 60. Specifically, a resist layer 61 having an opening 61A corresponding to the shape of the recesses 16 and 21 is formed on the lower surface of the conductive substrate 60, and the shape of the recess 22 is formed on the upper surface of the conductive substrate 60. A resist layer 62 is formed. The resist layers 61 and 62 are formed by, for example, a photolithography method. Further, the material of the resist layers 61 and 62 is not particularly limited as long as the material has desired resolution and has etching resistance and plating resistance.

  Subsequently, as shown in FIG. 9C, the upper surface of the conductive substrate 60 to be the second main surface R2 is covered with a cover sheet 63, and is formed on the lower surface of the conductive substrate 60 to be the first main surface R1. The conductive substrate 60 exposed from the resist layer 61 is etched by a predetermined amount to form the recesses 16 and 21 (first substrate processing step). Here, as the cover sheet 63, for example, a polyolefin-based adhesive film or the like can be used. Further, the etching solution used here can be appropriately selected according to the material of the conductive substrate 60. For example, when copper is used as the conductive substrate 60, a ferric chloride aqueous solution can be used as an etching solution.

  Next, as shown in FIG. 9D, as in the first embodiment, the surface of the conductive substrate 60 exposed from the resist layer 61 and the cover sheet 63, that is, the inner wall surfaces 16A of the recesses 16 and 21, The rough surface plating layer 23 whose surface is the roughened surface 23A is formed on 21A. As a result, a roughened surface is formed on the inner wall surface 21 </ b> A of the first recess 21 and the inner wall surface 16 </ b> A of the recess 16. Here, the thickness of the rough plating layer 23 can be set to 1 to 10 μm, for example. Further, the surface roughness of the roughened surface 23A is in the range of 100 to 500 nm in terms of the surface roughness Ra value.

  After such a plating process, as shown in FIG. 9E, the resist layer 61 formed on the lower surface side of the conductive substrate 60 is peeled off, and the cover sheet 63 is removed. Thereafter, the conductive substrate 60 and the resin sheet 64 disposed on the lower surface side of the conductive substrate 60 are disposed between the lower plate member 65 and the upper plate member 66, and are applied from both the upper and lower surfaces by a press device or the like. Press and heat. As a result, the resin sheet 64 is melted, and the melted resin 64 is embedded in the first recess 21 and the recess 16 as the resin layer 24 as shown in FIG. Here, as a material of the resin sheet 64, for example, a build-up resin (such as an epoxy resin with a filler) or a sealing resin can be used. Further, as the material of the plate members 65 and 66, a material having high heat resistance and rigidity is preferable, and a material excellent in releasability from the resin layer 24 is more preferable. For example, polytetrafluoroethylene or the like can be used. .

  The resin embedding process may be performed without removing the cover sheet 63 (see FIG. 9D). That is, the cover sheet 63, the conductive substrate 60, and the resin sheet 64 may be sandwiched between the plate members 65 and 66. In this case, the material of the cover sheet 63 is preferably a material having high heat resistance.

  Next, the surface of the conductive substrate 60 where the resin layer 24 is embedded (the lower surface in the drawing) is polished to expose the end surface of the die pad 13 and the end surface of the outer lead 14B. This polishing can be performed by, for example, sand blasting or buffing.

  Next, as shown in FIG. 10B, a plating process is performed on both surfaces of the conductive substrate 60 to form plated layers 13 </ b> C and 14 </ b> C on each of the end surface of the die pad 13 and the end surface of the lead 14. At this time, the resist layer 62 functions as a plating mask on the upper surface side of the conductive substrate 60, and the resin layer 24 functions as a plating mask on the lower surface side of the conductive substrate 60. Examples of the plating treatment include, but are not limited to, a plating treatment in which Ni plating and Au plating are sequentially performed, a plating treatment in which Ag plating is performed, and the like.

  Subsequently, as shown in FIG. 10C, after the resist layer 62 is peeled off, the conductive substrate 60 is etched from the upper surface side using the plating layer 13C as an etching mask (second substrate processing step). That is, as shown in FIG. 10D, the conductive substrate 60 exposed from the plating layer 13C formed on the upper surface of the conductive substrate 60 to be the second main surface R2 is etched by a predetermined amount, The rough plating layer 23 formed on the upper surface of the resin layer 24 is exposed. Further, the exposed rough plating layer 23 is etched to form a second recess 22 that communicates with the first recess 21 to form the opening 15. Thereby, the substrate frame 2B in which the section bar 11, the support bar 12 (see FIG. 8A), the die pad 13, and the leads 14 are defined is formed.

  Through the above manufacturing process, a structure in which a plurality of unit lead frames 10B assigned to each semiconductor element to be mounted are connected in a matrix, that is, a lead frame 1B having the structure shown in FIG. 8 is manufactured. In this lead frame 1B, a semiconductor element is mounted on the plated die pad 13, and the semiconductor element and the lead 14 are wire-bonded and used for batch molding.

According to embodiment described above, there exists an effect similar to (1)-(4) of 1st Embodiment.
In addition, the said 3rd Embodiment can also be implemented with the following aspects which changed this suitably.

  In the above embodiment, the resin embedding process is performed by the same method as in the first embodiment. For example, the resin embedding process may be performed by the same method as in the second embodiment. In other words, the insulating resin may be injected while being pressurized and heated using a gate portion provided in a region outside the unit lead frame 10B. Specifically, the roughened conductive substrate 60 and the resin films disposed on both surfaces of the conductive substrate 60 are fixed with a mold, and the insulating resin is injected from the gate portion while heating and pressing. By doing so, the resin layer 24 may be formed in the first recess 21 and the recess 16. In this case, in order to spread the resin to be injected over the entire space, the space for injecting the resin needs to be continuous. Therefore, in the steps of FIGS. 9B and 9C, the first recess 21 is spatial. The conductive substrate 60 is processed so as to be continuous.

Alternatively, the resin embedding step may be performed by, for example, vacuum printing.
In the above embodiment, the rough plating layer 23 is formed on the inner wall surface 21 </ b> A of the first recess 21 in the opening 15, and the resin layer 24 is formed in the first recess 21. For example, as shown in FIG. 11, a rough plating layer 23 is formed on the inner wall surface 22 </ b> A of the second recess 22 in the opening 15, and a resin layer 24 is formed in the second recess 22. May be. The method for manufacturing the lead frame 1C is substantially the same as the manufacturing process of the lead frame 1B shown in FIG. 9 and FIG.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIGS. The same members as those shown in FIGS. 1 to 11 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 12, the semiconductor device 70 of the present embodiment has a QFN package structure manufactured using the lead frame 1 of the first embodiment. The semiconductor device 70 has the unit lead frame 10 of the lead frame 1. A semiconductor element 71 is mounted on the die pad 13 of the unit lead frame 10, specifically on the die pad 13 having the plating layer 13C. An electrode (not shown) of the semiconductor element 71 is connected to the plating layer 14C (inner lead 14A) via a bonding wire 72. The semiconductor element 71 and the bonding wire 72 are sealed with a sealing resin 73. In the semiconductor device 70, the outer lead 14B (plating layer 14C) is exposed from the sealing resin 73 as an external connection terminal.

  The semiconductor element 71 is, for example, an IC chip or an LSI chip. As the bonding wire 72, for example, a fine wire such as gold (Au) or aluminum (Al) can be used. As a material of the sealing resin 73, for example, an epoxy resin, a polyimide resin, a phenol resin, a vinyl chloride resin, or the like can be used.

Next, a method for manufacturing the semiconductor device 70 configured as described above will be described.
First, the lead frame 1 is manufactured by the manufacturing method described with reference to FIG. 2, and after forming the plating layers 13C and 14C on the end surface of the die pad 13 and the end surface of the lead 14 as shown in FIG. The semiconductor element 71 is mounted on each die pad 13 on which the plating layer 13C is formed. Thereafter, the electrode of each semiconductor element 71 and the inner lead 14 </ b> A are electrically connected by the bonding wire 72. As a result, the semiconductor element 71 is mounted on the unit lead frame 10.

  Subsequently, as shown in FIG. 13B, the surface on the side where the semiconductor element 71 of the lead frame 1 is mounted for each mold cavity 3 (see FIG. 1A) by the collective molding method (in the drawing). , The upper surface) is sealed with a sealing resin 73. Thereby, the semiconductor element 71 and the bonding wire 72 are sealed with the sealing resin 73. Although not shown in the drawings, this sealing step is such that the lead frame 1 is placed on the lower mold of a molding die (one set of upper and lower molds), and the lead frame 1 is sandwiched by the upper mold from above. It is performed by heating and pressurizing while filling the sealing resin 73. As this sealing method, for example, a transfer mold can be used. In this sealing step, the resin layer 18 filled in the opening 15 functions as a member that prevents the sealing resin 73 from flowing.

Next, as shown in FIG. 1 3 (c), a dicing saw, to cut the section bar 11 and the sealing resin 73 of the position of the arrow, to 70 two pieces of individual semiconductor devices. Through such a process, the individual semiconductor device 70 shown in FIG. 1 3 (d) is manufactured.

According to this embodiment described above, the same effects as those of the first embodiment can be obtained.
In addition, the said 4th Embodiment can also be implemented in the following aspects which changed this suitably.

  In the fourth embodiment, the plating layers 13C and 14C are formed on the end surface of the die pad 13 and the end surface of the lead 14, respectively. For example, as illustrated in FIG. 14A, the semiconductor device 80 may be embodied in which the semiconductor element 71 is mounted on the unit lead frame 10 without forming the plating layers 13 </ b> C and 14 </ b> C. Further, any one of the plating layers 13C and 14C may be omitted.

  In the fourth embodiment, the semiconductor device 70 is manufactured using the lead frame 1 of the first embodiment. For example, the present invention may be embodied in a semiconductor device manufactured using the unit lead frame 10 of the lead frame 1A of the second embodiment. Further, as shown in FIG. 14B, the semiconductor device 81 may be embodied by using a unit lead frame 10B of the lead frame 1B of the third embodiment. Further, as shown in FIG. 14C, the semiconductor device 82 may be embodied using a unit lead frame 10C of a lead frame 1C (see FIG. 11) of a modification of the third embodiment. The method of manufacturing these semiconductor devices 81 and 82 is substantially the same as the manufacturing process of the semiconductor device 80 shown in FIG.

(Other embodiments)
In addition, each said embodiment can also be implemented in the following aspects which changed this suitably.
In each of the above embodiments, nickel chips may be used instead of the platinum electrode plates 44 and 45 of the plating apparatus 40 shown in FIG.

  In each of the above embodiments, after a plating layer having a smooth surface is formed on at least a part of the inner wall surface of the opening 15, a rough plating layer may be formed on the plating layer.

In each of the above embodiments, the inner wall surfaces of the opening 15 and the recesses 16, 21, and 22 are roughened by electrolytic plating, but the roughening method is not limited to this.
-There is no restriction | limiting in particular in the shape of lead frame 1,1A, 1B, 1C of said each embodiment. That is, at least a part of the inner wall surface 15A of the opening 15 that defines the die pad 13 and the lead 14 is roughened, and a resin is embedded in at least a part of the opening 15 so as to be in contact with the roughened surface. The shape of the lead frame is not particularly limited as long as it has the lead frame.

  In each of the above embodiments, the unit lead frames 10, 10B, and 10C are embodied in a lead frame in which a plurality of unit lead frames are connected in a matrix. However, for example, a plurality of unit lead frames 10, 10B, and 10C are connected in a strip shape. The lead frame may be embodied. That is, the arrangement of the unit lead frames is not particularly limited as long as a plurality of unit lead frames are connected in series.

  In the first to third embodiments, the lead frame used in the QFN is embodied, but the present invention is not limited to this. For example, it is embodied in a lead frame used for a surface mount type package in which a plurality of terminals for external connection are exposed on one side of a package such as BGA, LGA, CSP and SON (Small Outline Non-Leaded Package). Also good.

1, 1A, 1B, 1C Lead frame 2, 2A, 2B, 2C Substrate frame 4 Gate portion 10, 10B, 10C Unit lead frame 13 Die pad 14 Lead 15 Opening portion 17 Rough surface plating layer 18 Resin layer 21 First recess 22 First 2 concave portion 23 rough surface plating layer 24 resin layer 30, 50, 60 conductive substrate 31, 51 resist layer 54, 55 mold 56 resin 70, 80-82 semiconductor device 71 semiconductor element 72 bonding wire 73 sealing resin

Claims (16)

A lead frame in which a plurality of unit lead frames each having a section bar and a die pad and leads supported by the section bar are provided;
An opening defining the section bar and the die pad and the lead;
A recess formed in the lower surface of the section bar;
A rough surface plating layer having a roughened surface formed on at least a part of the inner wall surface of the opening and the inner wall surface of the recess, which is the side surface of the die pad or the side surface of the lead,
An insulating resin layer embedded in at least a part of the opening and the recess so as to be in contact with the rough surface plating layer;
A lead frame comprising: The opening is formed by communicating a first recess formed on the lower surface side of the die pad and a second recess formed on the upper surface side of the die pad,
The lead frame according to claim 1, wherein the resin layer is embedded to fill the first recess, the second recess, and the recess. The opening is formed by communicating a first recess formed on the lower surface side of the die pad and a second recess formed on the upper surface side of the die pad,
The resin layer is embedded to fill the recess and the first recess,
The lead frame according to claim 1, wherein an inner wall surface of the second recess is exposed from the resin layer. The lead frame according to any one of claims 1 to 3 , wherein a surface roughness Ra of the rough plating layer is 100 nm or more. Lead frame according to any one of claims 1-4 lower surface of the die pad, wherein a width narrower than that top surface of the die pad. The unit lead frame of the lead frame according to any one of claims 1 to 3,
A semiconductor element mounted on the die pad;
A bonding wire for electrically connecting the semiconductor element and the lead;
A sealing resin for sealing the semiconductor element and the bonding wire;
2. A semiconductor device according to claim 1, wherein an outer side surface of the lead and an outer side surface of the resin layer filled in the recess are formed flush with each other. A section bar defines a die pad and a lead supported by the section bar, and a first recess formed on the lower surface side of the die pad and a second recess formed on the upper surface side of the die pad communicate with each other. An opening formed by,
A third recess formed in the lower surface of the section bar;
A rough plating layer having a roughened surface formed only on the inner wall surface of the first recess, the inner wall surface of the second recess, and the inner wall surface of the third recess;
A unit lead frame having an insulating resin layer embedded so as to be in contact with the rough plating layer and filling only the first recess, the second recess, and the third recess;
A semiconductor element mounted on the die pad;
A sealing resin for sealing the semiconductor element in contact with the top surface of the section bar, the top surface of the die pad, the top surface of the lead, and the top surface of the resin layer;
A semiconductor device comprising: A section bar defines a die pad and a lead supported by the section bar, and a first recess formed on the lower surface side of the die pad and a second recess formed on the upper surface side of the die pad communicate with each other. An opening formed by,
A third recess formed in the lower surface of the section bar;
A rough surface plating layer having a roughened surface formed only on the inner wall surface of the first recess and the inner wall surface of the third recess;
A unit lead frame having an insulating resin layer embedded so as to be in contact with the rough plating layer and filling only the first recess and the third recess;
A semiconductor element mounted on the die pad;
A sealing resin that contacts the upper surface of the section bar, the upper surface of the die pad, the upper surface of the lead, and the upper surface of the resin layer, fills the second recess, and seals the semiconductor element;
A semiconductor device comprising: A method of manufacturing a lead frame in which a plurality of unit lead frames each having a section bar and a die pad and leads supported by the section bar are provided,
A substrate forming step of forming an opening for defining the section bar, the die pad and the lead in the conductive substrate, and forming a substrate frame by forming a recess on a lower surface of the conductive substrate to be the section bar. When,
A roughening step of forming a rough surface plating layer having a roughened surface only on at least a part of the inner wall surface of the opening and the inner wall surface of the recess which is the side surface of the die pad or the side surface of the lead;
A resin embedding step of embedding an insulating resin in at least a part of the opening and the recess so as to be in contact with the rough plating layer;
A method for manufacturing a lead frame, comprising: In the substrate forming step, the substrate frame is formed so that the openings are continuously formed in space.
The resin embedding step includes
The substrate frame after the roughening step is fixed with a mold, and the resin is injected into the opening by heating and pressurizing the insulating resin from a gate portion provided outside the unit lead frame. The lead frame manufacturing method according to claim 9 , wherein the portion is filled. The substrate forming step includes
Forming a resist layer having openings corresponding to the shapes of the openings and the recesses on both surfaces of the conductive substrate;
Etching the conductive substrate from both sides using the resist layer as an etching mask,
The step of forming the rough surface plating layer includes forming the rough surface plating layer by electrolytic plating using the resist layer as a mask,
The resin filling step is to fill the opening and the recess, the manufacturing method of lead frame according to claim 9 or 10, characterized in that filling the resin into the opening and the recess. A method of manufacturing a lead frame in which a plurality of unit lead frames each having a section bar and a die pad and leads supported by the section bar are provided,
A first substrate is formed on the lower surface of the conductive substrate that forms the opening defining the section bar, the die pad, and the lead, and the concave portion is formed on the lower surface of the conductive substrate serving as the section bar. Processing steps,
A roughening step of forming a rough surface plating layer having a roughened surface only on the inner wall surface of the first recess and the inner wall surface of the recess;
A resin embedding step of embedding an insulating resin in the first concave portion and the concave portion so as to be in contact with the rough surface plating layer and filling the first concave portion and the concave portion;
A second substrate processing step for forming the opening by forming a second recess communicating with the first recess on the upper surface of the conductive substrate;
A method for manufacturing a lead frame, comprising: In the first substrate processing step, the conductive substrate is processed so that the first concave portions are spatially continuously formed,
The resin embedding step includes
The conductive substrate after the roughening step is fixed with a mold, and an insulating resin is injected from a gate portion provided outside the unit lead frame while being heated and pressurized, whereby the resin is injected into the first substrate. The lead frame manufacturing method according to claim 12 , wherein one recess is filled. A method for manufacturing a semiconductor device using a lead frame manufactured by the method for manufacturing a lead frame according to any one of claims 9 to 13 ,
Mounting a semiconductor element on each die pad of the lead frame;
Electrically connecting the electrode of the semiconductor element and the lead by a bonding wire;
Sealing the semiconductor element and the bonding wire with a sealing resin;
Cutting the sealing resin at a predetermined position, the section bar, and the resin filled in the recesses, and dividing the semiconductor resin unit into units;
A method for manufacturing a semiconductor device, comprising: A first recess forming an opening defining the section bar, die pad, and lead is formed on the lower surface of the conductive substrate, and a second recess communicating with the first recess is formed on the upper surface of the conductive substrate. A substrate forming step of forming an opening and forming a substrate frame by forming a third recess on a lower surface of the conductive substrate to be the section bar;
A roughening step of forming a rough surface plating layer having a roughened surface only on the inner wall surface of the first recess, the inner wall surface of the second recess, and the inner wall surface of the third recess;
A resin embedding step of embedding an insulating resin so as to be in contact with the rough plating layer and filling only the first recess, the second recess, and the third recess;
Mounting a semiconductor element on the die pad;
Forming a sealing resin for sealing the semiconductor element in contact with an upper surface of the section bar, an upper surface of the die pad, an upper surface of the lead, and an upper surface of the resin;
A method for manufacturing a semiconductor device, comprising: First substrate processing for forming a first recess forming the opening defining the section bar, die pad, and lead on the lower surface of the conductive substrate, and forming a third recess on the lower surface of the conductive substrate serving as the section bar Process,
A roughening step of forming a rough surface plating layer having a roughened surface only on the inner wall surface of the first recess and the inner wall surface of the third recess;
A resin embedding step of embedding an insulating resin so as to be in contact with the rough plating layer and filling only the first recess and the third recess;
Forming a second recess on the upper surface of the conductive substrate to communicate with the first recess to form the opening;
Mounting a semiconductor element on the die pad;
Forming a sealing resin that contacts the upper surface of the section bar, the upper surface of the die pad, the upper surface of the lead, and the upper surface of the resin, fills the second recess, and seals the semiconductor element;
A method for manufacturing a semiconductor device, comprising:

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