CN103000648A - Large chip scale package and manufacturing method thereof - Google Patents
Large chip scale package and manufacturing method thereof Download PDFInfo
- Publication number
- CN103000648A CN103000648A CN201210478706XA CN201210478706A CN103000648A CN 103000648 A CN103000648 A CN 103000648A CN 201210478706X A CN201210478706X A CN 201210478706XA CN 201210478706 A CN201210478706 A CN 201210478706A CN 103000648 A CN103000648 A CN 103000648A
- Authority
- CN
- China
- Prior art keywords
- wafer
- layer
- hole
- glass
- tsv
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides large chip scale package and a manufacturing method thereof and belongs to the technical field of sensors. An optical interaction region is arranged at the center above a silicon substrate in a first surface of a wafer, one side provided with the optical interaction region is connected with a metal interconnection structure, and an input-output (I/O) around the optical interaction region on the silicon substrate is connected to an electrode pad through the metal interconnection structure. The surface of the metal interconnection structure is provided with a protective layer, and a stepped protrusion or groove structure is formed on the protective layer. The first surface of the wafer is bonded with a glass piece together, and a cavity is formed between the glass piece and the wafer. A second surface of the wafer is provided with a through silicon via (TSV) hole, the electrode pad penetrates through the silicon substrate through the TSV hole to be connected to a bonding pad on the second surface of the wafer, a passivation layer and a metal liner are sequentially manufactured on a hole wall of the TSV hole, and a polymer material is filled into the TSV hole. An anti-welding layer is manufactured on the second surface of the wafer, and a weld ball is manufactured on the bonding pad. By means of the large chip scale package and the manufacturing method, the layering problem of glass and the silicon substrate in an existing package structure is solved, and the packing reliability is improved.
Description
Technical field
The present invention relates to a kind of large chip size encapsulation (CSP) and a kind of method of making described large chip size encapsulation (CSP).Described encapsulating structure and manufacture method can be preferably used for imageing sensor or MEMS device.
Background technology
Chip size packages (CSP) is the chip encapsulation technology of a new generation, and its technical performance has had again new lifting.The CSP encapsulation can allow chip area and the ratio of package area surpass 1:1.14, and quite near the ideal situation of 1:1, absolute dimension also only has 32 square millimeters, is about 1/3 of common BGA, only is equivalent to 1/6 of TSOP memory chip area.Compare with the BGA encapsulation, the CSP encapsulation can improve memory capacity three times under the equal space.The purpose of CSP is when using the little chip of large chip (chip functions is more, and performance is better, and chip is more complicated) before substituting, and the area that its packaging body takies printed panel remains unchanged or be less.Packaging body just because of the CSP product is little and thin, so it has obtained rapidly application in hand-held mobile electronic device.CSP has not only dwindled significantly the volume size after the encapsulation, has reduced packaging cost, has improved packaging efficiency, and more meets the requirement of high-density packages; Simultaneously because because data transfer path is short, stability is high, this speed and the stability that has also promoted transfer of data when reducing energy consumption that is encapsulated in.
Imageing sensor is a kind of semiconductor module, is a kind of equipment that optical imagery is converted into electronic signal, electronic signal can be used to do further processing or be digitized after be stored, or be used for image transfer shown to another display unit etc.It is widely used in digital camera and other electro-optical devices.Nowadays imageing sensor mainly is divided into charge-coupled device (CCD) and cmos image sensor (CIS, CMOS Image Sensor).Although ccd image sensor is better than cmos image sensor at aspects such as picture quality and noises, cmos sensor can be with traditional semiconductor fabrication techniques manufacturing, and production cost is lower.Simultaneously because used parts number is relatively less and signal transmission distance is short, the advantages such as that cmos image sensor possesses is low in energy consumption, electric capacity, inductance and stray delay reduction.
Figure 1 shows that the encapsulation schematic diagram of a traditional cmos image sensor (CIS).Shown in cmos sensor is logical comprises: ceramic bases 2, the integrated circuit 4(IC that installs at ceramic bases 2 top surfaces), bond layer 3 is positioned at integrated circuit 4(IC) and ceramic bases 2 between.At integrated circuit 4(IC) there is the pad 6 on the IC surface of making on the surface, and 7 pads 8 with the substrate surface on the ceramic bases 2 are connected by going between.Image photosensitive area 5 is positioned at integrated circuit 4(IC) the top, image photosensitive area 5 comprises that can accept light produces the optics interactive elements of the signal of telecommunication (such as photosensitive electric diode, photodiode) array.Be installed on the framework 1 with the corresponding glass lens 10 of described optics interactive elements, framework 1 connects with ceramic bases 2 by bonding agent 9.
Cmos sensor structure shown in Figure 1 has much can improved aspect.The first, because bulky glass lens 10 has been used in this encapsulation, this is totally unfavorable to the volume that reduces to encapsulate, therefore can be by the volume that adopts lenticule 110 to reduce to encapsulate.Second, ceramic bases 2 can be changed to silicon substrate, by making heavy distribution layer (RDL) in surface of silicon with integrated circuit 4(IC) not shown on the I/O(figure at edge) be connected with the pad 8 of substrate surface, the size of encapsulating structure can further be reduced like this.The 3rd, shown in encapsulating structure can not be with the processing of the lower wafer scale of cost and surface mounting technology.
Fig. 2 is cmos image sensor (CIS) encapsulating structure of improved existing employing silicon through hole (TSV) technology.In encapsulation shown in Figure 2, at first at the top surface making image sensing unit 120 of silicon substrate 130, described image sensing district 120 comprises the transistor array (not shown) of optics interactive elements and the output of control photosignal, is placed with a plurality of micro lens 110 on image sensing district 120.Secondly, make heavy distribution layer 160(RDL by the surface at silicon substrate 130 tops) I/O(at 120 edges, image sensing district is not shown) be connected to silicon through hole 170(TSV).At last, silicon through hole 170(TSV) extend to the pad pad 175 of lower surface from the top of silicon substrate 130, soldered ball 190 is produced on the pad pad 175.Be furnished with welding resisting layer 180(SMF at the back side of silicon substrate 130).The sheet glass 150 at top is bonded together with silicon substrate 130 by polymer connector 140.
Growing along with the CMOS technology, integrated level is also more and more higher, this is just so that the area in image sensing district more and more comes to realize more large-area photosensitive region, and for encapsulating structure shown in Figure 2 when increasing along with the sensing unit area, sheet glass 150 is also more and more serious with the lamination between the silicon substrate 130.In addition, silicon through hole (TSV) is if adopt when electroplating Cu technique, and it (can be oxide, such as silicon dioxide that through hole need at first be made insulating barrier; Also can be nitride such as silicon nitride), separator is finished at last plating Cu and is filled up hole.Electroplating Cu also is a kind of expensive technique.
Summary of the invention
A first aspect of the present invention is: based on the current chip size packages (CSP) that is applicable to cmos image sensor, easily produce the problem of layering between with wafer for glass when chip size increases gradually, a kind of improved large size chip CSP encapsulating structure is provided, in order to improve this lamination problem, improve the reliability of encapsulation.
Large chip size encapsulation of the present invention (CSP) comprises wafer, and the front of described wafer 200 is for forming the first surface 201 in image sensing district, and the negative of described wafer 200 is second surface 202; The central authorities of silicon substrate 130 tops are provided with optics interactive areas 210 in described wafer 200 first surfaces 201, be connected with metal interconnection structure 220(IMD in the one side that is provided with optics interactive areas 210), the I/O on the silicon substrate 130 around the optics interactive areas 210 is by metal interconnection structure 220(IMD) be connected to electronic pads 225; Metal interconnection structure 220(IMD) surface is provided with protective layer 230, and is formed with step-like projection or groove structure at protective layer 230; Be bonded together by polymer connector 140 between the first surface 201 of wafer 200 and the sheet glass 150, between sheet glass 150 and wafer 200, form cavity by exposure imaging technique; The second surface 202 of wafer 200 is provided with TSV hole 260, pass silicon substrate 130 by TSV hole 260 electronic pads 225 is connected to pad pad 175 above wafer 200 second surfaces 202, on 260 hole walls of TSV hole, be manufactured with successively and make passivation layer 265 and clad lining 270, and with polymeric material TSV hole 260 is filled; Make welding resisting layer 180(SMF at wafer 200 second surfaces 202 at last), and soldered ball 190 is produced on the pad pad 175.
The material of described protective layer is silicon nitride.Described polymeric material is for to be comprised of resin, solvent, Photoactive compounds and additive etc.
A second aspect of the present invention has provided a kind of method of making described large chip size encapsulation, may further comprise the steps:
The first step: wafer is provided
Should comprise on the described wafer first surface and be formed with image sensing district and interconnect architecture electronic pads; Outermost layer protective layer on the wafer first surface is made the raised structures of step with the zone of glass bonding.
Perhaps the step raised structures on the described wafer first surface also can be groove structure.
Second step: in making polymer connecting material on glass
At first glass being carried out preliminary treatment cleans, preliminary treatment is cleaned and is comprised pickling neutralization, plasma cleaning etc., and then the bonding surface of glass coating one layer of polymeric glue, polymer latex is comprised of resin, solvent, Photoactive compounds and additive etc., forms cavity through techniques such as exposure imagings at polymer latex.
The 3rd step: glass carries out bonding with wafer
By at polymer spacers surface-coated one deck resin glue, then utilize bonding machine platform that glass isomorphous round key is combined together.
The 4th step: the wafer second surface grinds attenuate
By grinding at the wafer second surface wafer is carried out attenuate.
The 5th step: form the TSV hole at the wafer second surface
By at wafer second surface coating one deck photoresist, form the etching window by exposure imaging.Adopt dry method etch technology to form hole.Described dry method etch technology comprises deep reaction ion etching (DRIE).
The 6th step: the filling in TSV hole
At first in the TSV hole and the second surface of wafer form one deck passivation layer, and remove the passivation layer on electronic pads surface; Then make clad lining in passivation layer surface; Fill up at clad lining surface deposition one deck dielectric layer and with the TSV hole at last.
The 7th step: make line layer and soldered ball at the wafer second surface
By the dielectric layer to the wafer second surface expose, development and electroplating technology, form circuit layer at second surface, TSV is connected with the pad pad.Then soldered ball is produced on the pad pad.
In the described first step, step projection on the described wafer first surface or groove structure are after front road technique completes, by carry out the coating of polymer latex at the wafer first surface, form the etching window by exposure imaging, form required step projection or groove structure through the first surface that is etched in wafer.
In described the 3rd step, polymer latex can also be selected and be dry film (Dry Film), described dry film is by being comprised of resin, solvent, Photoactive compounds and additive etc., then can save on the polymer latex surface by being coated with this step process of bonded adhesives and finish bonding with wafer, used dry film just directly can carry out bonding with wafer without being coated with bonded adhesives, has reduced technological process.
In described the 4th step, described wafer reduction process also comprises the destressing plasma etching.After the wafer attenuate, by plasma etching, to remove because grinding remains in internal stress in the wafer, reduce the warpage of wafer, be convenient to simultaneously the carrying out of subsequent technique.
The present invention is by making projection or the groove structure of step at the wafer first surface, effectively increased glass with the bond strength between the wafer, improve glass with the layering between the wafer, improved the reliability of encapsulation, so that described encapsulation is applicable to larger sized chip size packages.On manufacture method, at first adopted dry film as the bonding material between glass and the wafer; Secondly the destressing plasma etching of taking after to the wafer attenuate can effectively be removed the internal stress that produces owing to grinding in the wafer, improves the warpage situation of wafer, thereby further facilitates later technological operation; Adopted at last the making metal substrate to utilize dielectric (such as polymer) to fill the technique in TSV hole but not expensive plating Cu technique.Also reduced production cost when in sum, these steps have reduced technological process and improved production efficiency.
Description of drawings
Fig. 1 is the structural representation of a traditional cmos sensor (CIS).
Fig. 2 is the structural representation of existing a cmos sensor (CIS).
Fig. 3 (a) is the detailed maps that encapsulates according to the cmos sensor (CIS) that embodiments of the invention are drawn, and wafer first surface bonding region has the raised structures of step.
Fig. 3 (b) is the detailed maps that encapsulates according to the cmos sensor (CIS) that embodiments of the invention are drawn, and wafer first surface bonding region has the groove structure of step.
Fig. 4 (a) be manufacturing process generalized section according to the cmos sensor (CIS) of embodiments of the invention draftings to (g).
Number in the figure: 1. framework, 2. ceramic bases, 3. bond layer, 4. integrated circuit; 5. image photosensitive area, the pad on 6.IC surface, 7. lead-in wire; 8. the pad of substrate surface, 9. bonding agent, 10. glass lens; 110. micro lens, 120. image sensing districts, 130. silicon substrates; 140. the polymer connector, 150. sheet glass, 160. heavy distribution layers; 170. the silicon through hole, 175. pad pads, 180. welding resisting layers; 190. soldered ball, 200. wafers, 201. first surfaces; 202, second surface, 210. optics interactive areas; 220. the metal interconnection structure, 225. electronic padses, 230. protective layers; 260.TSV the hole, 265. passivation layers, 270. clad linings.
Embodiment
The present invention comes reinforcing glass sheet 150 with the adhesion of wafer 200 by projection or the groove structure of making step at the first surface 201 of wafer 200, improved sheet glass 150 with the lamination problem between the wafer 200, improved the reliability of encapsulation and be fit to larger sized cmos sensor (CIS) encapsulation.Fig. 3 (a) and Fig. 3 (b) are respectively cmos sensor (CIS) the encapsulation schematic diagram at the step projection of wafer first surface 201 making and groove structure.
Shown in Fig. 3 (a), the encapsulation of the large chip size of embodiment of the present invention comprises wafer 200, and the front of described wafer 200 is for forming the first surface 201 in image sensing district, and the negative of described wafer 200 is second surface 202; The top center of described wafer 200 first surfaces 201 silicon substrates 130 is provided with optics interactive areas 210, be connected with metal interconnection structure 220(IMD in the one side that is provided with optics interactive areas 210), the I/O on the wafer 200 around the optics interactive areas 210 is by metal interconnection structure 220(IMD) be connected to electronic pads 225; Metal interconnection structure 220(IMD) surface is provided with protective layer 230(such as silicon nitride), and at protective layer 230(such as silicon nitride) be formed with step-like projection or groove structure; Protective layer 230(such as silicon nitride) upward and between the sheet glass 150 be bonded together by polymer connector 140, between sheet glass 150 and wafer 200, form cavity by exposure imaging technique; The second surface 202 of wafer 200 is provided with TSV hole 260, penetrate silicon substrate 130 by TSV hole 260 electronic pads 225 is connected to pad pad 175 above wafer 200 second surfaces 202, on 260 hole walls of TSV hole, be manufactured with successively and make passivation layer 265 and clad lining 270, and with polymeric material TSV hole 260 is filled; Make welding resisting layer 180(SMF at wafer 200 second surfaces 202 at last), and soldered ball 190 is produced on the pad pad 285.
Describe the manufacturing process of the cmos image sensor of the present embodiment in detail to (g) below in conjunction with Fig. 4 (a).Fig. 4 (a) be manufacturing process generalized section according to the cmos sensor of embodiments of the invention draftings to (g).
At first please refer to Fig. 4 (a), wafer 200 is provided, the front of described wafer 200 is for forming the first surface 201 in image sensing district, and the negative of described wafer 200 is second surface 202.Wafer 200 comprises: silicon substrate 130; Optics interactive areas 210 is formed at the central authorities of wafer 200 first surfaces 201 silicon substrates 130 tops; Making metal interconnection layer 220(IMD above the optics interactive areas 210) make the I/O(figure of optics interactive areas 210 peripheries upper not shown) with at metal interconnection layer 220(IMD) in electronic pads 225 be connected so that the image sensing district is with peripheral circuit generation electric connection; At metal interconnection layer 220(IMD) outside making protective layer 230(such as silicon nitride).Wherein on the protective layer (such as silicon nitride) 230 with sheet glass 150 bonding zones on the first surface 201, make in advance projection or the groove structure of step; Array has a plurality of photodiodes and a plurality of transistor (not shown)s that are connected respectively photodiode in the optics interactive areas 210.
Next please refer to Fig. 4 (b), at first polymer latex (being comprised of resin, solvent, Photoactive compounds and additive etc. such as photoresist) is utilized coating machine platform figure to be coated on the sheet glass 150 that cleans through preliminary treatment, by polymer latex is carried out exposure imaging, form cavity on polymer latex, remaining polymer latex is as the polymer connector 140 of bonding sheet glass 150 and wafer 200 bondings.Then be bonded together with wafer 200 by bonding machine platform sheet glass 150.
Next please refer to Fig. 4 (c), make TSV hole 260 at the second surface 202 of wafer, the TSV hole penetrates silicon substrate 130 and is communicated to electronic pads 225, so that electronic pads 225 can be realized being electrically connected by TSV hole 260 and wafer second surface 202.
When making TSV hole 260, following step is arranged: (a) silicon substrate 130 of wafer second surface 202 carried out attenuate, can the thickness of wafer 200 be down to about 130 microns from 600 ~ 700 microns by grinding technics; (b) wafer second surface 202 is carried out the destressing plasma etching, thereby remove the internal stress that produces owing to grinding in the wafer 200, improve the warpage of wafer 200, be convenient to subsequent technique and carry out; (c) form the etching window, by the wafer second surface 202 coating one deck photoresists behind attenuate, advance the etching window of the technique formation needs such as overexposure development; (d) etching in TSV hole 260 adopts dry method etch technology (such as deep reactive ion etch, DRIE) to form hole, electronic pads 225 is come out.The TSV hole 260 that forms is inclined hole, so that form passivation layer 265 in subsequent technique.The aperture that TSV hole 260 is connected with electronic pads 225 can more than or equal to or less than the width of electronic pads 225.Next please refer to Fig. 4 (d), make one deck passivation layer 265 at the second surface 202 of wafer, and remove the passivation layer on bottom electrical polar cushion 225 surfaces, to expose electronic pads 225.
Next please refer to Fig. 4 (e), to the making of TSV hole 260 hole inwalls and wafer second surface 202 enterprising row metal linings 270.
The making of clad lining 270 can be adopted the physical vapor deposition (PVD) of aluminium, sputter layer of metal lining 270 on the passivation layer 265 that previous step is made; Also can form by galvanoplastic the conductive substrates of layer of metal or alloy material at passivation layer 265.
Next please refer to Fig. 4 (f), hole is carried out the filling of dielectric filler (such as polymer) to finish TSV hole 260 structures; Carrying out etching by the clad lining 270 to wafer second surface 200b makes its patterning form line layer; On the line layer of making, be coated with one deck welding resisting layer 180(SMF) with the protection circuit layer; To welding resisting layer 180(SMF) carry out exposure imaging, make pad pad 175 in the precalculated position, TSV hole 260 and pad pad 175 are connected by line layer.Concrete steps comprise: (a) employing dielectric filler (such as polymer) is finished the filling to TSV hole 260; (b) form the etching window by exposure imaging technique at wafer second surface 202; clad lining 270 to wafer second surface 202 is etched with formation circuit distribution patterns; (c) form line layer by electroplating technology at wafer rear 202; (d) at wafer rear 202 coating welding resisting layer 180(SMF), by exposure imaging protection circuit layer and form pad pad 175.
Next please refer to Fig. 4 (g), with soldered ball 190, then by cutting machine the full wafer wafer is cut into single chip.
The description of the embodiment that the present invention carries out is that purpose is effectively explanation and describes the present invention, but by this only by example and should not be construed as the scope of the present invention that restriction is defined by claims.Technical staff under any this area can make possible change and modification without departing from the spirit and scope of the present invention.Protection therefore of the present invention covers essence of an invention and the interior modification of scope that claim defines.
Claims (6)
1. large chip size encapsulation, it is characterized in that: it includes wafer (200), and the front of described wafer (200) is for forming the first surface (201) in image sensing district, and the negative of described wafer (200) is second surface (202); The central authorities of silicon substrate 130 tops are provided with optics interactive areas (210) in described wafer (200) first surface (201), be connected with metal interconnection structure (220) in the one side that is provided with optics interactive areas (210), upper optics interactive areas (210) I/O on every side of silicon substrate (130) is connected to electronic pads (225) by metal interconnection structure (220); The surface of metal interconnection structure (220) is provided with protective layer (230), and is formed with step-like projection or groove structure at protective layer (230); Be bonded together by polymer connector (140) between the first surface (201) of wafer (200) and the sheet glass (150), be provided with the cavity that forms by exposure imaging technique between sheet glass (150) and the wafer (200); The second surface (202) of wafer (200) is provided with TSV hole (260), pass silicon substrate (130) by TSV hole (260) electronic pads (225) is connected to the top pad pad (175) of wafer (200) second surface (202), on the hole wall of TSV hole (260), be manufactured with successively and make passivation layer (265) and clad lining (270), and with polymer latex TSV hole (260) are filled; Be manufactured with welding resisting layer (180) on wafer (200) second surface (202), soldered ball 190 is produced on the pad pad (175).
2. large chip size encapsulation according to claim 1, it is characterized in that: the material of described protective layer (230) is silicon nitride; Polymer connector (140) is made of polymer latex; Described polymeric material is the material that comprises resin, solvent, Photoactive compounds and additive.
3. make the method that large chip size claimed in claim 1 encapsulates for one kind, it is characterized in that: may further comprise the steps:
The first step: wafer is provided;
Should comprise on the described wafer first surface and be formed with image sensing district and interconnect architecture electronic pads; Outermost layer protective layer on the wafer first surface is made the raised structures of step with the zone of glass bonding; Perhaps the step raised structures on the described wafer first surface is groove structure;
Second step: at making polymer connector on glass;
At first glass being carried out preliminary treatment cleans, preliminary treatment is cleaned and is comprised pickling neutralization, plasma cleaning, and then the bonding surface of glass coating one layer of polymeric glue, polymer latex includes resin, solvent, Photoactive compounds and additive, forms cavity through techniques such as exposure imagings at polymer latex;
The 3rd step: glass carries out bonding with wafer;
By at polymer connector surface-coated one deck resin glue, then utilize bonding machine platform that glass isomorphous round key is combined together;
The 4th step: the wafer second surface grinds attenuate;
By grinding at the wafer second surface wafer is carried out attenuate;
The 5th step: form the TSV hole at the wafer second surface;
By at wafer second surface coating one deck photoresist, form the etching window by exposure imaging; Adopt dry method etch technology to form hole; Described dry method etch technology comprises deep reaction ion etching;
The 6th step: the filling in TSV hole;
At first in the TSV hole and the second surface of wafer form one deck passivation layer, and remove the passivation layer on electronic pads surface; Then make clad lining in passivation layer surface; Fill up at clad lining surface deposition one deck dielectric layer and with the TSV hole at last;
The 7th step: make line layer and soldered ball at the wafer second surface;
By the dielectric layer to the wafer second surface expose, development and electroplating technology, form circuit layer at second surface, TSV is connected with the pad pad; Then soldered ball is produced on the pad pad.
4. a kind of method of making large chip size encapsulation according to claim 3, it is characterized in that: in the described first step, step projection on the described wafer first surface or groove structure are after front road technique completes, by carry out the coating of polymer latex at the wafer first surface, form the etching window by exposure imaging, form required step projection or groove structure through the first surface that is etched in wafer.
5. a kind of method of making large chip size encapsulation according to claim 3 is characterized in that: in described the 3rd step, polymer latex is replaced by dry film, described dry film comprises by by resin, solvent, Photoactive compounds and additive; Save on the polymer latex surface this moment by being coated with this step process of bonded adhesives and finish bonding with wafer, used dry film just directly carries out bonding with wafer without being coated with bonded adhesives.
6. a kind of method of making large chip size encapsulation according to claim 3, it is characterized in that: in described the 4th step, described wafer reduction process also comprises the destressing plasma etching; After the wafer attenuate, by plasma etching, to remove because grinding remains in internal stress in the wafer, reduce the warpage of wafer, be convenient to simultaneously the carrying out of subsequent technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210478706.XA CN103000648B (en) | 2012-11-22 | 2012-11-22 | Large chip sized package and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210478706.XA CN103000648B (en) | 2012-11-22 | 2012-11-22 | Large chip sized package and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103000648A true CN103000648A (en) | 2013-03-27 |
| CN103000648B CN103000648B (en) | 2016-03-09 |
Family
ID=47929026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210478706.XA Expired - Fee Related CN103000648B (en) | 2012-11-22 | 2012-11-22 | Large chip sized package and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103000648B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762198A (en) * | 2013-12-31 | 2014-04-30 | 中国科学院微电子研究所 | TSV pore filling method |
| CN104617029A (en) * | 2015-01-07 | 2015-05-13 | 中国电子科技集团公司第五十五研究所 | Method for improving semiconductor wafer bonding alignment precision |
| CN105731360A (en) * | 2014-12-09 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | MEMS sensor and preparation method of MEMS sensor |
| CN105826332A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN106365108A (en) * | 2015-07-23 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic apparatus |
| WO2017197831A1 (en) * | 2016-05-19 | 2017-11-23 | 深圳市汇顶科技股份有限公司 | Silicon through hole chip and manufacturing method therefor, fingerprint recognition sensor and terminal device |
| CN107946335A (en) * | 2017-12-22 | 2018-04-20 | 成都先锋材料有限公司 | A kind of CMOS image sensings encapsulating structure and preparation method thereof |
| US10199333B2 (en) | 2017-07-05 | 2019-02-05 | Omnivision Technologies, Inc. | Delamination-resistant semiconductor device and associated method |
| CN111090145A (en) * | 2018-10-23 | 2020-05-01 | 美光科技公司 | Semiconductor device with integrated optical component |
| CN112420603A (en) * | 2020-11-20 | 2021-02-26 | 中国科学院半导体研究所 | Preparation method of TSV-based MEMS sensor vertical electrical interconnection structure |
| CN113526454A (en) * | 2021-07-16 | 2021-10-22 | 芯知微(上海)电子科技有限公司 | MEMS packaging structure and manufacturing method thereof |
| CN115656789A (en) * | 2022-12-26 | 2023-01-31 | 惠州市金百泽电路科技有限公司 | Step bonding pad structure and testing method thereof |
| CN117013974A (en) * | 2023-10-08 | 2023-11-07 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
| CN117246973A (en) * | 2023-11-17 | 2023-12-19 | 苏州敏芯微电子技术股份有限公司 | Micro-electromechanical force sensor and preparation method thereof |
| CN113526454B (en) * | 2021-07-16 | 2024-04-19 | 芯知微(上海)电子科技有限公司 | MEMS packaging structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509636B1 (en) * | 2001-11-15 | 2003-01-21 | Siliconware Precision Industries Co., Ltd. | Semiconductor package |
| US20060180887A1 (en) * | 2005-02-15 | 2006-08-17 | Sharp Kabushiki Kaisha | Semiconductor device and production method thereof |
| CN101562191A (en) * | 2008-06-29 | 2009-10-21 | 天水华天科技股份有限公司 | Photoelectric packaging part with cavity and production method thereof |
| CN102637713A (en) * | 2012-03-31 | 2012-08-15 | 江阴长电先进封装有限公司 | Method for packaging image sensor comprising metal micro-bumps |
-
2012
- 2012-11-22 CN CN201210478706.XA patent/CN103000648B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6509636B1 (en) * | 2001-11-15 | 2003-01-21 | Siliconware Precision Industries Co., Ltd. | Semiconductor package |
| US20060180887A1 (en) * | 2005-02-15 | 2006-08-17 | Sharp Kabushiki Kaisha | Semiconductor device and production method thereof |
| CN101562191A (en) * | 2008-06-29 | 2009-10-21 | 天水华天科技股份有限公司 | Photoelectric packaging part with cavity and production method thereof |
| CN102637713A (en) * | 2012-03-31 | 2012-08-15 | 江阴长电先进封装有限公司 | Method for packaging image sensor comprising metal micro-bumps |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762198B (en) * | 2013-12-31 | 2016-07-06 | 中国科学院微电子研究所 | A kind of TSV filling perforation method |
| CN103762198A (en) * | 2013-12-31 | 2014-04-30 | 中国科学院微电子研究所 | TSV pore filling method |
| CN105731360A (en) * | 2014-12-09 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | MEMS sensor and preparation method of MEMS sensor |
| CN105731360B (en) * | 2014-12-09 | 2017-10-10 | 中芯国际集成电路制造(上海)有限公司 | MEMS sensor and preparation method thereof |
| CN104617029A (en) * | 2015-01-07 | 2015-05-13 | 中国电子科技集团公司第五十五研究所 | Method for improving semiconductor wafer bonding alignment precision |
| CN105826332A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN106365108A (en) * | 2015-07-23 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic apparatus |
| WO2017197831A1 (en) * | 2016-05-19 | 2017-11-23 | 深圳市汇顶科技股份有限公司 | Silicon through hole chip and manufacturing method therefor, fingerprint recognition sensor and terminal device |
| US10199333B2 (en) | 2017-07-05 | 2019-02-05 | Omnivision Technologies, Inc. | Delamination-resistant semiconductor device and associated method |
| US10692907B2 (en) | 2017-12-22 | 2020-06-23 | Pioneer Materials Inc. Chengdu | CMOS image sensor encapsulation structure and method for manufacturing the same |
| CN107946335A (en) * | 2017-12-22 | 2018-04-20 | 成都先锋材料有限公司 | A kind of CMOS image sensings encapsulating structure and preparation method thereof |
| CN111090145A (en) * | 2018-10-23 | 2020-05-01 | 美光科技公司 | Semiconductor device with integrated optical component |
| US11114383B2 (en) | 2018-10-23 | 2021-09-07 | Micron Technology, Inc. | Semiconductor devices having integrated optical components |
| US11728276B2 (en) | 2018-10-23 | 2023-08-15 | Micron Technology, Inc. | Semiconductor devices having integrated optical components |
| CN112420603A (en) * | 2020-11-20 | 2021-02-26 | 中国科学院半导体研究所 | Preparation method of TSV-based MEMS sensor vertical electrical interconnection structure |
| CN113526454A (en) * | 2021-07-16 | 2021-10-22 | 芯知微(上海)电子科技有限公司 | MEMS packaging structure and manufacturing method thereof |
| CN113526454B (en) * | 2021-07-16 | 2024-04-19 | 芯知微(上海)电子科技有限公司 | MEMS packaging structure and manufacturing method thereof |
| CN115656789A (en) * | 2022-12-26 | 2023-01-31 | 惠州市金百泽电路科技有限公司 | Step bonding pad structure and testing method thereof |
| CN115656789B (en) * | 2022-12-26 | 2024-04-09 | 惠州市金百泽电路科技有限公司 | Step bonding pad structure and testing method thereof |
| CN117013974A (en) * | 2023-10-08 | 2023-11-07 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
| CN117013974B (en) * | 2023-10-08 | 2024-01-30 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
| CN117246973A (en) * | 2023-11-17 | 2023-12-19 | 苏州敏芯微电子技术股份有限公司 | Micro-electromechanical force sensor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103000648B (en) | 2016-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103021983B (en) | Wafer level chip size package and manufacturing method thereof | |
| CN103000648B (en) | Large chip sized package and manufacture method thereof | |
| CN103000649B (en) | A kind of cmos image sensor encapsulating structure and manufacture method thereof | |
| KR102055840B1 (en) | Image sensor package | |
| CN101419952B (en) | Wafer stage chip encapsulation method and encapsulation construction | |
| US8552518B2 (en) | 3D integrated microelectronic assembly with stress reducing interconnects | |
| US7964926B2 (en) | Image sensing devices including image sensor chips, image sensor package modules employing the image sensing devices, electronic products employing the image sensor package modules, and methods of fabricating the same | |
| CN102856336B (en) | Wafer encapsulation body and forming method thereof | |
| KR101420934B1 (en) | Wire bond interposer package for cmos image sensor and method of making same | |
| KR100866619B1 (en) | Image sensor module of wafer level and manufacturing method thereof, and camera module | |
| CN102820282A (en) | 3D integration microelectronic assembly for integrated circuit devices and method of making same | |
| CN104054164A (en) | Semiconductor device and method for manufacturing same | |
| KR20120036259A (en) | Solid-state imaging device and manufacturing method thereof and electronic apparatus | |
| TW201624683A (en) | Photosensitive module and method for forming the same | |
| CN210897268U (en) | Photoelectric chip three-dimensional packaging structure with optical interconnection interface | |
| CN103413815A (en) | Wafer level image sensor encapsulation structure and wafer level image sensor encapsulation method | |
| CN105070732B (en) | High pixel image sensor package and preparation method thereof | |
| US20090014827A1 (en) | Image sensor module at wafer level, method of manufacturing the same, and camera module | |
| CN105023931A (en) | Backside illuminated image chip module structure and fabrication method thereof | |
| CN101996899A (en) | Cmos image sensor and manufacturing method thereof | |
| CN107221516B (en) | A kind of air-tightness image chip encapsulating structure and preparation method thereof | |
| CN104037146A (en) | Packaging structure and packaging method | |
| CN104393009B (en) | High-reliability image sensor encapsulation structure comprising silicon through hole | |
| CN203398116U (en) | Packaging structure for wafer-level image sensor | |
| WO2010131391A1 (en) | Semiconductor device and electronic device provided with same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160309 Termination date: 20191122 |