CN210897268U - Photoelectric chip three-dimensional packaging structure with optical interconnection interface - Google Patents
Photoelectric chip three-dimensional packaging structure with optical interconnection interface Download PDFInfo
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- CN210897268U CN210897268U CN201922309483.4U CN201922309483U CN210897268U CN 210897268 U CN210897268 U CN 210897268U CN 201922309483 U CN201922309483 U CN 201922309483U CN 210897268 U CN210897268 U CN 210897268U
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Abstract
The utility model discloses a three-dimensional packaging structure of photoelectricity chip with light interconnection interface, include: the optical chip comprises an optical interconnection structure and a groove at one end; a conductive via that penetrates the optical chip; the first wiring layer is arranged on the front surface of the optical chip and is electrically connected with the conductive through hole; the second wiring layer is arranged on the back surface of the optical chip and is electrically connected with the conductive through hole; an electrical chip disposed over the optical chip front side and electrically connected to the first wiring layer; the cover plate is arranged above the optical interaction structure of the optical chip and the groove; the plastic packaging layer is used for integrally and plastically packaging the front surface of the optical chip, the electric chip and the cover plate; and the external solder balls are arranged below the back surface of the optical chip and are electrically connected with the second wiring layer.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a three-dimensional packaging structure of photoelectricity chip with light interconnection interface.
Background
With the increasing communication data volume, the optical module transmission rate is required to be higher, and the standard rate of the next generation optical interconnect is 56Gbps and 112 Gbps. In the case of high-speed interconnects, transmission loss, crosstalk, and reflection caused by the interconnect wires between chips are not negligible, and parasitic inductance of the interconnect wires also greatly affects performance. Therefore, the shorter the interconnect between the optical chip and the electrical chip, the better the interconnect, and preferably the flip chip interconnect.
The existing packaging mode of the photoelectric chip is to tile the silicon photoelectric chip and the electric chip on a substrate, interconnect in a routing or flip-chip mode, and do not carry out plastic package. Or the cell chip is overlapped on the silicon optical chip to form a three-dimensional interconnection structure, the optical coupling part is still bonded on the cell chip in an optical fiber or FA mode, and the whole package is not subjected to plastic package.
With the development of silicon optical technology, an optical device and an electrode can be simultaneously manufactured on a silicon optical chip through a CMOS (complementary metal oxide semiconductor) process, and can be easily interconnected with an electric chip, and the reliability of packaging interconnection can be ensured through plastic packaging. Therefore, people hope to package the silicon optical chip and the electrical chip by adopting a common plastic package mode, but the optical coupling position of the silicon optical chip cannot be polluted, and a coupling space is required to be reserved, which is another problem.
There is the reliability that can't carry out plastic envelope, encapsulation interconnect relatively poor, the packaging area is great and the performance relatively poor scheduling problem to current photoelectric chip packaging mode, the utility model provides a photoelectric chip three-dimensional packaging structure with optical interconnection interface and manufacturing method thereof adopts and piles up electric chip and optical chip and then carry out the plastic envelope, has guaranteed the reliability of encapsulation interconnect, can realize optical chip's optical coupling again simultaneously, has realized shorter electric interconnection, littleer packaging area to higher performance has been realized.
SUMMERY OF THE UTILITY MODEL
There is the relatively poor, great and the relatively poor scheduling problem of performance of reliability that can't carry out plastic envelope, encapsulation interconnection to current photoelectric chip packaging mode, according to the utility model discloses an embodiment provides a photoelectric chip three-dimensional packaging structure with optical interconnection interface, include:
the optical chip comprises an optical interconnection structure and a groove at one end;
a conductive via that penetrates the optical chip;
the first wiring layer is arranged on the front surface of the optical chip and is electrically connected with the conductive through hole;
the second wiring layer is arranged on the back surface of the optical chip and is electrically connected with the conductive through hole;
an electrical chip disposed over the optical chip front side and electrically connected to the first wiring layer;
the cover plate is arranged above the optical interaction structure of the optical chip and the groove;
the plastic packaging layer is used for integrally and plastically packaging the front surface of the optical chip, the electric chip and the cover plate; and
and the external solder balls are arranged below the back surface of the optical chip and are electrically connected with the second wiring layer.
In one embodiment of the present invention, an end of the cover plate leaks out of the molding layer, and forms a hollow optical coupling structure together with the optical interconnection structure and the groove.
In one embodiment of the present invention, the optical chip is a laser or a modulator or a detector or an integrated optical chip with an optical interconnect structure.
In one embodiment of the present invention, the optical interconnect structure is a grating, a spot-size converter or a waveguide structure.
In one embodiment of the present invention, the electrical chip is flip-chip bonded on the first wiring layer; or the electric chip is positively mounted on the front surface of the optical chip and is electrically connected to the first wiring layer through wire bonding.
In an embodiment of the present invention, the hollow optical coupling structure is further provided with an optical fiber coupling efficiency enhancing structure coupled with the optical interconnection structure.
In one embodiment of the present invention, the optical fiber coupling efficiency enhancing structure is a lens or an isolator.
In another embodiment of the present invention, a method for manufacturing a three-dimensional package structure of an optoelectronic chip with an optical interconnection interface is provided, including:
forming an optical interconnection structure at a position of an optical chip wafer, which needs to be optically coupled, and manufacturing a groove between two adjacent chips;
preparing a metal through hole and a rewiring layer on an optical chip wafer;
assembling an electric chip and a cover plate on the top surface of the optical chip wafer;
carrying out plastic package on the top surface of the optical chip wafer;
forming an external solder ball below the wiring layer on the back of the optical chip wafer; and
the division forms a single package structure.
In another embodiment of the present invention, the fabricating metal vias and redistribution layers on an optical chip wafer further comprises:
forming a blind hole downwards from the front surface of the optical chip wafer;
forming metal through hole filling in the blind holes;
thinning the back of the optical chip wafer to realize the back leakage of the conductive through hole;
forming a wiring layer on the front surface of the optical chip wafer; and
and forming a wiring layer on the back surface of the optical chip.
In another embodiment of the present invention, the electrical chip is assembled on the top surface of the optical chip wafer by flip-chip bonding on the wiring layer, or by mounting the electrical chip on the front surface of the optical chip, and electrically connecting to the wiring layer by wire bonding.
The utility model provides a photoelectric chip three-dimensional packaging structure with an optical interconnection interface and a manufacturing method thereof, firstly, an optical interconnection structure and a groove are manufactured at the edge of a silicon photoelectric chip; next, forming a metal through hole penetrating through the upper surface and the lower surface in the silicon optical chip, and forming a wiring layer electrically connected with the metal through hole on the upper surface and the lower surface; then, stacking the electric chip and the cover plate patch on the silicon optical chip, and forming a hollow optical coupling structure between the electric chip and the cover plate; and then, carrying out plastic package on the packaging structure on the upper surface of the silicon optical chip, and forming an external solder ball electrically connected with a wiring layer on the lower surface of the silicon optical chip, thereby forming the three-dimensional packaging structure of the photoelectric chip with the optical interconnection interface. Based on the utility model discloses a this three-dimensional packaging structure of photoelectric chip with light interconnection interface adopts and piles up electric chip and optical chip and carry out the plastic envelope after, has guaranteed the reliability of encapsulation interconnection, can realize optical chip's optical coupling again simultaneously, has realized shorter electric interconnection, littleer packaging area to higher performance has been realized.
Drawings
To further clarify the above and other advantages and features of various embodiments of the present invention, a more particular description of various embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a schematic cross-sectional view of an optoelectronic chip three-dimensional package structure 100 with an optical interconnect interface according to an embodiment of the present invention.
Fig. 2 shows a schematic cross-sectional view 200 of the three-dimensional package structure 100 with an optical interconnection interface for optical coupling with an external optical fiber according to an embodiment of the present invention.
Fig. 3A to 3F are schematic cross-sectional views illustrating a process of forming the optoelectronic chip three-dimensional package structure 100 with an optical interconnection interface according to an embodiment of the present invention.
Fig. 4 shows a flowchart 400 for forming the optoelectronic chip three-dimensional package structure 100 with optical interconnect interface according to an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of an optoelectronic chip three-dimensional package structure 500 with an optical interconnect interface according to another embodiment of the present invention.
Fig. 6 shows a schematic cross-sectional view 600 of an optical coupling between the optoelectronic chip three-dimensional package structure 500 with an optical interconnection interface and an external optical fiber according to another embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of an optoelectronic chip three-dimensional package structure 700 with an optical interconnect interface according to still another embodiment of the present invention.
Fig. 8 shows a schematic cross-sectional view 800 of an optical coupling between the optoelectronic chip three-dimensional package structure 700 with an optical interconnection interface and an external optical fiber according to still another embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, the embodiments of the present invention describe the process steps in a specific order, however, this is only for the convenience of distinguishing the steps, and not for limiting the sequence of the steps.
The utility model provides a photoelectric chip three-dimensional packaging structure with an optical interconnection interface and a manufacturing method thereof, firstly, an optical interconnection structure and a groove are manufactured at the edge of a silicon photoelectric chip; next, forming a metal through hole penetrating through the upper surface and the lower surface in the silicon optical chip, and forming a wiring layer electrically connected with the metal through hole on the upper surface and the lower surface; then, stacking the electric chip and the cover plate patch on the silicon optical chip, and forming a hollow optical coupling structure between the electric chip and the cover plate; and then, carrying out plastic package on the packaging structure on the upper surface of the silicon optical chip, and forming an external solder ball electrically connected with a wiring layer on the lower surface of the silicon optical chip, thereby forming the three-dimensional packaging structure of the photoelectric chip with the optical interconnection interface. Based on the utility model discloses a this three-dimensional packaging structure of photoelectric chip with light interconnection interface adopts and piles up electric chip and optical chip and carry out the plastic envelope after, has guaranteed the reliability of encapsulation interconnection, can realize optical chip's optical coupling again simultaneously, has realized shorter electric interconnection, littleer packaging area to higher performance has been realized.
An optoelectronic chip three-dimensional package structure with an optical interconnection interface according to an embodiment of the present invention is described in detail below with reference to fig. 1. Fig. 1 shows a schematic cross-sectional view of an optoelectronic chip three-dimensional package structure 100 with an optical interconnect interface according to an embodiment of the present invention. As shown in fig. 1, the three-dimensional package structure 100 of the optoelectronic chip with the optical interconnection interface further includes an optical chip 110, a conductive via 120, a first wiring layer 130, a second wiring layer 140, an electrical chip 150, a cover plate 160, a molding layer 170, an external solder ball 180, an optical interconnection structure 111, and an optical coupling structure 190.
The optical chip 110 may be an active optoelectronic chip such as a laser, a modulator, a detector, etc., or an optoelectronic integrated chip with multiple structures, and the material thereof may be a silicon optical chip, or a semiconductor material of indium, gallium, arsenic, phosphorus compound, or a silicon carbide or silicon nitride material. There is also an optical interconnect structure 111 at the edge of the optical chip 110, and the optical interconnect structure 111 may be a grating, a spot-size converter or a waveguide structure.
The conductive via 120 is penetratingly disposed in the optical chip 110. In one embodiment of the present invention, the conductive via 120 is a standard TSV conductive via, and the via fill material is copper metal formed by electroplating.
The first wiring layer 130 is disposed over the photonic chip 110 and electrically connected to the conductive vias 120 to redistribute the chip pad locations. In an embodiment of the present invention, the first wiring layer 130 may be a single-layer wiring layer or a multi-layer wiring layer, and a dielectric layer is further disposed between the same-layer wiring layer and between adjacent-layer metals, thereby playing the role of insulation and protection.
The second wiring layer 140 is disposed under the photonic chip 110, electrically connected to the conductive via 120, and provided with an external connection pad on the outermost wiring layer. In an embodiment of the present invention, the second wiring layer 140, similar to the first wiring layer 130, may also be a single-layer wiring layer or a multi-layer wiring layer, and a dielectric layer is further disposed between the same-layer wiring layer and between adjacent layers, so as to perform the insulation and protection functions.
The electrical chip 150 is a chip requiring interconnection, associated with the optical chip 110, and includes a driving chip, an amplifying chip, a signal processing chip, an ASIC chip, a power supply chip, and the like. The electrical chip 150 is flip-chip bonded or wire bonded to the first wiring layer 130 on the upper surface of the optical chip.
The cover plate 160 is fixedly disposed over the optical interconnect structure 111 at the edge of the optical chip 110. In one embodiment of the present invention, the material of the cover plate 160 may be glass, silicon, organic material, etc.
The molding compound layer 170 covers the upper surface of the optical chip 110, and covers the first wiring layer 130, the electrical chip 150, and the cover plate 160.
The optical coupling structure 190 is a hollow structure, and is formed by a groove at the edge of the optical chip 110, the optical interconnection structure 111, and the cover plate 160. The optical fiber is used for aligning and connecting with an external optical fiber to realize the function of optical coupling.
Fig. 2 shows a schematic cross-sectional view 200 of the three-dimensional package structure 100 with an optical interconnection interface for optical coupling with an external optical fiber according to an embodiment of the present invention. As shown in fig. 2, the structure 200 for optically coupling the optoelectronic chip three-dimensional package structure 100 with the optical interconnection interface and the external optical fiber further includes an optoelectronic chip three-dimensional package structure 210/100 with an optical interconnection interface, a substrate 220, an optical fiber 230, and an optical fiber coupler 240. The three-dimensional photoelectric chip packaging structure 210/100 with the optical interconnection interface and the optical fiber coupler 240 are fixedly arranged on the substrate 220, and the optical fiber 230 is aligned and coupled to the optical coupling structure 190 of the three-dimensional photoelectric chip packaging structure 210/100 with the optical interconnection interface through the optical fiber coupler 240, so that high-efficiency optical signal coupling connection is realized.
A method for forming the optoelectronic chip three-dimensional package structure 100 with an optical interconnection interface according to an embodiment of the present invention is described in detail below with reference to fig. 3A to 3F and fig. 4. Fig. 3A to 3F are schematic cross-sectional views illustrating a process of forming the optoelectronic chip three-dimensional package structure 100 with an optical interconnection interface according to an embodiment of the present invention; fig. 4 shows a flowchart 400 for forming the optoelectronic chip three-dimensional package structure 100 with optical interconnect interface according to an embodiment of the present invention.
First, at step 410, as shown in FIG. 3A, an optical interconnect structure is formed at a location of an optical chip wafer where optical coupling is desired, and a recess is formed between two adjacent chips. The optical interconnect structure may be a grating, a spot-size converter or a waveguide structure; the recess is formed by etching according to the setting and is part of the optical coupling structure of the package structure.
Next, at step 420, metal vias and re-wiring layers are fabricated on the optical chip wafer, as shown in FIG. 3B. The utility model discloses a concrete embodiment, form from the downward blind hole in optical chip wafer front through laser through-hole, mechanical through-hole or sculpture through-hole technology, the metal through-hole that forms is filled to rethread electroplating, and rethread optical chip wafer back attenuate realizes that the back of electrically conductive through-hole spills, is carrying out the wiring layer at the front and the back and is making. In another embodiment of the present invention, the wiring layers on the front and back sides of the optical chip wafer may be single-layered or multi-layered.
Then, at step 430, the electrical chips and cover plate are assembled on the top surface of the photonic chip wafer, as shown in FIG. 3C. In an embodiment of the present invention, the electrical chip is soldered and attached to the top surface of the optical chip wafer by flip-chip bonding or wire bonding, and is electrically connected to the wiring layer and further electrically connected to the metal through hole inside the optical chip. The cover plate can be fixedly arranged at the corresponding position above the groove of the optical chip through the processes of pasting, bonding and the like.
Next, in step 440, as shown in fig. 3D, the top surface of the optical chip wafer is subjected to plastic packaging. The plastic packaging layer covers the upper surface of the optical chip and covers the top wiring layer, the electric chip and the cover plate.
Then, in step 450, as shown in fig. 3E, external solder balls are formed under the wiring layer on the back side of the optical chip wafer. In one embodiment of the present invention, the bump (bump) or the conductive copper pillar (copperpilar) may be formed by electroplating, and the BGA solder ball may be formed by a ball-mounting process.
Finally, at step 460, individual package structures are singulated as shown in fig. 3F.
An optoelectronic chip three-dimensional package structure with an optical interconnection interface according to another embodiment of the present invention is described in detail below with reference to fig. 5. Fig. 5 is a schematic cross-sectional view of an optoelectronic chip three-dimensional package structure 500 with an optical interconnect interface according to another embodiment of the present invention. As shown in fig. 5, the three-dimensional package structure 500 of the optoelectronic chip with optical interconnection interface further includes an optical chip 510, a conductive via 520, a first wiring layer 530, a second wiring layer 540, an electrical chip 550, a cover plate 560, a molding layer 570, external solder balls 580, an optical interconnection structure 511, and an optical coupling structure 590.
The three-dimensional package structure 500 of the optoelectronic chip with the optical interconnection interface is different from the three-dimensional package structure 100 of the optoelectronic chip with the optical interconnection interface only in the shape of the cover plate 560, thereby resulting in a different shape of the optical coupling structure.
Fig. 6 shows a schematic cross-sectional view 600 of an optical coupling between the optoelectronic chip three-dimensional package structure 500 with an optical interconnection interface and an external optical fiber according to another embodiment of the present invention. As shown in fig. 6, the structure 600 for optically coupling the optoelectronic chip three-dimensional package structure 500 with the optical interconnection interface and the external optical fiber further includes an optoelectronic chip three-dimensional package structure 610/500 with an optical interconnection interface, a substrate 620, an optical fiber 630, and an optical fiber coupler 640. The three-dimensional optoelectronic chip packaging structure 610/500 with the optical interconnection interface and the optical fiber coupler 640 are fixedly arranged on the substrate 620, and the optical fiber 630 is aligned to the optical coupling structure 590 of the three-dimensional optoelectronic chip packaging structure 610/500 with the optical interconnection interface through the optical fiber coupler 640, but does not enter the optical coupling structure 590, so that high-efficiency optical signal coupling connection is realized.
A three-dimensional package structure of an optoelectronic chip with an optical interconnection interface according to another embodiment of the present invention is described in detail below with reference to fig. 7. Fig. 7 is a schematic cross-sectional view of an optoelectronic chip three-dimensional package structure 700 with an optical interconnect interface according to still another embodiment of the present invention. As shown in fig. 7, the three-dimensional package structure 700 of the optoelectronic chip with the optical interconnection interface further includes an optical chip 710, a conductive via 720, a first wiring layer 730, a second wiring layer 740, an electronic chip 750, a cover plate 760, a molding layer 770, an external solder ball 780, an optical interconnection structure 711, an optical coupling structure 790 and a fiber coupling efficiency enhancing structure 795.
The three-dimensional package structure 700 of the optoelectronic chip with the optical interconnection interface is different from the three-dimensional package structure 100 of the optoelectronic chip with the optical interconnection interface only in that an optical fiber coupling efficiency enhancing structure 795 is added to the optical coupling structure 790, and the optical fiber coupling efficiency enhancing structure 795 may be a lens or an isolator.
Fig. 8 shows a schematic cross-sectional view 800 of an optical coupling between the optoelectronic chip three-dimensional package structure 700 with an optical interconnection interface and an external optical fiber according to still another embodiment of the present invention. As shown in fig. 8, the structure 800 for optically coupling the optoelectronic chip three-dimensional package structure 700 with the optical interconnection interface and the external optical fiber further includes an optoelectronic chip three-dimensional package structure 810/700 with an optical interconnection interface, a substrate 820, an optical fiber 830, and an optical fiber coupler 840. The three-dimensional photoelectric chip packaging structure 810/700 with the optical interconnection interface and the optical fiber coupler 840 are fixedly arranged on the substrate 820, and the optical fiber 830 is aligned to the optical fiber coupling efficiency enhancing structure 795 and the optical coupling structure 790 of the three-dimensional photoelectric chip packaging structure 810/700 with the optical interconnection interface through the optical fiber coupler 840, but does not enter the optical coupling structure 790, so that high-efficiency optical signal coupling connection is realized.
Based on the photoelectric chip three-dimensional packaging structure with the optical interconnection interface and the manufacturing method thereof provided by the utility model, firstly, the optical interconnection structure and the groove are manufactured at the edge of the silicon optical chip; next, forming a metal through hole penetrating through the upper surface and the lower surface in the silicon optical chip, and forming a wiring layer electrically connected with the metal through hole on the upper surface and the lower surface; then, stacking the electric chip and the cover plate patch on the silicon optical chip, and forming a hollow optical coupling structure between the electric chip and the cover plate; and then, carrying out plastic package on the packaging structure on the upper surface of the silicon optical chip, and forming an external solder ball electrically connected with a wiring layer on the lower surface of the silicon optical chip, thereby forming the three-dimensional packaging structure of the photoelectric chip with the optical interconnection interface. Based on the utility model discloses a this three-dimensional packaging structure of photoelectric chip with light interconnection interface adopts and piles up electric chip and optical chip and carry out the plastic envelope after, has guaranteed the reliability of encapsulation interconnection, can realize optical chip's optical coupling again simultaneously, has realized shorter electric interconnection, littleer packaging area to higher performance has been realized.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (7)
1. The utility model provides a three-dimensional packaging structure of photoelectricity chip with optical interconnection interface which characterized in that includes:
the optical chip comprises an optical interconnection structure and a groove at one end;
a conductive via that penetrates the optical chip;
the first wiring layer is arranged on the front surface of the optical chip and is electrically connected with the conductive through hole;
the second wiring layer is arranged on the back surface of the optical chip and is electrically connected with the conductive through hole;
an electrical chip disposed over the optical chip front side and electrically connected to the first wiring layer;
the cover plate is arranged above the optical interaction structure of the optical chip and the groove;
the plastic packaging layer is used for integrally and plastically packaging the front surface of the optical chip, the electric chip and the cover plate; and
and the external solder balls are arranged below the back surface of the optical chip and are electrically connected with the second wiring layer.
2. The optoelectronic chip three-dimensional package structure with optical interconnect interface of claim 1, wherein an end of the cover plate leaks out of the molding layer to form a hollow optical coupling structure together with the optical interconnect structure and the recess.
3. The optoelectronic chip three-dimensional package structure with optical interconnect interface of claim 1, wherein the optical chip is a laser or a modulator or a detector or an integrated optical chip with optical interconnect structure.
4. The optoelectronic chip three-dimensional package structure with optical interconnect interface of claim 1, wherein the optical interconnect structure is a grating, a spot-size converter, or a waveguide structure.
5. The optoelectronic chip three-dimensional package structure with optical interconnect interface of claim 1, wherein the electrical chip is flip-chip bonded on the first wiring layer; or the electric chip is positively mounted on the front surface of the optical chip and is electrically connected to the first wiring layer through wire bonding.
6. The optoelectronic chip three-dimensional package structure with optical interconnect interface of claim 2, wherein the hollow optical coupling structure is further provided with a fiber coupling efficiency enhancing structure coupled to the optical interconnect structure.
7. The optoelectronic chip three-dimensional package structure with optical interconnect interface of claim 6, wherein the fiber coupling efficiency enhancing structure is a lens or an isolator.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512589A (en) * | 2022-04-21 | 2022-05-17 | 威海三维曲板智能装备有限公司 | Photoelectric hybrid packaging structure and manufacturing method thereof |
| CN115166913A (en) * | 2022-06-29 | 2022-10-11 | 中国科学院西安光学精密机械研究所 | Wavelength division multiplexing common-package optical interconnection architecture based on microring |
| WO2024066360A1 (en) * | 2022-09-30 | 2024-04-04 | 青岛海信宽带多媒体技术有限公司 | Optical module |
-
2019
- 2019-12-20 CN CN201922309483.4U patent/CN210897268U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512589A (en) * | 2022-04-21 | 2022-05-17 | 威海三维曲板智能装备有限公司 | Photoelectric hybrid packaging structure and manufacturing method thereof |
| CN114512589B (en) * | 2022-04-21 | 2022-06-17 | 威海三维曲板智能装备有限公司 | Photoelectric hybrid packaging structure and manufacturing method thereof |
| CN115166913A (en) * | 2022-06-29 | 2022-10-11 | 中国科学院西安光学精密机械研究所 | Wavelength division multiplexing common-package optical interconnection architecture based on microring |
| CN115166913B (en) * | 2022-06-29 | 2024-05-10 | 中国科学院西安光学精密机械研究所 | Wavelength division multiplexing co-packaging optical interconnection architecture based on micro-ring |
| WO2024066360A1 (en) * | 2022-09-30 | 2024-04-04 | 青岛海信宽带多媒体技术有限公司 | Optical module |
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