CN114823358A - Manufacturing method of packaging structure and packaging structure - Google Patents
Manufacturing method of packaging structure and packaging structure Download PDFInfo
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- CN114823358A CN114823358A CN202210272769.3A CN202210272769A CN114823358A CN 114823358 A CN114823358 A CN 114823358A CN 202210272769 A CN202210272769 A CN 202210272769A CN 114823358 A CN114823358 A CN 114823358A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
- Optical Couplings Of Light Guides (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a manufacturing method of a packaging structure and the packaging structure, wherein the method comprises the following steps: the semiconductor wafer comprises a plurality of first semiconductor chips, the plurality of first semiconductor chips on the semiconductor wafer form an integral structure, and for each first semiconductor chip, an optical coupling area protection ring surrounding an optical coupling area is manufactured on a non-optical coupling area of the first semiconductor chip, so that when a plastic package layer is manufactured on the non-optical coupling area of the first semiconductor chip, the upper surface of the optical coupling area is not covered by the plastic package layer, the optical coupling interface in the optical coupling area is protected from being polluted by organic matters in the plastic package layer, the surface purity of the optical coupling area is ensured, and the subsequent optical coupling interface can maintain high coupling efficiency with an optical fiber array.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and in particular, to a method for manufacturing a package structure and a package structure.
Background
With the increasing development of semiconductor technology, a package structure having a high integration density is more and more important. For example, the 3D package structure can be used to realize mutual stacking between chips.
At present, in an existing silicon optical chip, an Electrical Integrated Chip (EIC) and an optical chip (PIC) adopt different wafer generation process, and chip-level interconnection (for example, wire bonding or flip interconnection) is adopted to realize connection between the electrical chip (EIC) and the optical chip (PIC), so as to form a three-dimensional interconnection structure.
In the three-dimensional packaging of the optical chip (PIC) and the electrical chip (EIC), in order to avoid warpage caused by thinning the optical chip (PIC) and thus cause dislocation or failure of the connection point of the optical chip (PIC) and the electrical chip (EIC), or in order to make the packaging of the optical chip (PIC) and the electrical chip (EIC) have higher strength, a plastic packaging layer is generally required to be formed on the surface of the optical chip (PIC). However, the optical chip (PIC) has an optical fiber coupling interface for inputting light, and directly plastic-encapsulating the surface of the PIC may cause damage to the optical fiber coupling interface, thereby causing a significant increase in insertion loss of the optical fiber coupling interface and affecting the practical use of the optoelectronic chip.
The traditional 3D photoelectric chip without plastic package has the disadvantages of excessive warpage and low yield in the process of stacking multiple layers of chips, cannot be applied to stacking between a large-sized photonic integrated circuit chip and an electronic integrated circuit chip, and is also not beneficial to mounting of an ultrathin photonic integrated circuit chip with a Through Silicon Via (TSV) structure.
Disclosure of Invention
In order to overcome the defects of the prior art, an object of the present invention is to provide a method for manufacturing a package structure and a package structure, which can protect an optical fiber coupling interface on an optical chip while fixing a optoelectronic integrated chip with a plastic package material to improve the package strength and avoid warpage of the optical chip.
The purpose of the invention is realized by adopting the following technical scheme:
according to an aspect of the present invention, there is provided a method for manufacturing a package structure, the method including:
providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of first semiconductor chips, each first semiconductor chip is provided with a first surface and a second surface which are opposite, the first surface is provided with a light coupling area and a non-light coupling area which surrounds the light coupling area, and a light coupling interface is arranged in the light coupling area; providing at least one second semiconductor chip and an optical coupling region protection ring corresponding to each first semiconductor chip, and fixing the at least one second semiconductor chip and the optical coupling region protection ring on the non-optical coupling region of the first surface of the first semiconductor chip respectively, wherein the optical coupling region protection ring surrounds the optical coupling region; and manufacturing a plastic package layer, wherein the plastic package layer coats the at least one second semiconductor chip and the outer surface of the optical coupling area protection ring, which is far away from the optical coupling area, and does not cover the area occupied by the optical coupling area protection ring.
Further, in a direction perpendicular to the first surface, a top surface of the optical coupling region guard ring away from the first surface is flush with a top surface of the at least one second semiconductor chip away from the first surface.
Further, the manufacturing of the plastic package layer comprises: providing a plastic package mold, wherein the plastic package mold is provided with a plurality of U-shaped cavities corresponding to the plurality of first semiconductor chips one by one, and a colloidal plastic package material is arranged in a preset area in each cavity; and inverting and pressing the plastic packaging mold provided with the colloidal plastic packaging material on the first surface of the semiconductor wafer to form the plastic packaging layer.
Further, the manufacturing of the plastic package layer further comprises: and when the plastic package mold is inverted and pressed on the semiconductor wafer, the top surface of the optical coupling area protection ring, which is far away from the first surface, is attached to the bottom of the cavity.
Optionally, the manufacturing the molding layer further includes: before setting up gummy plastic packaging material, every the bottom of cavity sets up dredges the glue film, and dredges the glue film preset regional department and set up gummy plastic packaging material.
Further, the manufacturing of the plastic package layer further comprises: and when the plastic package mold is inverted and pressed on the semiconductor wafer, the top surface of the optical coupling area protection ring, which is far away from the first surface, is attached to the sparse adhesive layer.
Further, after the plastic packaging layer is formed, the plastic packaging mold is removed.
Further, after the plastic package mold is removed, the semiconductor wafer is cut to obtain a plurality of separated chip package assemblies, and each chip package assembly comprises a first semiconductor chip, at least one corresponding second semiconductor chip, an optical coupling area protection ring and a plastic package layer.
Further, after obtaining a plurality of separated chip package assemblies, mounting each chip package assembly on a corresponding package substrate; and mounting a light guiding structure or a laser chip onto the optical coupling interface of the first semiconductor chip.
Further, before the at least one second semiconductor chip and the optical coupling region guard ring are respectively fixed on the non-optical coupling region of the first surface of the corresponding first semiconductor chip, a plurality of conductive channels are manufactured in each first semiconductor chip, and two side surfaces of each conductive channel are respectively exposed from two side surfaces of the first semiconductor chip.
Further, after two side surfaces of each conductive channel are exposed from the surface of the first semiconductor chip, a first conductive bump is manufactured on one exposed side surface of each conductive channel.
Further, after a first conductive bump is manufactured on the exposed side surface of each conductive channel, temporarily bonding the side surface of each first semiconductor chip close to the first conductive bump with a second bearing substrate; and manufacturing a second conductive bump on the other exposed side surface of each conductive channel of each first semiconductor chip.
Further, after a second conductive bump is manufactured on the other side surface of each exposed conductive channel of each first semiconductor chip, temporarily bonding one side surface of the first semiconductor chip close to the second conductive bump with a first bearing substrate; and debonding the second carrier substrate.
Optionally, the first semiconductor chip is a photonic integrated circuit chip and the second semiconductor chip is an electronic integrated circuit chip.
Optionally, the optical coupling region protection ring is a hollow tubular structure or a cup-shaped structure having a hollow and a cap.
Optionally, the optical coupling region guard ring comprises at least one of metal, ceramic, silicon.
According to another aspect of the embodiments of the present invention, there is also provided a package structure, including: a first semiconductor chip having first and second opposite surfaces, a light coupling region and a non-light coupling region surrounding the light coupling region being provided on the first surface, the light coupling region being provided with a light coupling interface; the at least one second semiconductor chip and the optical coupling area protection ring are respectively fixed on the non-optical coupling area of the first surface, wherein the optical coupling area protection ring surrounds the optical coupling area; and the plastic packaging layer coats the outer side surfaces, far away from the optical coupling area, of the at least one second semiconductor chip and the optical coupling area protection ring, and does not cover the area occupied by the optical coupling area protection ring.
Further, in a direction perpendicular to the first surface, a top surface of the optical coupling region protection ring away from the first surface is flush with a top surface of the molding layer away from the first surface.
Further, a top surface of the at least one second semiconductor chip away from the first surface is exposed outside the molding layer, and in a direction perpendicular to the first surface, a top surface of the optical coupling region guard ring away from the first surface is flush with a top surface of the at least one second semiconductor chip away from the first surface.
Optionally, the optical coupling region protection ring is a hollow tubular structure or a cup-shaped structure having a hollow structure and a cap.
Optionally, the optical coupling region guard ring comprises at least one of metal, ceramic, silicon.
Optionally, when the optical coupling region protection ring is cup-shaped, the hollow structure and the top cover are bonded by an adhesive layer.
The manufacturing method of the packaging structure and the packaging structure provided by the embodiment of the invention can ensure that the upper surface of the optical coupling area is not covered by the plastic packaging layer, protect the optical coupling interface in the optical coupling area from being polluted by organic matters in the plastic packaging layer, ensure the surface purity of the optical coupling area, and be beneficial to maintaining higher coupling efficiency between the subsequent optical coupling interface and the optical fiber array.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other embodiments based on these drawings without creative efforts.
Fig. 1 is a flow chart of a method of fabricating a package structure according to an embodiment of the invention.
Fig. 2A-2C are schematic diagrams illustrating a manufacturing process of a method for manufacturing a package structure according to an embodiment of the invention.
Fig. 3 is a schematic plan view of a first semiconductor chip according to an embodiment of the present invention.
Fig. 4 is a schematic top view of a package structure with a semiconductor chip according to an embodiment of the invention.
Fig. 5A-5B are schematic diagrams illustrating a manufacturing process for manufacturing a molding layer according to an embodiment of the invention.
Fig. 6A-6B are schematic views illustrating a manufacturing process for manufacturing a molding layer according to another embodiment of the invention.
Fig. 7-8 are schematic views illustrating steps of a method for manufacturing a package structure according to an embodiment of the invention.
Fig. 9 is a schematic diagram of a chip scale package structure according to an embodiment of the invention.
Fig. 10 is a schematic diagram illustrating a connection between a chip scale package structure and a package substrate according to an embodiment of the invention.
Fig. 11A to fig. 11C are schematic views illustrating a manufacturing process of a method for manufacturing a package structure according to another embodiment of the invention.
Detailed Description
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. A chip in this context may include a bare chip. The chronological order illustrated herein represents an exemplary scenario when referring to the method steps, but does not represent a limitation of the chronological order. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Aiming at the problems of incapability of plastic package, poor package interconnection reliability, large package area, poor performance and the like of the existing photoelectric chip package mode, the embodiment of the invention provides a manufacturing method of a package structure with an optical interconnection interface.
The present invention will be described in further detail with reference to the accompanying drawings and detailed description, in order to make the objects, features and advantages thereof more comprehensible.
Fig. 1 is a flow chart of a method of fabricating a package structure according to an embodiment of the invention. The manufacturing method of the packaging structure comprises the following steps:
s101, providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of first semiconductor chips, each first semiconductor chip is provided with a first surface and a second surface which are opposite, a light coupling area and a non-light coupling area surrounding the light coupling area are arranged on the first surface, and a light coupling interface is arranged in the light coupling area;
s102, for each first semiconductor chip, providing at least one second semiconductor chip and an optical coupling area guard ring corresponding to the first semiconductor chip, and fixing the at least one second semiconductor chip and the optical coupling area guard ring on the non-optical coupling area of the first surface of the first semiconductor chip, respectively, wherein the optical coupling area guard ring surrounds the optical coupling area;
s103, manufacturing a plastic package layer, wherein the plastic package layer covers the at least one second semiconductor chip and the outer surface of the optical coupling area protection ring, which is far away from the optical coupling area, and does not cover the area occupied by the optical coupling area protection ring.
Fig. 2A-2C are schematic views illustrating a manufacturing process of a method for manufacturing a package structure according to an embodiment of the invention. Fig. 3 is a schematic plan view of a first semiconductor chip according to an embodiment of the present invention. Fig. 4 is a schematic top view of a package structure with a semiconductor chip according to an embodiment of the invention. The following describes an embodiment of the present invention in detail with reference to fig. 2A to 2C, fig. 3, and fig. 4.
In the embodiment of the present invention, the first semiconductor chip 102 is an optical chip (photonic integrated circuit chip, PIC) which uses photons as an information carrier for information processing and data transmission, and the second semiconductor chip 103 is an electrical chip (electronic integrated circuit chip, EIC) which uses electrons as an information carrier for information processing and data transmission, such as a silicon-based electrical chip, a germanium-based electrical chip, or a compound semiconductor electrical chip, and the integration of the optical chip and the electrical chip can be realized by stacking the first semiconductor chip 102 and the second semiconductor chip 103.
For example, referring to fig. 2A, a first carrier substrate 200 and a semiconductor wafer 100 having a plurality of first semiconductor chips 102 on the first carrier substrate 200 are provided, each first semiconductor chip 102 has a first surface 102A and a second surface 102b opposite to each other, and the second surface 102b is temporarily bonded to the first carrier substrate 200 through a bonding adhesive 201.
Illustratively, as shown in fig. 3, a light coupling region 1024 and a non-light coupling region 1025 surrounding the light coupling region 1024 are disposed on the first surface 102a of the first semiconductor chip 102, a light coupling interface 104 is disposed in the light coupling region 1024, and light provided by an external light source can be input into the light coupling interface 104 through a Fiber Array (FA), for example, coupled into the first semiconductor chip 102 through a grating coupler in the light coupling interface 104. In other embodiments, other optical interconnection interfaces or devices for transmitting optical signals may be correspondingly disposed in the optical coupling interface 104.
As shown in fig. 2B to 2C and fig. 4, at least one second semiconductor chip 103 and an optical coupling region guard ring 400 corresponding to the first semiconductor chip 102 are provided for each first semiconductor chip 102, and the at least one second semiconductor chip 103 and the optical coupling region guard ring 400 are fixed to the non-optical coupling region 1025 on the first surface 102a of the first semiconductor chip 102, respectively, for example, by soldering or other methods; wherein the optical coupling region guard ring 400 surrounds the optical coupling region 1024.
It should be noted that, in the embodiment of the present invention, it is illustrated that one second semiconductor chip 103 is formed above the first semiconductor chip 102, in practical use, there may be more than one second semiconductor chips 103, for example, 2, 3, 4 or more, and the second semiconductor chips 103 may be flexibly selected according to practical needs.
Since the molding compound layer and the like include organic materials, organic contact with the optical coupling region 1024 may cause organic residue, which may affect the coupling efficiency of the optical coupling interface 104, cause serious optical loss, and affect the operation of the first semiconductor chip 102. To form protection for the optical coupling interface 104 in the optical coupling region 1024, embodiments of the present invention fabricate an optical coupling region guard ring 400 around the optical coupling region 1024 at the periphery of the optical coupling region 1024. Illustratively, the optical coupling region protection ring 400 is a hollow tubular structure or a cup-shaped structure having a hollow structure and a top cover, and subsequently, when a molding compound layer is manufactured, due to the existence of the optical coupling region protection ring 400, the upper surface of the optical coupling region can be uncovered by the molding compound layer, so that the molding compound layer only covers the at least one second semiconductor chip 103 and the outer side surface of the optical coupling region protection ring 400 away from the optical coupling region 1024 and covers the non-optical coupling region 1025 except for the region occupied by the optical coupling region protection ring 400, and the surface purity of the optical coupling region 1024 is ensured while the optical coupling interface 104 in the optical coupling region 1024 is protected from being contaminated by organic matters in the molding compound layer, which is beneficial for the subsequent optical coupling interface 104 to maintain high coupling efficiency with the optical fiber array. In addition, due to the existence of the optical coupling region protection ring 400, the problem that in a traditional plastic package process, since a plastic package layer covers the optical coupling region 1024, laser hole opening processing needs to be performed on the plastic package layer in the later period to expose the optical coupling region 1024 is also avoided.
It should be understood that if the optical coupling region protection ring 400 is a cup-shaped structure with a hollow top cap, after the molding layer is manufactured, the top cap thereof is removed to expose the optical coupling region 1024, so as to facilitate the subsequent input of the light from the external light source into the first semiconductor chip 102 through the optical coupling interface 104. When the coupling region protection ring 400 is a cup-shaped structure, the hollow structure and the top cap are bonded by an adhesive layer, and the adhesive layer can be removed by illumination, heating, and the like, so that the optical coupling region 1024 can be protected better, and the optical coupling region 1024 can be conveniently packaged subsequently. If the optical coupling region protection ring 400 is a tubular structure having a hollow core, the optical coupling region 1024 can be directly exposed.
Optionally, the optical coupling region guard ring 400 comprises at least one of metal, ceramic, silicon. Preferably, the optical coupling region guard ring 400 is made of a material having a thermal expansion coefficient and a rigidity similar to those of the first semiconductor chip 102, such as ceramic or silicon. The optical coupling region protection ring 400 is fixed on the non-optical coupling region 1025 on the first surface 102a of the first semiconductor chip 102 by means of substrate bonding or adhesive bonding.
Alternatively, the order of fixing the at least one second semiconductor chip 103 and the optical coupling region guard ring 400 may not be limited.
Further, in a direction perpendicular to the first surface 102a, a top surface of the optical coupling region guard ring 400 away from the first surface 102a is flush with a top surface of the at least one second semiconductor chip 103 away from the first surface 102 a.
Fig. 5A-5B are schematic diagrams illustrating a manufacturing process for manufacturing a molding layer according to an embodiment of the invention.
As shown in fig. 5A, in an embodiment of the present invention, the fabricating the molding layer includes: providing a plastic package mold 800, wherein the plastic package mold 800 is provided with a plurality of U-shaped cavities 801 corresponding to the plurality of first semiconductor chips 102 one by one, and a colloidal plastic package material 1061, such as a plastic package adhesive, is disposed at a preset area in each cavity 801; then, the plastic package mold 800 provided with the colloidal plastic package material 1061 is inverted and pressed on a surface of the semiconductor wafer 100 away from the first carrier substrate 200 to form the plastic package layer 106.
Exemplarily, the preset area is an area where the plastic package adhesive is disposed outside the corresponding optical coupling area protection ring 400 and the optical coupling area 1024 of each cavity 801, and by using the characteristic that the plastic package adhesive is not prone to fluid movement and gravity drop at will, in the process of inverting and pressing the plastic package mold 800 provided with the plastic package adhesive, the plastic package adhesive can be uniformly filled into a gap to be filled, and the plastic package adhesive can also be prevented from dropping in the optical coupling area 1024, so that the optical coupling interface 104 in the optical coupling area 1024 is protected from being contaminated by the plastic package adhesive. And heating and curing the plastic package adhesive to obtain the 3D chip stacked package structure with the optical coupling region 1024 not covered by the plastic package layer 106.
For example, the inner wall of the U-shaped cavity is smooth, for example, the inner configuration of the U-shaped cavity may be designed according to the shape of the plastic package layer to be formed, and the embodiment of the invention is not limited herein.
As shown in fig. 5B, when the mold chase 800 is inverted and bonded onto the semiconductor wafer 100, a top surface of the optical coupling region protection ring 400 away from the first surface 102a is attached to a bottom of the cavity 801, so that after the gel-like molding compound 1061 is cured to form the molding layer 106, a top surface of the optical coupling region protection ring 400 away from the first surface 102a is flush with a top surface of the molding layer 106 away from the first surface 102a in a direction perpendicular to the first surface 102 a. Moreover, in the embodiment of the present invention, since the top surface of the optical coupling region protection ring 400 away from the first surface 102a is flush with the top surface of the at least one second semiconductor chip 103 away from the first surface 102a, after the molding compound layer is formed, the top surface of the at least one second semiconductor chip 103 away from the first surface 102a can be exposed outside the molding compound layer 106, which is not only beneficial to reducing the volume of the package structure, but also beneficial to dissipating heat of the at least one second semiconductor chip 103. Meanwhile, the subsequent process of thinning the plastic packaging layer 106 is also omitted, so that the top surface of the at least one second semiconductor chip 103 far away from the first surface 102a is exposed, and the manufacturing process flow is simplified and the manufacturing cost is reduced.
Fig. 6A-6B are schematic views illustrating a manufacturing process for manufacturing a molding layer according to another embodiment of the invention.
As shown in fig. 6A, in another embodiment of the present invention, compared to fig. 5A, the fabricating the molding layer further includes: before the colloidal plastic package material 1061 is arranged, an adhesive thinning layer 901 is arranged at the bottom of each cavity 801, and the colloidal plastic package material 1061 is arranged at the preset area of the adhesive thinning layer 901.
As shown in fig. 6B, when the plastic mold 800 is inverted and pressed on the semiconductor wafer 100, the top surface of the optical coupling region guard ring 400 away from the first surface 102a is attached to the adhesive dispensing layer 901.
Exemplarily, the preset region refers to a region where plastic-sealing glue is disposed outside the corresponding optical coupling region protection ring 400 and the optical coupling region 1024 of each cavity 801. Illustratively, the hydrophobic layer 901 is made of teflon or the like, and the hydrophobic layer 901 has the hydrophobic property, that is, has repellency to colloid, so that after the colloidal plastic package material 1061 is disposed at the preset area of the hydrophobic layer 901 and after the plastic package mold 800 provided with the plastic package glue is inverted and pressed, the plastic package glue is prevented from adhering to the surface of the hydrophobic layer 901 and the side wall close to the bottom of the cavity 801, and the plastic package glue is conveniently separated from the plastic package mold 800 after being cured.
Fig. 7-8 are schematic views illustrating steps of a method for manufacturing a package structure according to an embodiment of the invention. Fig. 9 is a schematic diagram of a chip scale package structure according to an embodiment of the invention. Fig. 10 is a schematic diagram illustrating a connection between a chip scale package structure and a package substrate according to an embodiment of the invention.
As shown in fig. 7, the method for manufacturing the package structure further includes: after the plastic package layer 106 is formed, the plastic package mold 800 is removed.
As shown in fig. 8, the method for manufacturing the package structure further includes: after removing the plastic package mold 800, the first carrier substrate 200 is debonded.
Further, after the first carrier substrate 200 is debonded, the semiconductor wafer 100 is front-cut, that is, cut on the side of the semiconductor wafer 100 having the molding layer 106, so as to obtain a plurality of separated chip package assemblies 1000; as shown in fig. 9, each of the chip package assemblies 1000 has a first semiconductor chip 102, at least one corresponding second semiconductor chip 103, a light coupling area guard ring 400, and a molding layer 106. At this time, the presence of the molding layer 106 increases the surface strength of the semiconductor wafer 100, and therefore, even when the semiconductor wafer 100 is subjected to front-side dicing, the risk of chipping of the semiconductor wafer 100 due to dicing chipping hardly occurs.
Subsequently, as shown in fig. 10, each of the chip package assemblies 1000 is mounted on the corresponding package substrate 700. Specifically, the second conductive bump 1023 on the chip package assembly 1000 having at least one second conductive bump 1023 is bonded to an electrical connection point (not shown) on the package substrate 700. Discrete devices such as capacitors, resistors, inductors, etc. may be additionally mounted or integrated on the package substrate 700 according to actual needs.
With continued reference to fig. 10, after at least one chip package assembly 1000 having second conductive bumps 1023 is bonded to electrical connection points on the package substrate 700, a light guide structure 600 or laser chip is mounted to the optical coupling interface 104.
Illustratively, the light guide structure 600 is a Fiber Array (FA). Alternatively, the light guiding structure 600 may be a prism, which guides the laser beam to the light coupling structure 104 by means of laser integration, specifically, the laser beam emitted by the laser chip passes through a lens and is incident to the prism, and the prism couples the laser beam into the first semiconductor chip 102 through the light coupling interface 104.
Alternatively, the laser chip may be directly mounted over the optical coupling interface 104, such that a laser beam emitted by the laser chip is directed at the optical coupling interface 104, and the laser beam may be directly coupled to the first semiconductor chip 102. The laser chip is mounted above the optical coupling interface 104, which can greatly simplify the device structure and improve the integration level.
Fig. 11A to fig. 11C are schematic views illustrating a manufacturing process of a method for manufacturing a package structure according to another embodiment of the invention.
As shown in fig. 11A to fig. 11C, the method for manufacturing a package structure according to the embodiment of the present invention further includes: before the at least one second semiconductor chip 103 and the optical coupling area guard ring 400 are respectively fixed on the non-optical coupling area 1025 of the first surface 102a of the corresponding first semiconductor chip 102, a plurality of conductive channels 1021 are manufactured in each first semiconductor chip 102, and both side surfaces of each conductive channel 1021 are respectively exposed from both side surfaces of the first semiconductor chip 102. The conductive via 1021 may be formed by connecting multiple conductive layers and manufactured separately in multiple steps.
Specifically, when the first semiconductor chip 102 is a Silicon-based optical chip, a plurality of conductive vias are formed in the substrate of the first semiconductor chip 102, and the conductive vias may be formed by a "Through Silicon Via" (TSV) technology, which is a high-density packaging technology and is gradually replacing the mature wire bonding technology in the current process, and is considered as a fourth-generation packaging technology. The TSV technology realizes vertical electrical interconnection of the through-silicon vias by filling conductive substances such as copper, tungsten, polysilicon, and the like. The through silicon via technology can reduce the interconnection length, reduce signal delay, reduce capacitance/inductance, realize low power consumption and high-speed communication between chips, increase broadband and realize miniaturization of device integration through vertical interconnection. The TSV process may include deep silicon etching to form a micro-or blind via, deposition of an insulating layer/barrier layer/seed layer, deep hole filling, chemical mechanical polishing, thinning, and redistribution lead preparation, the process method for forming a conductive via in an optical chip includes, but is not limited to, laser etching, deep reactive ion etching, and the like, and then filling a conductive material (e.g., metal) by using a process such as deep hole filling after the conductive via is formed. The present invention is not described in detail herein.
As shown in fig. 11A, after exposing both side surfaces of each of the conductive vias 1021 from the surface of the first semiconductor chip 102, a first conductive bump 1022 is formed on the exposed side surface of each of the conductive vias 101. The first conductive bump 1022 is, for example, a pad (metal bump) or a solder ball. A first conductive bump 1022 is formed on the exposed surface of each conductive via 1021 to electrically connect the conductive via 1021 with an external electrical connection point. The first surface 102a of the first semiconductor chip 102 having the at least one first conductive bump 1022 is temporarily bonded to the second carrier substrate 300 by the bonding paste 301.
As shown in fig. 11B, after the first semiconductor chip 102 having at least one first conductive bump 1022 is temporarily bonded to the second carrier substrate 300, a second conductive bump 1023 is formed on the other side surface of the first semiconductor chip 102 where each of the conductive vias 1021 is exposed.
As shown in fig. 11C, after a second conductive bump 1023 is formed on the other side surface of the first semiconductor chip 102 exposed by each conductive channel 1021, the second surface 102b of the first semiconductor chip 102 having at least one second conductive bump 1023 is temporarily bonded to the first carrier substrate 200 through the bonding adhesive 201, and the second carrier substrate 300 is debonded, so as to obtain the structure shown in fig. 2A, which is composed of the first carrier substrate 200 and the semiconductor wafer 100 including a plurality of first semiconductor chips.
Specifically, as shown in fig. 2A to fig. 2C, a plurality of third conductive bumps 1032 are formed on one side of the second semiconductor chip 103, wherein the plurality of third conductive bumps 1032 correspond to the first conductive bumps 1022 on each of the conductive channels 1021 in a one-to-one manner. Each of the third conductive bumps 1032 is bonded to the corresponding first conductive bump 1022, so as to fixedly connect the second semiconductor chip 103 and the first semiconductor chip 102 together.
In the embodiment of the present invention, the second semiconductor chip 103 is flip-chip bonded to the first semiconductor chip 102. Each of the third conductive bumps 1032 is bonded to the corresponding first conductive bump 1022, and the Bonding manner may be Thermal Compression Bonding (TCB), reflow soldering, laser Bonding, or direct metal Bonding. If the second semiconductor chip 103 has a solder ball or a bump, an underfill process is required. It is to be understood that a plurality of second semiconductor chips 103 may also be connected to the same first semiconductor chip 102 according to actual needs.
It should be noted that the one-to-one correspondence between the plurality of third conductive bumps 1032 and the first conductive bumps 1022 on each of the conductive vias 1021 is for performing one-to-one connection when connecting electrical signal terminals, and is not completely limited to one-to-one correspondence between upper and lower projection positions. It should be understood that when the plurality of third conductive bumps 1032 correspond to the first conductive bumps 1022 and the lower projection positions on each of the conductive channels 1021, the required connection distance is shortest when the first semiconductor chip 102 and the second semiconductor chip 10 are vertically interconnected, and therefore, the problems of higher impedance, limited current passing capability and the like caused by too long connection lines between the first semiconductor chip 102 and the second semiconductor chip 103 can be avoided, so that the loss of the upper and lower interconnections between the first semiconductor chip 102 and the second semiconductor chip 103 is reduced.
According to another aspect of the embodiments of the present invention, a package structure is also provided.
With continuing reference to fig. 3 and fig. 9, a package structure 1000 according to an embodiment of the present invention includes: the semiconductor chip comprises a first semiconductor chip 102, at least one second semiconductor chip 103, an optical coupling region protection ring 400 and a plastic packaging layer 106, wherein the first semiconductor chip 102 is provided with a first surface 102a and a second surface 102b which are opposite, an optical coupling region 1024 and a non-optical coupling region 1025 which surrounds the optical coupling region 1024 are arranged on the first surface 102a, and an optical coupling interface 104 is arranged in the optical coupling region 1024; the at least one second semiconductor chip 103 and the optical coupling area guard ring 400 are respectively fixed on the non-optical coupling area 1025 of the first surface 102 a; wherein the optical coupling region guard ring 400 surrounds the optical coupling region 1024; the molding compound layer 106 covers the at least one second semiconductor chip 103 and the outer surface of the optical coupling region protection ring 400 away from the optical coupling region 1024 and does not cover the area occupied by the optical coupling region protection ring 400.
Further, in a direction perpendicular to the first surface 102a, a top surface of the optical coupling region protection ring 400 away from the first surface 102a is flush with a top surface of the molding layer 106 away from the first surface 102 a.
Further, a top surface of the at least one second semiconductor chip 103 away from the first surface 102a is exposed outside the molding layer 106, and in a direction perpendicular to the first surface 102a, a top surface of the optical coupling region guard ring 400 away from the first surface 102a is flush with a top surface of the at least one second semiconductor chip 103 away from the first surface 102 a.
Illustratively, the optical coupling region protection ring 400 is a hollow tubular structure or a cup-shaped structure having a hollow and a cap.
Optionally, the optical coupling region guard ring 400 comprises at least one of metal, ceramic, silicon. Preferably, the optical coupling region guard ring 400 is made of a material having a thermal expansion coefficient and a rigidity similar to those of the first semiconductor chip 102, such as ceramic or silicon. The optical coupling region protection ring 400 is fixed on the non-optical coupling region 1025 on the first surface 102a of the first semiconductor chip 102 by means of substrate bonding or adhesive bonding.
As can be seen from the above, the method for manufacturing a package structure and the package structure provided in the embodiments of the present invention includes: the semiconductor wafer comprises a plurality of first semiconductor chips, the plurality of first semiconductor chips on the semiconductor wafer form an integral structure, and for each first semiconductor chip, an optical coupling area protection ring surrounding an optical coupling area is manufactured on a non-optical coupling area of the first semiconductor chip, so that when a plastic package layer is manufactured on the non-optical coupling area of the first semiconductor chip, the upper surface of the optical coupling area is not covered by the plastic package layer, the optical coupling interface in the optical coupling area is protected from being polluted by organic matters in the plastic package layer, the surface purity of the optical coupling area is ensured, and the subsequent optical coupling interface can maintain high coupling efficiency with an optical fiber array.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, which is defined by the appended claims.
Claims (22)
1. A method for fabricating a package structure, the method comprising:
providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of first semiconductor chips, each first semiconductor chip is provided with a first surface and a second surface which are opposite, the first surface is provided with a light coupling area and a non-light coupling area which surrounds the light coupling area, and a light coupling interface is arranged in the light coupling area;
providing at least one second semiconductor chip and an optical coupling region protection ring corresponding to each first semiconductor chip, and fixing the at least one second semiconductor chip and the optical coupling region protection ring on the non-optical coupling region of the first surface of the first semiconductor chip respectively, wherein the optical coupling region protection ring surrounds the optical coupling region;
and manufacturing a plastic package layer, wherein the plastic package layer covers the at least one second semiconductor chip and the outer surface of the optical coupling area protection ring, which is far away from the optical coupling area, and does not cover the area occupied by the optical coupling area protection ring.
2. The method of claim 1, wherein a top surface of the optical coupling region guard ring away from the first surface is flush with a top surface of the at least one second semiconductor chip away from the first surface in a direction perpendicular to the first surface.
3. The method for manufacturing the package structure according to claim 2, wherein the manufacturing the molding layer comprises:
providing a plastic package mold, wherein the plastic package mold is provided with a plurality of U-shaped cavities corresponding to the plurality of first semiconductor chips one by one,
arranging a colloidal plastic packaging material at a preset area in each cavity;
and inverting and pressing the plastic packaging mold provided with the colloidal plastic packaging material on the first surface of the semiconductor wafer to form the plastic packaging layer.
4. The method of manufacturing a package structure according to claim 3, wherein the manufacturing the molding layer further comprises:
and when the plastic package mold is inverted and pressed on the semiconductor wafer, the top surface of the optical coupling area protection ring, which is far away from the first surface, is attached to the bottom of the cavity.
5. The method for manufacturing a package structure according to claim 3, wherein the manufacturing of the molding layer further comprises:
before setting up gummy plastic packaging material, every the bottom of cavity sets up dredges the glue film, and dredges the glue film preset regional department and set up gummy plastic packaging material.
6. The method for manufacturing a package structure according to claim 5, wherein the manufacturing of the molding layer further comprises:
and when the plastic package mold is inverted and pressed on the semiconductor wafer, the top surface of the optical coupling area protection ring, which is far away from the first surface, is attached to the sparse adhesive layer.
7. The method of fabricating the package structure of claim 3, wherein the method further comprises:
and removing the plastic packaging mold after the plastic packaging layer is formed.
8. The method of fabricating the package structure of claim 7, wherein the method further comprises:
and after the plastic package mold is removed, cutting the semiconductor wafer to obtain a plurality of separated chip package assemblies, wherein each chip package assembly comprises a first semiconductor chip, at least one corresponding second semiconductor chip, an optical coupling area protection ring and a plastic package layer.
9. The method of fabricating a package structure according to claim 8, wherein the method further comprises:
after obtaining a plurality of separated chip package assemblies, mounting each chip package assembly on a corresponding package substrate; and
mounting a light guiding structure or a laser chip onto the optical coupling interface of the first semiconductor chip.
10. The method of fabricating the package structure of claim 1, wherein the method further comprises:
before the at least one second semiconductor chip and the optical coupling region protection ring are respectively fixed on the non-optical coupling region of the first surface of the corresponding first semiconductor chip, a plurality of conductive channels are manufactured in each first semiconductor chip, and two side surfaces of each conductive channel are respectively exposed from two side surfaces of the first semiconductor chip.
11. The method of fabricating the package structure of claim 10, wherein the method further comprises:
and after two side surfaces of each conductive channel are exposed from the surface of the first semiconductor chip, manufacturing a first conductive bump on the exposed side surface of each conductive channel.
12. The method of fabricating the package structure of claim 11, wherein the method further comprises:
after a first conductive bump is manufactured on the exposed side surface of each conductive channel, temporarily bonding the side surface of each first semiconductor chip close to the first conductive bump with a second bearing substrate; and the number of the first and second groups,
and manufacturing a second conductive bump on the other exposed side surface of each conductive channel of each first semiconductor chip.
13. The method of fabricating the package structure of claim 12, wherein the method further comprises:
after a second conductive bump is manufactured on the other side surface of each exposed conductive channel of each first semiconductor chip, temporarily bonding one side surface of the first semiconductor chip close to the second conductive bump with a first bearing substrate; and the number of the first and second groups,
and debonding the second bearing substrate.
14. The method of claim 1, wherein the step of forming the package structure comprises the steps of,
the first semiconductor chip is a photonic integrated circuit chip and the second semiconductor chip is an electronic integrated circuit chip.
15. The method of claim 1, wherein the step of forming the package structure comprises the steps of,
the optical coupling region protection ring is a hollow tubular structure or a cup-shaped structure having a hollow and a cap.
16. The method of claim 15, wherein the step of forming the package structure comprises the step of forming a semiconductor package,
the optical coupling region guard ring comprises any one of metal, ceramic, and silicon.
17. A package structure, comprising:
a first semiconductor chip having first and second opposite surfaces, a light coupling region and a non-light coupling region surrounding the light coupling region being provided on the first surface, the light coupling region being provided with a light coupling interface;
the at least one second semiconductor chip and the optical coupling area protection ring are respectively fixed on the non-optical coupling area of the first surface, wherein the optical coupling area protection ring surrounds the optical coupling area;
and the plastic packaging layer covers the at least one second semiconductor chip and the outer surface of the optical coupling area protection ring, which is far away from the optical coupling area, and does not cover the area occupied by the optical coupling area protection ring.
18. The package structure of claim 17,
in a direction perpendicular to the first surface, a top surface of the optical coupling region protection ring away from the first surface is flush with a top surface of the molding layer away from the first surface.
19. The package structure of claim 17,
the top surface of the at least one second semiconductor chip far away from the first surface is exposed outside the plastic packaging layer, and in the direction perpendicular to the first surface, the top surface of the optical coupling area protection ring far away from the first surface is flush with the top surface of the at least one second semiconductor chip far away from the first surface.
20. The package structure of claim 17,
the optical coupling region protection ring is a hollow tubular structure or a cup-shaped structure having a hollow structure and a cap.
21. The package structure of claim 20,
the optical coupling region guard ring comprises at least one material of metal, ceramic, and silicon.
22. The package structure of claim 20, wherein when the optical coupling region protection ring is cup-shaped, the hollow structure and the top cap are bonded by an adhesive layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210272769.3A CN114823358A (en) | 2022-03-18 | 2022-03-18 | Manufacturing method of packaging structure and packaging structure |
| PCT/CN2023/080944 WO2023174186A1 (en) | 2022-03-18 | 2023-03-10 | Manufacturing method for packaging structure, and packaging structure |
| TW112109929A TW202339023A (en) | 2022-03-18 | 2023-03-17 | Method of manufacturing a packaging structure and a packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210272769.3A CN114823358A (en) | 2022-03-18 | 2022-03-18 | Manufacturing method of packaging structure and packaging structure |
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| CN114823358A true CN114823358A (en) | 2022-07-29 |
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| CN202210272769.3A Pending CN114823358A (en) | 2022-03-18 | 2022-03-18 | Manufacturing method of packaging structure and packaging structure |
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| Country | Link |
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| CN (1) | CN114823358A (en) |
| TW (1) | TW202339023A (en) |
| WO (1) | WO2023174186A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023174186A1 (en) * | 2022-03-18 | 2023-09-21 | 上海曦智科技有限公司 | Manufacturing method for packaging structure, and packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20180180808A1 (en) * | 2016-12-22 | 2018-06-28 | Oracle International Corporation | Wafer-level packaged optoelectronic module |
| US11302683B2 (en) * | 2020-04-01 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Optical signal processing package structure |
| CN112034567B (en) * | 2020-09-04 | 2022-07-05 | 华进半导体封装先导技术研发中心有限公司 | Photoelectric chip packaging structure and packaging method thereof |
| CN113241329B (en) * | 2021-04-30 | 2022-06-17 | 杭州光智元科技有限公司 | Three-dimensional packaging method and packaging structure of photoelectric chip |
| CN113960715B (en) * | 2021-12-23 | 2022-03-08 | 杭州光智元科技有限公司 | Manufacturing method of packaging structure and packaging structure |
| CN114823358A (en) * | 2022-03-18 | 2022-07-29 | 上海曦智科技有限公司 | Manufacturing method of packaging structure and packaging structure |
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- 2022-03-18 CN CN202210272769.3A patent/CN114823358A/en active Pending
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2023
- 2023-03-10 WO PCT/CN2023/080944 patent/WO2023174186A1/en unknown
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Cited By (1)
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|---|---|---|---|---|
| WO2023174186A1 (en) * | 2022-03-18 | 2023-09-21 | 上海曦智科技有限公司 | Manufacturing method for packaging structure, and packaging structure |
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| TW202339023A (en) | 2023-10-01 |
| WO2023174186A1 (en) | 2023-09-21 |
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